]> Git Repo - J-u-boot.git/blame - board/netphone/netphone.c
projects / J-u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
* Patches by Pantelis Antoniou, 30 Mar 2004:
[J-u-boot.git] / board / netphone / netphone.c
CommitLineData
04a85b3b
WD		 1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Pantelis Antoniou, Intracom S.A., [email protected]
26 * U-Boot port on NetTA4 board
27 */
28
29#include <common.h>
30#include <miiphy.h>
31#include <sed156x.h>
32
33#include "mpc8xx.h"
34
35#ifdef CONFIG_HW_WATCHDOG
36#include <watchdog.h>
37#endif
38
39/****************************************************************/
40
41/* some sane bit macros */
42#define _BD(_b) (1U << (31-(_b)))
43#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
44
45#define _BW(_b) (1U << (15-(_b)))
46#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
47
48#define _BB(_b) (1U << (7-(_b)))
49#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
50
51#define _B(_b) _BD(_b)
52#define _BR(_l, _h) _BDR(_l, _h)
53
54/****************************************************************/
55
56/*
57 * Check Board Identity:
58 *
59 * Return 1 always.
60 */
61
62int checkboard(void)
63{
64 printf ("Intracom NetPhone\n");
65 return (0);
66}
67
68/****************************************************************/
69
70#define _NOT_USED_ 0xFFFFFFFF
71
72/****************************************************************/
73
74#define CS_0000 0x00000000
75#define CS_0001 0x10000000
76#define CS_0010 0x20000000
77#define CS_0011 0x30000000
78#define CS_0100 0x40000000
79#define CS_0101 0x50000000
80#define CS_0110 0x60000000
81#define CS_0111 0x70000000
82#define CS_1000 0x80000000
83#define CS_1001 0x90000000
84#define CS_1010 0xA0000000
85#define CS_1011 0xB0000000
86#define CS_1100 0xC0000000
87#define CS_1101 0xD0000000
88#define CS_1110 0xE0000000
89#define CS_1111 0xF0000000
90
91#define BS_0000 0x00000000
92#define BS_0001 0x01000000
93#define BS_0010 0x02000000
94#define BS_0011 0x03000000
95#define BS_0100 0x04000000
96#define BS_0101 0x05000000
97#define BS_0110 0x06000000
98#define BS_0111 0x07000000
99#define BS_1000 0x08000000
100#define BS_1001 0x09000000
101#define BS_1010 0x0A000000
102#define BS_1011 0x0B000000
103#define BS_1100 0x0C000000
104#define BS_1101 0x0D000000
105#define BS_1110 0x0E000000
106#define BS_1111 0x0F000000
107
108#define A10_AAAA 0x00000000
109#define A10_AAA0 0x00200000
110#define A10_AAA1 0x00300000
111#define A10_000A 0x00800000
112#define A10_0000 0x00A00000
113#define A10_0001 0x00B00000
114#define A10_111A 0x00C00000
115#define A10_1110 0x00E00000
116#define A10_1111 0x00F00000
117
118#define RAS_0000 0x00000000
119#define RAS_0001 0x00040000
120#define RAS_1110 0x00080000
121#define RAS_1111 0x000C0000
122
123#define CAS_0000 0x00000000
124#define CAS_0001 0x00010000
125#define CAS_1110 0x00020000
126#define CAS_1111 0x00030000
127
128#define WE_0000 0x00000000
129#define WE_0001 0x00004000
130#define WE_1110 0x00008000
131#define WE_1111 0x0000C000
132
133#define GPL4_0000 0x00000000
134#define GPL4_0001 0x00001000
135#define GPL4_1110 0x00002000
136#define GPL4_1111 0x00003000
137
138#define GPL5_0000 0x00000000
139#define GPL5_0001 0x00000400
140#define GPL5_1110 0x00000800
141#define GPL5_1111 0x00000C00
142#define LOOP 0x00000080
143
144#define EXEN 0x00000040
145
146#define AMX_COL 0x00000000
147#define AMX_ROW 0x00000020
148#define AMX_MAR 0x00000030
149
150#define NA 0x00000008
151
152#define UTA 0x00000004
153
154#define TODT 0x00000002
155
156#define LAST 0x00000001
157
158/* #define CAS_LATENCY 3 */
159#define CAS_LATENCY 2
160
161const uint sdram_table[0x40] = {
162
163#if CAS_LATENCY == 3
164 /* RSS */
165 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
166 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
167 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
168 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
169 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
170 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
171 _NOT_USED_, _NOT_USED_,
172
173 /* RBS */
174 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
175 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
176 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
177 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
178 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
179 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
180 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
181 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
182 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
183 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
184
185 /* WSS */
186 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
187 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
188 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
189 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
190 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
191 _NOT_USED_, _NOT_USED_, _NOT_USED_,
192
193 /* WBS */
194 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
195 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
196 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
197 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
198 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
199 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
200 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
201 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
202 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
203 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
204 _NOT_USED_, _NOT_USED_, _NOT_USED_,
205#endif
206
207#if CAS_LATENCY == 2
208 /* RSS */
209 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
210 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
211 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
212 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
213 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
214 _NOT_USED_,
215 _NOT_USED_, _NOT_USED_,
216
217 /* RBS */
218 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
219 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
220 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
221 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
222 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
223 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
224 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
225 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
226 _NOT_USED_,
227 _NOT_USED_, _NOT_USED_, _NOT_USED_,
228 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
229
230 /* WSS */
231 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
232 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
233 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
234 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
235 _NOT_USED_,
236 _NOT_USED_, _NOT_USED_,
237 _NOT_USED_,
238
239 /* WBS */
240 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
241 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
242 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
243 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
244 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
245 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
246 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
247 _NOT_USED_,
248 _NOT_USED_, _NOT_USED_, _NOT_USED_,
249 _NOT_USED_, _NOT_USED_, _NOT_USED_,
250 _NOT_USED_, _NOT_USED_,
251
252#endif
253
254 /* UPT */
255 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
256 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
257 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
258 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
259 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
260 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
261 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
262 _NOT_USED_, _NOT_USED_,
263
264 /* EXC */
265 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
266 _NOT_USED_,
267
268 /* REG */
269 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
270 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
271};
272
273/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
274/* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
275#define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
276
277/* 8 */
278#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
279 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
280 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
281
282void check_ram(unsigned int addr, unsigned int size)
283{
284 unsigned int i, j, v, vv;
285 volatile unsigned int *p;
286 unsigned int pv;
287
288 p = (unsigned int *)addr;
289 pv = (unsigned int)p;
290 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
291 *p++ = pv;
292
293 p = (unsigned int *)addr;
294 for (i = 0; i < size / sizeof(unsigned int); i++) {
295 v = (unsigned int)p;
296 vv = *p;
297 if (vv != v) {
298 printf("%p: read %08x instead of %08x\n", p, vv, v);
299 hang();
300 }
301 p++;
302 }
303
304 for (j = 0; j < 5; j++) {
305 switch (j) {
306 case 0: v = 0x00000000; break;
307 case 1: v = 0xffffffff; break;
308 case 2: v = 0x55555555; break;
309 case 3: v = 0xaaaaaaaa; break;
310 default:v = 0xdeadbeef; break;
311 }
312 p = (unsigned int *)addr;
313 for (i = 0; i < size / sizeof(unsigned int); i++) {
314 *p = v;
315 vv = *p;
316 if (vv != v) {
317 printf("%p: read %08x instead of %08x\n", p, vv, v);
318 hang();
319 }
320 *p = ~v;
321 p++;
322 }
323 }
324}
325
326long int initdram(int board_type)
327{
328 volatile immap_t *immap = (immap_t *) CFG_IMMR;
329 volatile memctl8xx_t *memctl = &immap->im_memctl;
330 long int size;
331
332 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
333
334 /*
335 * Preliminary prescaler for refresh
336 */
337 memctl->memc_mptpr = MPTPR_PTP_DIV8;
338
339 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
340
341 /*
342 * Map controller bank 3 to the SDRAM bank at preliminary address.
343 */
344 memctl->memc_or3 = CFG_OR3_PRELIM;
345 memctl->memc_br3 = CFG_BR3_PRELIM;
346
347 memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
348
349 udelay(200);
350
351 /* perform SDRAM initialisation sequence */
352 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
353 udelay(1);
354
355 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
356 udelay(1);
357
358 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
359 udelay(1);
360
361 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
362
363 udelay(10000);
364
365 {
366 u32 d1, d2;
367
368 d1 = 0xAA55AA55;
369 *(volatile u32 *)0 = d1;
370 d2 = *(volatile u32 *)0;
371 if (d1 != d2) {
372 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
373 hang();
374 }
375
376 d1 = 0x55AA55AA;
377 *(volatile u32 *)0 = d1;
378 d2 = *(volatile u32 *)0;
379 if (d1 != d2) {
380 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
381 hang();
382 }
383 }
384
385 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
386
387#if 0
388 printf("check 0\n");
389 check_ram(( 0 << 20), (2 << 20));
390 printf("check 16\n");
391 check_ram((16 << 20), (2 << 20));
392 printf("check 32\n");
393 check_ram((32 << 20), (2 << 20));
394 printf("check 48\n");
395 check_ram((48 << 20), (2 << 20));
396#endif
397
398 if (size == 0) {
399 printf("SIZE is zero: LOOP on 0\n");
400 for (;;) {
401 *(volatile u32 *)0 = 0;
402 (void)*(volatile u32 *)0;
403 }
404 }
405
406 return size;
407}
408
409/* ------------------------------------------------------------------------- */
410
411void reset_phys(void)
412{
413 int phyno;
414 unsigned short v;
415
416 udelay(10000);
417 /* reset the damn phys */
418 mii_init();
419
420 for (phyno = 0; phyno < 32; ++phyno) {
421 miiphy_read(phyno, PHY_PHYIDR1, &v);
422 if (v == 0xFFFF)
423 continue;
424 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
425 udelay(10000);
426 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
427 udelay(10000);
428 }
429}
430
431/* ------------------------------------------------------------------------- */
432
433/* GP = general purpose, SP = special purpose (on chip peripheral) */
434
435/* bits that can have a special purpose or can be configured as inputs/outputs */
436#define PA_GP_INMASK 0
437#define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
438#define PA_SP_MASK 0
439#define PA_ODR_VAL 0
440#define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
441#define PA_SP_DIRVAL 0
442
443#define PB_GP_INMASK _B(28)
444#define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
445#define PB_SP_MASK (_BR(22, 25))
446#define PB_ODR_VAL 0
447#define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
448#define PB_SP_DIRVAL 0
449
450#define PC_GP_INMASK _BW(12)
451#define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
452#define PC_SP_MASK 0
453#define PC_SOVAL 0
454#define PC_INTVAL 0
455#define PC_GP_OUTVAL (_BW(10) | _BW(11))
456#define PC_SP_DIRVAL 0
457
458#define PE_GP_INMASK _B(31)
459#define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
460#define PE_SP_MASK 0
461#define PE_ODR_VAL 0
462#define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
463#define PE_SP_DIRVAL 0
464
465int board_early_init_f(void)
466{
467 volatile immap_t *immap = (immap_t *) CFG_IMMR;
468 volatile iop8xx_t *ioport = &immap->im_ioport;
469 volatile cpm8xx_t *cpm = &immap->im_cpm;
470 volatile memctl8xx_t *memctl = &immap->im_memctl;
471
472 /* NAND chip select */
473 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
474 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
475
476 /* DSP chip select */
477 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
478 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
479
480 /* External register chip select */
481 memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
482 memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
483
484 memctl->memc_br5 &= ~BR_V;
485 memctl->memc_br6 &= ~BR_V;
486 memctl->memc_br7 &= ~BR_V;
487
488 ioport->iop_padat = PA_GP_OUTVAL;
489 ioport->iop_paodr = PA_ODR_VAL;
490 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
491 ioport->iop_papar = PA_SP_MASK;
492
493 cpm->cp_pbdat = PB_GP_OUTVAL;
494 cpm->cp_pbodr = PB_ODR_VAL;
495 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
496 cpm->cp_pbpar = PB_SP_MASK;
497
498 ioport->iop_pcdat = PC_GP_OUTVAL;
499 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
500 ioport->iop_pcso = PC_SOVAL;
501 ioport->iop_pcint = PC_INTVAL;
502 ioport->iop_pcpar = PC_SP_MASK;
503
504 cpm->cp_pedat = PE_GP_OUTVAL;
505 cpm->cp_peodr = PE_ODR_VAL;
506 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
507 cpm->cp_pepar = PE_SP_MASK;
508
509 return 0;
510}
511
512#if (CONFIG_COMMANDS & CFG_CMD_NAND)
513
514#include <linux/mtd/nand.h>
515
516extern ulong nand_probe(ulong physadr);
517extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
518
519void nand_init(void)
520{
521 unsigned long totlen;
522
523 totlen = nand_probe(CFG_NAND_BASE);
524 printf ("%4lu MB\n", totlen >> 20);
525}
526#endif
527
528#ifdef CONFIG_HW_WATCHDOG
529
530void hw_watchdog_reset(void)
531{
532 /* XXX add here the really funky stuff */
533}
534
535#endif
536
537#ifdef CONFIG_SHOW_ACTIVITY
538
539static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
540
541/* called from timer interrupt every 1/CFG_HZ sec */
542void board_show_activity(ulong timestamp)
543{
544 if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
545 --left_to_poll;
546}
547
548extern void phone_console_do_poll(void);
549
550static void do_poll(void)
551{
552 unsigned int base;
553
554 while (left_to_poll <= 0) {
555 phone_console_do_poll();
556 base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
557 do {
558 left_to_poll = base;
559 } while (base != left_to_poll);
560 }
561}
562
563/* called when looping */
564void show_activity(int arg)
565{
566 do_poll();
567}
568
569#endif
570
571#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
572int overwrite_console(void)
573{
574 /* printf("overwrite_console called\n"); */
575 return 0;
576}
577#endif
578
579extern int drv_phone_init(void);
580extern int drv_phone_use_me(void);
581
582int misc_init_r(void)
583{
584 return drv_phone_init();
585}
586
587int last_stage_init(void)
588{
589 int i;
590
591 reset_phys();
592
593 /* check in order to enable the local console */
594 left_to_poll = PHONE_CONSOLE_POLL_HZ;
595 i = CFG_HZ * 2;
596 while (i > 0) {
597
598 if (tstc()) {
599 getc();
600 break;
601 }
602
603 do_poll();
604
605 if (drv_phone_use_me()) {
606 console_assign(stdin, "phone");
607 console_assign(stdout, "phone");
608 console_assign(stderr, "phone");
609 setenv("bootdelay", "-1");
610 break;
611 }
612
613 udelay(1000000 / CFG_HZ);
614 i--;
615 left_to_poll--;
616 }
617 left_to_poll = PHONE_CONSOLE_POLL_HZ;
618
619 return 0;
620}
Empty description
This page took 0.088335 seconds and 4 git commands to generate.