[J-u-boot.git] / doc / README.nand

# SPDX-License-Identifier: GPL-2.0+
NAND FLASH commands and notes

See NOTE below!!!

# (C) Copyright 2003
# Dave Ellis, SIXNET, [email protected]
#

Commands:

   nand bad
      Print a list of all of the bad blocks in the current device.

   nand device
      Print information about the current NAND device.

   nand device num
      Make device `num' the current device and print information about it.

   nand erase off|partition size
   nand erase clean [off|partition size]
      Erase `size' bytes starting at offset `off'. Alternatively partition
      name can be specified, in this case size will be eventually limited
      to not exceed partition size (this behaviour applies also to read
      and write commands). Only complete erase blocks can be erased.

      If `erase' is specified without an offset or size, the entire flash
      is erased. If `erase' is specified with partition but without an
      size, the entire partition is erased.

      If `clean' is specified, a JFFS2-style clean marker is written to
      each block after it is erased.

      This command will not erase blocks that are marked bad. There is
      a debug option in cmd_nand.c to allow bad blocks to be erased.
      Please read the warning there before using it, as blocks marked
      bad by the manufacturer must _NEVER_ be erased.

   nand info
      Print information about all of the NAND devices found.

   nand read addr ofs|partition size
      Read `size' bytes from `ofs' in NAND flash to `addr'.  Blocks that
      are marked bad are skipped.  If a page cannot be read because an
      uncorrectable data error is found, the command stops with an error.

   nand read.oob addr ofs|partition size
      Read `size' bytes from the out-of-band data area corresponding to
      `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
      data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks or ECC errors.

   nand write addr ofs|partition size
      Write `size' bytes from `addr' to `ofs' in NAND flash.  Blocks that
      are marked bad are skipped.  If a page cannot be read because an
      uncorrectable data error is found, the command stops with an error.

      As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
      as long as the image is short enough to fit even after skipping the
      bad blocks.  Compact images, such as those produced by mkfs.jffs2
      should work well, but loading an image copied from another flash is
      going to be trouble if there are any bad blocks.

   nand write.trimffs addr ofs|partition size
      Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
      the NAND flash in a manner identical to the 'nand write' command
      described above -- with the additional check that all pages at the end
      of eraseblocks which contain only 0xff data will not be written to the
      NAND flash. This behaviour is required when flashing UBI images
      containing UBIFS volumes as per the UBI FAQ[1].

      [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo

   nand write.oob addr ofs|partition size
      Write `size' bytes from `addr' to the out-of-band data area
      corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
      of data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks.

   nand read.raw addr ofs|partition [count]
   nand write.raw addr ofs|partition [count]
      Read or write one or more pages at "ofs" in NAND flash, from or to
      "addr" in memory.  This is a raw access, so ECC is avoided and the
      OOB area is transferred as well.  If count is absent, it is assumed
      to be one page.  As with .yaffs2 accesses, the data is formatted as
      a packed sequence of "data, oob, data, oob, ..." -- no alignment of
      individual pages is maintained.

Configuration Options:

   CONFIG_SYS_NAND_U_BOOT_OFFS
	NAND Offset from where SPL will read u-boot image. This is the starting
	address of u-boot MTD partition in NAND.

   CONFIG_CMD_NAND
      Enables NAND support and commands.

   CONFIG_CMD_NAND_TORTURE
      Enables the torture command (see description of this command below).

   CONFIG_SYS_NAND_MAX_CHIPS
      The maximum number of NAND chips per device to be supported.

   CONFIG_SYS_NAND_SELF_INIT
      Traditionally, glue code in drivers/mtd/nand/raw/nand.c has driven
      the initialization process -- it provides the mtd and nand
      structs, calls a board init function for a specific device,
      calls nand_scan(), and registers with mtd.

      This arrangement does not provide drivers with the flexibility to
      run code between nand_scan_ident() and nand_scan_tail(), or other
      deviations from the "normal" flow.

      If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/raw/nand.c
      will make one call to board_nand_init(), with no arguments.  That
      function is responsible for calling a driver init function for
      each NAND device on the board, that performs all initialization
      tasks except setting mtd->name, and registering with the rest of
      U-Boot.  Those last tasks are accomplished by calling  nand_register()
      on the new mtd device.

      Example of new init to be added to the end of an existing driver
      init:

	/* chip is struct nand_chip, and is now provided by the driver. */
	mtd = nand_to_mtd(&chip);

	/*
	 * Fill in appropriate values if this driver uses these fields,
	 * or uses the standard read_byte/write_buf/etc. functions from
	 * nand_base.c that use these fields.
	 */
	chip.IO_ADDR_R = ...;
	chip.IO_ADDR_W = ...;

	if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL))
		error out

	/*
	 * Insert here any code you wish to run after the chip has been
	 * identified, but before any other I/O is done.
	 */

	if (nand_scan_tail(mtd))
		error out

	/*
	 * devnum is the device number to be used in nand commands
	 * and in mtd->name.  Must be less than CONFIG_SYS_MAX_NAND_DEVICE.
	 */
	if (nand_register(devnum, mtd))
		error out

      In addition to providing more flexibility to the driver, it reduces
      the difference between a U-Boot driver and its Linux counterpart.
      nand_init() is now reduced to calling board_nand_init() once, and
      printing a size summary.  This should also make it easier to
      transition to delayed NAND initialization.

      Please convert your driver even if you don't need the extra
      flexibility, so that one day we can eliminate the old mechanism.


Platform specific options
=========================
   CONFIG_NAND_OMAP_GPMC
	Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
	GPMC controller is used for parallel NAND flash devices, and can
	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
	and BCH16 ECC algorithms.

   CONFIG_NAND_OMAP_ELM
	Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
	ELM controller is used for ECC error detection (not ECC calculation)
	of BCH4, BCH8 and BCH16 ECC algorithms.
	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	thus such SoC platforms need to depend on software library for ECC error
	detection. However ECC calculation on such plaforms would still be
	done by GPMC controller.

   CONFIG_SPL_NAND_AM33XX_BCH
	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
        hardware ECC correction. This is useful for platforms which have ELM
	hardware engine and use NAND boot mode.
	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
        SPL-NAND driver with software ECC correction support.

    CONFIG_NAND_OMAP_GPMC_PREFETCH
	On OMAP platforms that use the GPMC controller
	(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
	uses the prefetch mode to speed up read operations.

NOTE:
=====

The Disk On Chip driver is currently broken and has been for some time.
There is a driver in drivers/mtd/nand/raw, taken from Linux, that works with
the current NAND system but has not yet been adapted to the u-boot
environment.

Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006

JFFS2 related commands:

  implement "nand erase clean" and old "nand erase"
  using both the new code which is able to skip bad blocks
  "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.

Miscellaneous and testing commands:
  "markbad [offset]"
  create an artificial bad block (for testing bad block handling)

  "scrub [offset length]"
  like "erase" but don't skip bad block. Instead erase them.
  DANGEROUS!!! Factory set bad blocks will be lost. Use only
  to remove artificial bad blocks created with the "markbad" command.

  "torture offset [size]"
  Torture block to determine if it is still reliable.
  Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
  This command returns 0 if the block is still reliable, else 1.
  If the block is detected as unreliable, it is up to the user to decide to
  mark this block as bad.
  The analyzed block is put through 3 erase / write cycles (or less if the block
  is detected as unreliable earlier).
  This command can be used in scripts, e.g. together with the markbad command to
  automate retries and handling of possibly newly detected bad blocks if the
  nand write command fails.
  It can also be used manually by users having seen some NAND errors in logs to
  search the root cause of these errors.
  The underlying nand_torture() function is also useful for code willing to
  automate actions following a nand->write() error. This would e.g. be required
  in order to program or update safely firmware to NAND, especially for the UBI
  part of such firmware.
  Optionally, a second parameter size can be given to test multiple blocks with
  one call. If size is not a multiple of the NAND's erase size, then the block
  that contains offset + size will be tested in full. If used with size, this
  command returns 0 if all tested blocks have been found reliable, else 1.


NAND locking command (for chips with active LOCKPRE pin)

  "nand lock"
  set NAND chip to lock state (all pages locked)

  "nand lock tight"
  set NAND chip to lock tight state (software can't change locking anymore)

  "nand lock status"
  displays current locking status of all pages

  "nand unlock [offset] [size]"
  unlock consecutive area (can be called multiple times for different areas)

  "nand unlock.allexcept [offset] [size]"
  unlock all except specified consecutive area

I have tested the code with board containing 128MiB NAND large page chips
and 32MiB small page chips.
Commit	Line	Data
83d290c5	1	# SPDX-License-Identifier: GPL-2.0+
7a8e9bed WD	2	NAND FLASH commands and notes
7a8e9bed WD	3
4e3ccd26 WD	4	See NOTE below!!!
4e3ccd26 WD	5
7a8e9bed WD	6	# (C) Copyright 2003
	7	# Dave Ellis, SIXNET, [email protected]
	8	#
7a8e9bed WD	9
	10	Commands:
	11
	12	nand bad
	13	Print a list of all of the bad blocks in the current device.
	14
	15	nand device
	16	Print information about the current NAND device.
	17
	18	nand device num
	19	Make device `num' the current device and print information about it.
	20
856f0544 SR	21	nand erase off\|partition size
	22	nand erase clean [off\|partition size]
	23	Erase `size' bytes starting at offset `off'. Alternatively partition
	24	name can be specified, in this case size will be eventually limited
	25	to not exceed partition size (this behaviour applies also to read
	26	and write commands). Only complete erase blocks can be erased.
	27
	28	If `erase' is specified without an offset or size, the entire flash
	29	is erased. If `erase' is specified with partition but without an
	30	size, the entire partition is erased.
7a8e9bed WD	31
7a8e9bed WD	32	If `clean' is specified, a JFFS2-style clean marker is written to
856f0544	33	each block after it is erased.
7a8e9bed WD	34
	35	This command will not erase blocks that are marked bad. There is
	36	a debug option in cmd_nand.c to allow bad blocks to be erased.
	37	Please read the warning there before using it, as blocks marked
	38	bad by the manufacturer must _NEVER_ be erased.
	39
	40	nand info
	41	Print information about all of the NAND devices found.
	42
856f0544	43	nand read addr ofs\|partition size
984e03cd SW	44	Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
	45	are marked bad are skipped. If a page cannot be read because an
	46	uncorrectable data error is found, the command stops with an error.
7a8e9bed	47
856f0544	48	nand read.oob addr ofs\|partition size
7a8e9bed WD	49	Read `size' bytes from the out-of-band data area corresponding to
	50	`ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
	51	data for one 512-byte page or 2 256-byte pages. There is no check
	52	for bad blocks or ECC errors.
	53
856f0544	54	nand write addr ofs\|partition size
984e03cd SW	55	Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
	56	are marked bad are skipped. If a page cannot be read because an
	57	uncorrectable data error is found, the command stops with an error.
	58
	59	As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
	60	as long as the image is short enough to fit even after skipping the
	61	bad blocks. Compact images, such as those produced by mkfs.jffs2
	62	should work well, but loading an image copied from another flash is
	63	going to be trouble if there are any bad blocks.
7a8e9bed	64
c9494866 BG	65	nand write.trimffs addr ofs\|partition size
	66	Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
	67	the NAND flash in a manner identical to the 'nand write' command
	68	described above -- with the additional check that all pages at the end
	69	of eraseblocks which contain only 0xff data will not be written to the
	70	NAND flash. This behaviour is required when flashing UBI images
	71	containing UBIFS volumes as per the UBI FAQ[1].
	72
	73	[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
	74
856f0544	75	nand write.oob addr ofs\|partition size
7a8e9bed WD	76	Write `size' bytes from `addr' to the out-of-band data area
	77	corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
	78	of data for one 512-byte page or 2 256-byte pages. There is no check
	79	for bad blocks.
	80
418396e2 SW	81	nand read.raw addr ofs\|partition [count]
	82	nand write.raw addr ofs\|partition [count]
	83	Read or write one or more pages at "ofs" in NAND flash, from or to
	84	"addr" in memory. This is a raw access, so ECC is avoided and the
	85	OOB area is transferred as well. If count is absent, it is assumed
	86	to be one page. As with .yaffs2 accesses, the data is formatted as
	87	a packed sequence of "data, oob, data, oob, ..." -- no alignment of
	88	individual pages is maintained.
fb3659ac	89
7a8e9bed WD	90	Configuration Options:
7a8e9bed WD	91
434f2cfc	92	CONFIG_SYS_NAND_U_BOOT_OFFS
	93	NAND Offset from where SPL will read u-boot image. This is the starting
	94	address of u-boot MTD partition in NAND.
	95
b5501f7d	96	CONFIG_CMD_NAND
3f42dc87	97	Enables NAND support and commands.
7a8e9bed	98
3287f6d3 BT	99	CONFIG_CMD_NAND_TORTURE
	100	Enables the torture command (see description of this command below).
	101
99067b08 SW	102	CONFIG_SYS_NAND_MAX_CHIPS
	103	The maximum number of NAND chips per device to be supported.
	104
578931b3	105	CONFIG_SYS_NAND_SELF_INIT
a430fa06	106	Traditionally, glue code in drivers/mtd/nand/raw/nand.c has driven
578931b3 SW	107	the initialization process -- it provides the mtd and nand
	108	structs, calls a board init function for a specific device,
	109	calls nand_scan(), and registers with mtd.
	110
	111	This arrangement does not provide drivers with the flexibility to
	112	run code between nand_scan_ident() and nand_scan_tail(), or other
	113	deviations from the "normal" flow.
	114
a430fa06	115	If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/raw/nand.c
578931b3 SW	116	will make one call to board_nand_init(), with no arguments. That
	117	function is responsible for calling a driver init function for
	118	each NAND device on the board, that performs all initialization
	119	tasks except setting mtd->name, and registering with the rest of
	120	U-Boot. Those last tasks are accomplished by calling nand_register()
	121	on the new mtd device.
	122
	123	Example of new init to be added to the end of an existing driver
	124	init:
	125
578931b3	126	/* chip is struct nand_chip, and is now provided by the driver. */
30780f94	127	mtd = nand_to_mtd(&chip);
578931b3 SW	128
	129	/*
	130	* Fill in appropriate values if this driver uses these fields,
	131	* or uses the standard read_byte/write_buf/etc. functions from
	132	* nand_base.c that use these fields.
	133	*/
	134	chip.IO_ADDR_R = ...;
	135	chip.IO_ADDR_W = ...;
	136
65cc0e2a	137	if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL))
578931b3 SW	138	error out
	139
	140	/*
	141	* Insert here any code you wish to run after the chip has been
	142	* identified, but before any other I/O is done.
	143	*/
	144
	145	if (nand_scan_tail(mtd))
	146	error out
	147
b616d9b0 SW	148	/*
b616d9b0 SW	149	* devnum is the device number to be used in nand commands
4dc34be4	150	* and in mtd->name. Must be less than CONFIG_SYS_MAX_NAND_DEVICE.
b616d9b0 SW	151	*/
b616d9b0 SW	152	if (nand_register(devnum, mtd))
578931b3 SW	153	error out
	154
	155	In addition to providing more flexibility to the driver, it reduces
	156	the difference between a U-Boot driver and its Linux counterpart.
	157	nand_init() is now reduced to calling board_nand_init() once, and
	158	printing a size summary. This should also make it easier to
	159	transition to delayed NAND initialization.
	160
	161	Please convert your driver even if you don't need the extra
	162	flexibility, so that one day we can eliminate the old mechanism.
	163
beba5f04	164
	165	Platform specific options
	166	=========================
	167	CONFIG_NAND_OMAP_GPMC
	168	Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
	169	GPMC controller is used for parallel NAND flash devices, and can
	170	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
	171	and BCH16 ECC algorithms.
	172
	173	CONFIG_NAND_OMAP_ELM
	174	Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
	175	ELM controller is used for ECC error detection (not ECC calculation)
	176	of BCH4, BCH8 and BCH16 ECC algorithms.
	177	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	178	thus such SoC platforms need to depend on software library for ECC error
	179	detection. However ECC calculation on such plaforms would still be
	180	done by GPMC controller.
	181
434f2cfc	182	CONFIG_SPL_NAND_AM33XX_BCH
	183	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
	184	hardware ECC correction. This is useful for platforms which have ELM
	185	hardware engine and use NAND boot mode.
	186	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	187	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
	188	SPL-NAND driver with software ECC correction support.
	189
c316f577 DM	190	CONFIG_NAND_OMAP_GPMC_PREFETCH
	191	On OMAP platforms that use the GPMC controller
	192	(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
	193	uses the prefetch mode to speed up read operations.
	194
4e3ccd26 WD	195	NOTE:
	196	=====
	197
99067b08	198	The Disk On Chip driver is currently broken and has been for some time.
a430fa06	199	There is a driver in drivers/mtd/nand/raw, taken from Linux, that works with
99067b08 SW	200	the current NAND system but has not yet been adapted to the u-boot
99067b08 SW	201	environment.
2255b2d2	202
2255b2d2 SR	203	Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
	204
	205	JFFS2 related commands:
	206
	207	implement "nand erase clean" and old "nand erase"
	208	using both the new code which is able to skip bad blocks
	209	"nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
	210
2255b2d2 SR	211	Miscellaneous and testing commands:
	212	"markbad [offset]"
	213	create an artificial bad block (for testing bad block handling)
	214
	215	"scrub [offset length]"
	216	like "erase" but don't skip bad block. Instead erase them.
	217	DANGEROUS!!! Factory set bad blocks will be lost. Use only
	218	to remove artificial bad blocks created with the "markbad" command.
	219
1866be7d	220	"torture offset [size]"
3287f6d3 BT	221	Torture block to determine if it is still reliable.
	222	Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
	223	This command returns 0 if the block is still reliable, else 1.
	224	If the block is detected as unreliable, it is up to the user to decide to
	225	mark this block as bad.
	226	The analyzed block is put through 3 erase / write cycles (or less if the block
	227	is detected as unreliable earlier).
	228	This command can be used in scripts, e.g. together with the markbad command to
	229	automate retries and handling of possibly newly detected bad blocks if the
	230	nand write command fails.
	231	It can also be used manually by users having seen some NAND errors in logs to
	232	search the root cause of these errors.
	233	The underlying nand_torture() function is also useful for code willing to
	234	automate actions following a nand->write() error. This would e.g. be required
	235	in order to program or update safely firmware to NAND, especially for the UBI
	236	part of such firmware.
1866be7d MK	237	Optionally, a second parameter size can be given to test multiple blocks with
	238	one call. If size is not a multiple of the NAND's erase size, then the block
	239	that contains offset + size will be tested in full. If used with size, this
	240	command returns 0 if all tested blocks have been found reliable, else 1.
3287f6d3	241
2255b2d2 SR	242
	243	NAND locking command (for chips with active LOCKPRE pin)
	244
	245	"nand lock"
	246	set NAND chip to lock state (all pages locked)
	247
	248	"nand lock tight"
	249	set NAND chip to lock tight state (software can't change locking anymore)
	250
	251	"nand lock status"
	252	displays current locking status of all pages
	253
	254	"nand unlock [offset] [size]"
	255	unlock consecutive area (can be called multiple times for different areas)
	256
eee623a5 JH	257	"nand unlock.allexcept [offset] [size]"
eee623a5 JH	258	unlock all except specified consecutive area
2255b2d2 SR	259
	260	I have tested the code with board containing 128MiB NAND large page chips
	261	and 32MiB small page chips.