[J-u-boot.git] / doc / README.nand

NAND FLASH commands and notes

See NOTE below!!!

# (C) Copyright 2003
# Dave Ellis, SIXNET, [email protected]
#
# SPDX-License-Identifier:	GPL-2.0+

Commands:

   nand bad
      Print a list of all of the bad blocks in the current device.

   nand device
      Print information about the current NAND device.

   nand device num
      Make device `num' the current device and print information about it.

   nand erase off|partition size
   nand erase clean [off|partition size]
      Erase `size' bytes starting at offset `off'. Alternatively partition
      name can be specified, in this case size will be eventually limited
      to not exceed partition size (this behaviour applies also to read
      and write commands). Only complete erase blocks can be erased.

      If `erase' is specified without an offset or size, the entire flash
      is erased. If `erase' is specified with partition but without an
      size, the entire partition is erased.

      If `clean' is specified, a JFFS2-style clean marker is written to
      each block after it is erased.

      This command will not erase blocks that are marked bad. There is
      a debug option in cmd_nand.c to allow bad blocks to be erased.
      Please read the warning there before using it, as blocks marked
      bad by the manufacturer must _NEVER_ be erased.

   nand info
      Print information about all of the NAND devices found.

   nand read addr ofs|partition size
      Read `size' bytes from `ofs' in NAND flash to `addr'.  Blocks that
      are marked bad are skipped.  If a page cannot be read because an
      uncorrectable data error is found, the command stops with an error.

   nand read.oob addr ofs|partition size
      Read `size' bytes from the out-of-band data area corresponding to
      `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
      data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks or ECC errors.

   nand write addr ofs|partition size
      Write `size' bytes from `addr' to `ofs' in NAND flash.  Blocks that
      are marked bad are skipped.  If a page cannot be read because an
      uncorrectable data error is found, the command stops with an error.

      As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
      as long as the image is short enough to fit even after skipping the
      bad blocks.  Compact images, such as those produced by mkfs.jffs2
      should work well, but loading an image copied from another flash is
      going to be trouble if there are any bad blocks.

   nand write.trimffs addr ofs|partition size
      Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
      the NAND flash in a manner identical to the 'nand write' command
      described above -- with the additional check that all pages at the end
      of eraseblocks which contain only 0xff data will not be written to the
      NAND flash. This behaviour is required when flashing UBI images
      containing UBIFS volumes as per the UBI FAQ[1].

      [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo

   nand write.oob addr ofs|partition size
      Write `size' bytes from `addr' to the out-of-band data area
      corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
      of data for one 512-byte page or 2 256-byte pages. There is no check
      for bad blocks.

   nand read.raw addr ofs|partition [count]
   nand write.raw addr ofs|partition [count]
      Read or write one or more pages at "ofs" in NAND flash, from or to
      "addr" in memory.  This is a raw access, so ECC is avoided and the
      OOB area is transferred as well.  If count is absent, it is assumed
      to be one page.  As with .yaffs2 accesses, the data is formatted as
      a packed sequence of "data, oob, data, oob, ..." -- no alignment of
      individual pages is maintained.

Configuration Options:

   CONFIG_SYS_NAND_U_BOOT_OFFS
	NAND Offset from where SPL will read u-boot image. This is the starting
	address of u-boot MTD partition in NAND.

   CONFIG_CMD_NAND
      Enables NAND support and commmands.

   CONFIG_CMD_NAND_TORTURE
      Enables the torture command (see description of this command below).

   CONFIG_SYS_MAX_NAND_DEVICE
      The maximum number of NAND devices you want to support.

   CONFIG_SYS_NAND_MAX_ECCPOS
      If specified, overrides the maximum number of ECC bytes
      supported.  Useful for reducing image size, especially with SPL.
      This must be at least 48 if nand_base.c is used.

   CONFIG_SYS_NAND_MAX_OOBFREE
      If specified, overrides the maximum number of free OOB regions
      supported.  Useful for reducing image size, especially with SPL.
      This must be at least 2 if nand_base.c is used.

   CONFIG_SYS_NAND_MAX_CHIPS
      The maximum number of NAND chips per device to be supported.

   CONFIG_SYS_NAND_SELF_INIT
      Traditionally, glue code in drivers/mtd/nand/nand.c has driven
      the initialization process -- it provides the mtd and nand
      structs, calls a board init function for a specific device,
      calls nand_scan(), and registers with mtd.

      This arrangement does not provide drivers with the flexibility to
      run code between nand_scan_ident() and nand_scan_tail(), or other
      deviations from the "normal" flow.

      If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/nand.c
      will make one call to board_nand_init(), with no arguments.  That
      function is responsible for calling a driver init function for
      each NAND device on the board, that performs all initialization
      tasks except setting mtd->name, and registering with the rest of
      U-Boot.  Those last tasks are accomplished by calling  nand_register()
      on the new mtd device.

      Example of new init to be added to the end of an existing driver
      init:

	/*
	 * devnum is the device number to be used in nand commands
	 * and in mtd->name.  Must be less than
	 * CONFIG_SYS_NAND_MAX_DEVICE.
	 */
	mtd = &nand_info[devnum];

	/* chip is struct nand_chip, and is now provided by the driver. */
	mtd->priv = &chip;

	/*
	 * Fill in appropriate values if this driver uses these fields,
	 * or uses the standard read_byte/write_buf/etc. functions from
	 * nand_base.c that use these fields.
	 */
	chip.IO_ADDR_R = ...;
	chip.IO_ADDR_W = ...;

	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
		error out

	/*
	 * Insert here any code you wish to run after the chip has been
	 * identified, but before any other I/O is done.
	 */

	if (nand_scan_tail(mtd))
		error out

	if (nand_register(devnum))
		error out

      In addition to providing more flexibility to the driver, it reduces
      the difference between a U-Boot driver and its Linux counterpart.
      nand_init() is now reduced to calling board_nand_init() once, and
      printing a size summary.  This should also make it easier to
      transition to delayed NAND initialization.

      Please convert your driver even if you don't need the extra
      flexibility, so that one day we can eliminate the old mechanism.


   CONFIG_SYS_NAND_ONFI_DETECTION
	Enables detection of ONFI compliant devices during probe.
	And fetching device parameters flashed on device, by parsing
	ONFI parameter page.

   CONFIG_BCH
	Enables software based BCH ECC algorithm present in lib/bch.c
	This is used by SoC platforms which do not have built-in ELM
	hardware engine required for BCH ECC correction.


Platform specific options
=========================
   CONFIG_NAND_OMAP_GPMC
	Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
	GPMC controller is used for parallel NAND flash devices, and can
	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
	and BCH16 ECC algorithms.

   CONFIG_NAND_OMAP_ELM
	Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
	ELM controller is used for ECC error detection (not ECC calculation)
	of BCH4, BCH8 and BCH16 ECC algorithms.
	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	thus such SoC platforms need to depend on software library for ECC error
	detection. However ECC calculation on such plaforms would still be
	done by GPMC controller.

   CONFIG_SPL_NAND_AM33XX_BCH
	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
        hardware ECC correction. This is useful for platforms which have ELM
	hardware engine and use NAND boot mode.
	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
        SPL-NAND driver with software ECC correction support.

   CONFIG_NAND_OMAP_ECCSCHEME
	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
	It can take following values:
	OMAP_ECC_HAM1_CODE_SW
		1-bit Hamming code using software lib.
		(for legacy devices only)
	OMAP_ECC_HAM1_CODE_HW
		1-bit Hamming code using GPMC hardware.
		(for legacy devices only)
	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
		4-bit BCH code (unsupported)
	OMAP_ECC_BCH4_CODE_HW
		4-bit BCH code (unsupported)
	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
		8-bit BCH code with
		- ecc calculation using GPMC hardware engine,
		- error detection using software library.
		- requires CONFIG_BCH to enable software BCH library
		(For legacy device which do not have ELM h/w engine)
	OMAP_ECC_BCH8_CODE_HW
		8-bit BCH code with
		- ecc calculation using GPMC hardware engine,
		- error detection using ELM hardware engine.
	OMAP_ECC_BCH16_CODE_HW
		16-bit BCH code with
		- ecc calculation using GPMC hardware engine,
		- error detection using ELM hardware engine.

	How to select ECC scheme on OMAP and AMxx platforms ?
	-----------------------------------------------------
	Though higher ECC schemes have more capability to detect and correct
	bit-flips, but still selection of ECC scheme is dependent on following
	- hardware engines present in SoC.
		Some legacy OMAP SoC do not have ELM h/w engine thus such
		SoC cannot support BCHx_HW ECC schemes.
	- size of OOB/Spare region
		With higher ECC schemes, more OOB/Spare area is required to
		store ECC. So choice of ECC scheme is limited by NAND oobsize.

	In general following expression can help:
		NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
	where
		NAND_OOBSIZE	= number of bytes available in
				OOB/spare area per NAND page.
		NAND_PAGESIZE	= bytes in main-area of NAND page.
		ECC_BYTES	= number of ECC bytes generated to
				protect 512 bytes of data, which is:
				3 for HAM1_xx ecc schemes
				7 for BCH4_xx ecc schemes
				14 for BCH8_xx ecc schemes
				26 for BCH16_xx ecc schemes

		example to check for BCH16 on 2K page NAND
		NAND_PAGESIZE = 2048
		NAND_OOBSIZE = 64
		2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
		Thus BCH16 cannot be supported on 2K page NAND.

		However, for 4K pagesize NAND
		NAND_PAGESIZE = 4096
		NAND_OOBSIZE = 64
		ECC_BYTES = 26
		2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
		Thus BCH16 can be supported on 4K page NAND.


    CONFIG_NAND_OMAP_GPMC_PREFETCH
	On OMAP platforms that use the GPMC controller
	(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
	uses the prefetch mode to speed up read operations.

NOTE:
=====

The Disk On Chip driver is currently broken and has been for some time.
There is a driver in drivers/mtd/nand, taken from Linux, that works with
the current NAND system but has not yet been adapted to the u-boot
environment.

Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006

JFFS2 related commands:

  implement "nand erase clean" and old "nand erase"
  using both the new code which is able to skip bad blocks
  "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.

Miscellaneous and testing commands:
  "markbad [offset]"
  create an artificial bad block (for testing bad block handling)

  "scrub [offset length]"
  like "erase" but don't skip bad block. Instead erase them.
  DANGEROUS!!! Factory set bad blocks will be lost. Use only
  to remove artificial bad blocks created with the "markbad" command.

  "torture offset"
  Torture block to determine if it is still reliable.
  Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
  This command returns 0 if the block is still reliable, else 1.
  If the block is detected as unreliable, it is up to the user to decide to
  mark this block as bad.
  The analyzed block is put through 3 erase / write cycles (or less if the block
  is detected as unreliable earlier).
  This command can be used in scripts, e.g. together with the markbad command to
  automate retries and handling of possibly newly detected bad blocks if the
  nand write command fails.
  It can also be used manually by users having seen some NAND errors in logs to
  search the root cause of these errors.
  The underlying nand_torture() function is also useful for code willing to
  automate actions following a nand->write() error. This would e.g. be required
  in order to program or update safely firmware to NAND, especially for the UBI
  part of such firmware.


NAND locking command (for chips with active LOCKPRE pin)

  "nand lock"
  set NAND chip to lock state (all pages locked)

  "nand lock tight"
  set NAND chip to lock tight state (software can't change locking anymore)

  "nand lock status"
  displays current locking status of all pages

  "nand unlock [offset] [size]"
  unlock consecutive area (can be called multiple times for different areas)

  "nand unlock.allexcept [offset] [size]"
  unlock all except specified consecutive area

I have tested the code with board containing 128MiB NAND large page chips
and 32MiB small page chips.
Commit	Line	Data
7a8e9bed WD	1	NAND FLASH commands and notes
7a8e9bed WD	2
4e3ccd26 WD	3	See NOTE below!!!
4e3ccd26 WD	4
7a8e9bed WD	5	# (C) Copyright 2003
	6	# Dave Ellis, SIXNET, [email protected]
	7	#
1a459660	8	# SPDX-License-Identifier: GPL-2.0+
7a8e9bed WD	9
	10	Commands:
	11
	12	nand bad
	13	Print a list of all of the bad blocks in the current device.
	14
	15	nand device
	16	Print information about the current NAND device.
	17
	18	nand device num
	19	Make device `num' the current device and print information about it.
	20
856f0544 SR	21	nand erase off\|partition size
	22	nand erase clean [off\|partition size]
	23	Erase `size' bytes starting at offset `off'. Alternatively partition
	24	name can be specified, in this case size will be eventually limited
	25	to not exceed partition size (this behaviour applies also to read
	26	and write commands). Only complete erase blocks can be erased.
	27
	28	If `erase' is specified without an offset or size, the entire flash
	29	is erased. If `erase' is specified with partition but without an
	30	size, the entire partition is erased.
7a8e9bed WD	31
7a8e9bed WD	32	If `clean' is specified, a JFFS2-style clean marker is written to
856f0544	33	each block after it is erased.
7a8e9bed WD	34
	35	This command will not erase blocks that are marked bad. There is
	36	a debug option in cmd_nand.c to allow bad blocks to be erased.
	37	Please read the warning there before using it, as blocks marked
	38	bad by the manufacturer must _NEVER_ be erased.
	39
	40	nand info
	41	Print information about all of the NAND devices found.
	42
856f0544	43	nand read addr ofs\|partition size
984e03cd SW	44	Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
	45	are marked bad are skipped. If a page cannot be read because an
	46	uncorrectable data error is found, the command stops with an error.
7a8e9bed	47
856f0544	48	nand read.oob addr ofs\|partition size
7a8e9bed WD	49	Read `size' bytes from the out-of-band data area corresponding to
	50	`ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
	51	data for one 512-byte page or 2 256-byte pages. There is no check
	52	for bad blocks or ECC errors.
	53
856f0544	54	nand write addr ofs\|partition size
984e03cd SW	55	Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
	56	are marked bad are skipped. If a page cannot be read because an
	57	uncorrectable data error is found, the command stops with an error.
	58
	59	As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
	60	as long as the image is short enough to fit even after skipping the
	61	bad blocks. Compact images, such as those produced by mkfs.jffs2
	62	should work well, but loading an image copied from another flash is
	63	going to be trouble if there are any bad blocks.
7a8e9bed	64
c9494866 BG	65	nand write.trimffs addr ofs\|partition size
	66	Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
	67	the NAND flash in a manner identical to the 'nand write' command
	68	described above -- with the additional check that all pages at the end
	69	of eraseblocks which contain only 0xff data will not be written to the
	70	NAND flash. This behaviour is required when flashing UBI images
	71	containing UBIFS volumes as per the UBI FAQ[1].
	72
	73	[1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
	74
856f0544	75	nand write.oob addr ofs\|partition size
7a8e9bed WD	76	Write `size' bytes from `addr' to the out-of-band data area
	77	corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
	78	of data for one 512-byte page or 2 256-byte pages. There is no check
	79	for bad blocks.
	80
418396e2 SW	81	nand read.raw addr ofs\|partition [count]
	82	nand write.raw addr ofs\|partition [count]
	83	Read or write one or more pages at "ofs" in NAND flash, from or to
	84	"addr" in memory. This is a raw access, so ECC is avoided and the
	85	OOB area is transferred as well. If count is absent, it is assumed
	86	to be one page. As with .yaffs2 accesses, the data is formatted as
	87	a packed sequence of "data, oob, data, oob, ..." -- no alignment of
	88	individual pages is maintained.
fb3659ac	89
7a8e9bed WD	90	Configuration Options:
7a8e9bed WD	91
434f2cfc	92	CONFIG_SYS_NAND_U_BOOT_OFFS
	93	NAND Offset from where SPL will read u-boot image. This is the starting
	94	address of u-boot MTD partition in NAND.
	95
b5501f7d JL	96	CONFIG_CMD_NAND
b5501f7d JL	97	Enables NAND support and commmands.
7a8e9bed	98
3287f6d3 BT	99	CONFIG_CMD_NAND_TORTURE
	100	Enables the torture command (see description of this command below).
	101
6d0f6bcf	102	CONFIG_SYS_MAX_NAND_DEVICE
7a8e9bed WD	103	The maximum number of NAND devices you want to support.
7a8e9bed WD	104
68ec9c85 PK	105	CONFIG_SYS_NAND_MAX_ECCPOS
	106	If specified, overrides the maximum number of ECC bytes
	107	supported. Useful for reducing image size, especially with SPL.
	108	This must be at least 48 if nand_base.c is used.
	109
	110	CONFIG_SYS_NAND_MAX_OOBFREE
	111	If specified, overrides the maximum number of free OOB regions
	112	supported. Useful for reducing image size, especially with SPL.
	113	This must be at least 2 if nand_base.c is used.
	114
99067b08 SW	115	CONFIG_SYS_NAND_MAX_CHIPS
	116	The maximum number of NAND chips per device to be supported.
	117
578931b3 SW	118	CONFIG_SYS_NAND_SELF_INIT
	119	Traditionally, glue code in drivers/mtd/nand/nand.c has driven
	120	the initialization process -- it provides the mtd and nand
	121	structs, calls a board init function for a specific device,
	122	calls nand_scan(), and registers with mtd.
	123
	124	This arrangement does not provide drivers with the flexibility to
	125	run code between nand_scan_ident() and nand_scan_tail(), or other
	126	deviations from the "normal" flow.
	127
	128	If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/nand.c
	129	will make one call to board_nand_init(), with no arguments. That
	130	function is responsible for calling a driver init function for
	131	each NAND device on the board, that performs all initialization
	132	tasks except setting mtd->name, and registering with the rest of
	133	U-Boot. Those last tasks are accomplished by calling nand_register()
	134	on the new mtd device.
	135
	136	Example of new init to be added to the end of an existing driver
	137	init:
	138
	139	/*
	140	* devnum is the device number to be used in nand commands
	141	* and in mtd->name. Must be less than
	142	* CONFIG_SYS_NAND_MAX_DEVICE.
	143	*/
	144	mtd = &nand_info[devnum];
	145
	146	/* chip is struct nand_chip, and is now provided by the driver. */
	147	mtd->priv = &chip;
	148
	149	/*
	150	* Fill in appropriate values if this driver uses these fields,
	151	* or uses the standard read_byte/write_buf/etc. functions from
	152	* nand_base.c that use these fields.
	153	*/
	154	chip.IO_ADDR_R = ...;
	155	chip.IO_ADDR_W = ...;
	156
	157	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
	158	error out
	159
	160	/*
	161	* Insert here any code you wish to run after the chip has been
	162	* identified, but before any other I/O is done.
	163	*/
	164
	165	if (nand_scan_tail(mtd))
	166	error out
	167
	168	if (nand_register(devnum))
	169	error out
	170
	171	In addition to providing more flexibility to the driver, it reduces
	172	the difference between a U-Boot driver and its Linux counterpart.
	173	nand_init() is now reduced to calling board_nand_init() once, and
	174	printing a size summary. This should also make it easier to
	175	transition to delayed NAND initialization.
	176
	177	Please convert your driver even if you don't need the extra
	178	flexibility, so that one day we can eliminate the old mechanism.
	179
beba5f04	180
d016dc42	181	CONFIG_SYS_NAND_ONFI_DETECTION
	182	Enables detection of ONFI compliant devices during probe.
	183	And fetching device parameters flashed on device, by parsing
	184	ONFI parameter page.
	185
	186	CONFIG_BCH
	187	Enables software based BCH ECC algorithm present in lib/bch.c
	188	This is used by SoC platforms which do not have built-in ELM
	189	hardware engine required for BCH ECC correction.
	190
	191
beba5f04	192	Platform specific options
	193	=========================
	194	CONFIG_NAND_OMAP_GPMC
	195	Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
	196	GPMC controller is used for parallel NAND flash devices, and can
	197	do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
	198	and BCH16 ECC algorithms.
	199
	200	CONFIG_NAND_OMAP_ELM
	201	Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
	202	ELM controller is used for ECC error detection (not ECC calculation)
	203	of BCH4, BCH8 and BCH16 ECC algorithms.
	204	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	205	thus such SoC platforms need to depend on software library for ECC error
	206	detection. However ECC calculation on such plaforms would still be
	207	done by GPMC controller.
	208
434f2cfc	209	CONFIG_SPL_NAND_AM33XX_BCH
	210	Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
	211	hardware ECC correction. This is useful for platforms which have ELM
	212	hardware engine and use NAND boot mode.
	213	Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
	214	so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
	215	SPL-NAND driver with software ECC correction support.
	216
3f719069	217	CONFIG_NAND_OMAP_ECCSCHEME
	218	On OMAP platforms, this CONFIG specifies NAND ECC scheme.
	219	It can take following values:
	220	OMAP_ECC_HAM1_CODE_SW
	221	1-bit Hamming code using software lib.
	222	(for legacy devices only)
	223	OMAP_ECC_HAM1_CODE_HW
	224	1-bit Hamming code using GPMC hardware.
	225	(for legacy devices only)
	226	OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
	227	4-bit BCH code (unsupported)
	228	OMAP_ECC_BCH4_CODE_HW
	229	4-bit BCH code (unsupported)
	230	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
	231	8-bit BCH code with
	232	- ecc calculation using GPMC hardware engine,
	233	- error detection using software library.
	234	- requires CONFIG_BCH to enable software BCH library
	235	(For legacy device which do not have ELM h/w engine)
	236	OMAP_ECC_BCH8_CODE_HW
	237	8-bit BCH code with
	238	- ecc calculation using GPMC hardware engine,
	239	- error detection using ELM hardware engine.
867f0304	240	OMAP_ECC_BCH16_CODE_HW
	241	16-bit BCH code with
	242	- ecc calculation using GPMC hardware engine,
	243	- error detection using ELM hardware engine.
	244
	245	How to select ECC scheme on OMAP and AMxx platforms ?
	246	-----------------------------------------------------
	247	Though higher ECC schemes have more capability to detect and correct
	248	bit-flips, but still selection of ECC scheme is dependent on following
	249	- hardware engines present in SoC.
	250	Some legacy OMAP SoC do not have ELM h/w engine thus such
	251	SoC cannot support BCHx_HW ECC schemes.
	252	- size of OOB/Spare region
	253	With higher ECC schemes, more OOB/Spare area is required to
	254	store ECC. So choice of ECC scheme is limited by NAND oobsize.
	255
	256	In general following expression can help:
	257	NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
	258	where
	259	NAND_OOBSIZE = number of bytes available in
	260	OOB/spare area per NAND page.
	261	NAND_PAGESIZE = bytes in main-area of NAND page.
	262	ECC_BYTES = number of ECC bytes generated to
	263	protect 512 bytes of data, which is:
	264	3 for HAM1_xx ecc schemes
	265	7 for BCH4_xx ecc schemes
	266	14 for BCH8_xx ecc schemes
	267	26 for BCH16_xx ecc schemes
	268
	269	example to check for BCH16 on 2K page NAND
	270	NAND_PAGESIZE = 2048
	271	NAND_OOBSIZE = 64
	272	2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
	273	Thus BCH16 cannot be supported on 2K page NAND.
	274
	275	However, for 4K pagesize NAND
	276	NAND_PAGESIZE = 4096
	277	NAND_OOBSIZE = 64
	278	ECC_BYTES = 26
	279	2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
	280	Thus BCH16 can be supported on 4K page NAND.
	281
beba5f04	282
c316f577 DM	283	CONFIG_NAND_OMAP_GPMC_PREFETCH
	284	On OMAP platforms that use the GPMC controller
	285	(CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
	286	uses the prefetch mode to speed up read operations.
	287
4e3ccd26 WD	288	NOTE:
	289	=====
	290
99067b08 SW	291	The Disk On Chip driver is currently broken and has been for some time.
	292	There is a driver in drivers/mtd/nand, taken from Linux, that works with
	293	the current NAND system but has not yet been adapted to the u-boot
	294	environment.
2255b2d2	295
2255b2d2 SR	296	Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
	297
	298	JFFS2 related commands:
	299
	300	implement "nand erase clean" and old "nand erase"
	301	using both the new code which is able to skip bad blocks
	302	"nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
	303
2255b2d2 SR	304	Miscellaneous and testing commands:
	305	"markbad [offset]"
	306	create an artificial bad block (for testing bad block handling)
	307
	308	"scrub [offset length]"
	309	like "erase" but don't skip bad block. Instead erase them.
	310	DANGEROUS!!! Factory set bad blocks will be lost. Use only
	311	to remove artificial bad blocks created with the "markbad" command.
	312
3287f6d3 BT	313	"torture offset"
	314	Torture block to determine if it is still reliable.
	315	Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
	316	This command returns 0 if the block is still reliable, else 1.
	317	If the block is detected as unreliable, it is up to the user to decide to
	318	mark this block as bad.
	319	The analyzed block is put through 3 erase / write cycles (or less if the block
	320	is detected as unreliable earlier).
	321	This command can be used in scripts, e.g. together with the markbad command to
	322	automate retries and handling of possibly newly detected bad blocks if the
	323	nand write command fails.
	324	It can also be used manually by users having seen some NAND errors in logs to
	325	search the root cause of these errors.
	326	The underlying nand_torture() function is also useful for code willing to
	327	automate actions following a nand->write() error. This would e.g. be required
	328	in order to program or update safely firmware to NAND, especially for the UBI
	329	part of such firmware.
	330
2255b2d2 SR	331
	332	NAND locking command (for chips with active LOCKPRE pin)
	333
	334	"nand lock"
	335	set NAND chip to lock state (all pages locked)
	336
	337	"nand lock tight"
	338	set NAND chip to lock tight state (software can't change locking anymore)
	339
	340	"nand lock status"
	341	displays current locking status of all pages
	342
	343	"nand unlock [offset] [size]"
	344	unlock consecutive area (can be called multiple times for different areas)
	345
eee623a5 JH	346	"nand unlock.allexcept [offset] [size]"
eee623a5 JH	347	unlock all except specified consecutive area
2255b2d2 SR	348
	349	I have tested the code with board containing 128MiB NAND large page chips
	350	and 32MiB small page chips.