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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2da0fc0d DE |
2 | /* |
3 | * (C) Copyright 2010 | |
d38826a3 | 4 | * Dirk Eibach, Guntermann & Drunck GmbH, [email protected] |
2da0fc0d DE |
5 | */ |
6 | ||
7 | #ifndef __GDSYS_FPGA_H | |
8 | #define __GDSYS_FPGA_H | |
9 | ||
fe4a9675 | 10 | #ifdef CONFIG_GDSYS_LEGACY_DRIVERS |
255ef4d9 DE |
11 | int init_func_fpga(void); |
12 | ||
2da0fc0d DE |
13 | enum { |
14 | FPGA_STATE_DONE_FAILED = 1 << 0, | |
15 | FPGA_STATE_REFLECTION_FAILED = 1 << 1, | |
255ef4d9 | 16 | FPGA_STATE_PLATFORM = 1 << 2, |
2da0fc0d DE |
17 | }; |
18 | ||
19 | int get_fpga_state(unsigned dev); | |
2da0fc0d | 20 | |
aba27acf DE |
21 | int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); |
22 | int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); | |
23 | ||
24 | extern struct ihs_fpga *fpga_ptr[]; | |
25 | ||
26 | #define FPGA_SET_REG(ix, fld, val) \ | |
27 | fpga_set_reg((ix), \ | |
28 | &fpga_ptr[ix]->fld, \ | |
29 | offsetof(struct ihs_fpga, fld), \ | |
30 | val) | |
31 | ||
32 | #define FPGA_GET_REG(ix, fld, val) \ | |
33 | fpga_get_reg((ix), \ | |
34 | &fpga_ptr[ix]->fld, \ | |
35 | offsetof(struct ihs_fpga, fld), \ | |
36 | val) | |
fe4a9675 | 37 | #endif |
aba27acf | 38 | |
0e60aa85 | 39 | struct ihs_gpio { |
2da0fc0d DE |
40 | u16 read; |
41 | u16 clear; | |
42 | u16 set; | |
0e60aa85 | 43 | }; |
2da0fc0d | 44 | |
0e60aa85 | 45 | struct ihs_i2c { |
b46226bd DE |
46 | u16 interrupt_status; |
47 | u16 interrupt_enable; | |
2da0fc0d | 48 | u16 write_mailbox_ext; |
b46226bd | 49 | u16 write_mailbox; |
2da0fc0d | 50 | u16 read_mailbox_ext; |
b46226bd | 51 | u16 read_mailbox; |
0e60aa85 | 52 | }; |
2da0fc0d | 53 | |
0e60aa85 | 54 | struct ihs_osd { |
2da0fc0d DE |
55 | u16 version; |
56 | u16 features; | |
57 | u16 control; | |
58 | u16 xy_size; | |
52158e36 DE |
59 | u16 xy_scale; |
60 | u16 x_pos; | |
61 | u16 y_pos; | |
0e60aa85 | 62 | }; |
2da0fc0d | 63 | |
50dcf89d DE |
64 | struct ihs_mdio { |
65 | u16 control; | |
66 | u16 address_data; | |
67 | u16 rx_data; | |
68 | }; | |
69 | ||
70 | struct ihs_io_ep { | |
71 | u16 transmit_data; | |
72 | u16 rx_tx_control; | |
73 | u16 receive_data; | |
74 | u16 rx_tx_status; | |
75 | u16 reserved; | |
76 | u16 device_address; | |
77 | u16 target_address; | |
78 | }; | |
79 | ||
6e9e6c36 | 80 | #ifdef CONFIG_NEO |
0e60aa85 | 81 | struct ihs_fpga { |
6e9e6c36 DE |
82 | u16 reflection_low; /* 0x0000 */ |
83 | u16 versions; /* 0x0002 */ | |
84 | u16 fpga_features; /* 0x0004 */ | |
85 | u16 fpga_version; /* 0x0006 */ | |
86 | u16 reserved_0[8187]; /* 0x0008 */ | |
87 | u16 reflection_high; /* 0x3ffe */ | |
0e60aa85 | 88 | }; |
6e9e6c36 DE |
89 | #endif |
90 | ||
2da0fc0d | 91 | #endif |