projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2da0fc0d DE |
2 | /* |
| 3 | * (C) Copyright 2010 | |
| d38826a3 | 4 | * Dirk Eibach, Guntermann & Drunck GmbH, [email protected] |
| 2da0fc0d DE |
5 | */ |
| 6 | ||
| 7 | #ifndef __GDSYS_FPGA_H | |
| 8 | #define __GDSYS_FPGA_H | |
| 9 | ||
| 255ef4d9 DE |
10 | int init_func_fpga(void); |
| 11 | ||
| 2da0fc0d DE |
12 | enum { |
| 13 | FPGA_STATE_DONE_FAILED = 1 << 0, | |
| 14 | FPGA_STATE_REFLECTION_FAILED = 1 << 1, | |
| 255ef4d9 | 15 | FPGA_STATE_PLATFORM = 1 << 2, |
| 2da0fc0d DE |
16 | }; |
| 17 | ||
| 18 | int get_fpga_state(unsigned dev); | |
| 2da0fc0d | 19 | |
| aba27acf DE |
20 | int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data); |
| 21 | int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data); | |
| 22 | ||
| 23 | extern struct ihs_fpga *fpga_ptr[]; | |
| 24 | ||
| 25 | #define FPGA_SET_REG(ix, fld, val) \ | |
| 26 | fpga_set_reg((ix), \ | |
| 27 | &fpga_ptr[ix]->fld, \ | |
| 28 | offsetof(struct ihs_fpga, fld), \ | |
| 29 | val) | |
| 30 | ||
| 31 | #define FPGA_GET_REG(ix, fld, val) \ | |
| 32 | fpga_get_reg((ix), \ | |
| 33 | &fpga_ptr[ix]->fld, \ | |
| 34 | offsetof(struct ihs_fpga, fld), \ | |
| 35 | val) | |
| 36 | ||
| 0e60aa85 | 37 | struct ihs_gpio { |
| 2da0fc0d DE |
38 | u16 read; |
| 39 | u16 clear; | |
| 40 | u16 set; | |
| 0e60aa85 | 41 | }; |
| 2da0fc0d | 42 | |
| 0e60aa85 | 43 | struct ihs_i2c { |
| b46226bd DE |
44 | u16 interrupt_status; |
| 45 | u16 interrupt_enable; | |
| 2da0fc0d | 46 | u16 write_mailbox_ext; |
| b46226bd | 47 | u16 write_mailbox; |
| 2da0fc0d | 48 | u16 read_mailbox_ext; |
| b46226bd | 49 | u16 read_mailbox; |
| 0e60aa85 | 50 | }; |
| 2da0fc0d | 51 | |
| 0e60aa85 | 52 | struct ihs_osd { |
| 2da0fc0d DE |
53 | u16 version; |
| 54 | u16 features; | |
| 55 | u16 control; | |
| 56 | u16 xy_size; | |
| 52158e36 DE |
57 | u16 xy_scale; |
| 58 | u16 x_pos; | |
| 59 | u16 y_pos; | |
| 0e60aa85 | 60 | }; |
| 2da0fc0d | 61 | |
| 50dcf89d DE |
62 | struct ihs_mdio { |
| 63 | u16 control; | |
| 64 | u16 address_data; | |
| 65 | u16 rx_data; | |
| 66 | }; | |
| 67 | ||
| 68 | struct ihs_io_ep { | |
| 69 | u16 transmit_data; | |
| 70 | u16 rx_tx_control; | |
| 71 | u16 receive_data; | |
| 72 | u16 rx_tx_status; | |
| 73 | u16 reserved; | |
| 74 | u16 device_address; | |
| 75 | u16 target_address; | |
| 76 | }; | |
| 77 | ||
| 6e9e6c36 | 78 | #ifdef CONFIG_NEO |
| 0e60aa85 | 79 | struct ihs_fpga { |
| 6e9e6c36 DE |
80 | u16 reflection_low; /* 0x0000 */ |
| 81 | u16 versions; /* 0x0002 */ | |
| 82 | u16 fpga_features; /* 0x0004 */ | |
| 83 | u16 fpga_version; /* 0x0006 */ | |
| 84 | u16 reserved_0[8187]; /* 0x0008 */ | |
| 85 | u16 reflection_high; /* 0x3ffe */ | |
| 0e60aa85 | 86 | }; |
| 6e9e6c36 DE |
87 | #endif |
| 88 | ||
| d6918816 | 89 | #if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP) |
| 50dcf89d DE |
90 | struct ihs_fpga { |
| 91 | u16 reflection_low; /* 0x0000 */ | |
| 92 | u16 versions; /* 0x0002 */ | |
| 93 | u16 fpga_version; /* 0x0004 */ | |
| 94 | u16 fpga_features; /* 0x0006 */ | |
| 95 | u16 reserved_0[1]; /* 0x0008 */ | |
| 96 | u16 top_interrupt; /* 0x000a */ | |
| 7ed45d3d DE |
97 | u16 reserved_1[2]; /* 0x000c */ |
| 98 | u16 control; /* 0x0010 */ | |
| 99 | u16 extended_control; /* 0x0012 */ | |
| 0e60aa85 | 100 | struct ihs_gpio gpio; /* 0x0014 */ |
| 2da0fc0d | 101 | u16 mpc3w_control; /* 0x001a */ |
| 50dcf89d DE |
102 | u16 reserved_2[2]; /* 0x001c */ |
| 103 | struct ihs_io_ep ep; /* 0x0020 */ | |
| 104 | u16 reserved_3[9]; /* 0x002e */ | |
| 071be896 | 105 | struct ihs_i2c i2c0; /* 0x0040 */ |
| 50dcf89d | 106 | u16 reserved_4[10]; /* 0x004c */ |
| e50e8968 DE |
107 | u16 mc_int; /* 0x0060 */ |
| 108 | u16 mc_int_en; /* 0x0062 */ | |
| 109 | u16 mc_status; /* 0x0064 */ | |
| 110 | u16 mc_control; /* 0x0066 */ | |
| 111 | u16 mc_tx_data; /* 0x0068 */ | |
| 112 | u16 mc_tx_address; /* 0x006a */ | |
| 113 | u16 mc_tx_cmd; /* 0x006c */ | |
| 114 | u16 mc_res; /* 0x006e */ | |
| 115 | u16 mc_rx_cmd_status; /* 0x0070 */ | |
| 116 | u16 mc_rx_data; /* 0x0072 */ | |
| 50dcf89d | 117 | u16 reserved_5[69]; /* 0x0074 */ |
| 2da0fc0d | 118 | u16 reflection_high; /* 0x00fe */ |
| 7ed45d3d DE |
119 | struct ihs_osd osd0; /* 0x0100 */ |
| 120 | #ifdef CONFIG_SYS_OSD_DH | |
| 121 | u16 reserved_6[57]; /* 0x010e */ | |
| 122 | struct ihs_osd osd1; /* 0x0180 */ | |
| 123 | u16 reserved_7[9]; /* 0x018e */ | |
| 124 | struct ihs_i2c i2c1; /* 0x01a0 */ | |
| 125 | u16 reserved_8[1834]; /* 0x01ac */ | |
| 126 | u16 videomem0[2048]; /* 0x1000 */ | |
| 127 | u16 videomem1[2048]; /* 0x2000 */ | |
| 128 | #else | |
| 50dcf89d | 129 | u16 reserved_6[889]; /* 0x010e */ |
| 7ed45d3d DE |
130 | u16 videomem0[2048]; /* 0x0800 */ |
| 131 | #endif | |
| 0e60aa85 | 132 | }; |
| 2da0fc0d DE |
133 | #endif |
| 134 | ||
| a3f9d6c7 DE |
135 | #ifdef CONFIG_STRIDER_CPU |
| 136 | struct ihs_fpga { | |
| 137 | u16 reflection_low; /* 0x0000 */ | |
| 138 | u16 versions; /* 0x0002 */ | |
| 139 | u16 fpga_version; /* 0x0004 */ | |
| 140 | u16 fpga_features; /* 0x0006 */ | |
| 141 | u16 reserved_0[1]; /* 0x0008 */ | |
| 142 | u16 top_interrupt; /* 0x000a */ | |
| 143 | u16 reserved_1[3]; /* 0x000c */ | |
| 144 | u16 extended_control; /* 0x0012 */ | |
| 145 | struct ihs_gpio gpio; /* 0x0014 */ | |
| 146 | u16 mpc3w_control; /* 0x001a */ | |
| 147 | u16 reserved_2[2]; /* 0x001c */ | |
| 148 | struct ihs_io_ep ep; /* 0x0020 */ | |
| 149 | u16 reserved_3[9]; /* 0x002e */ | |
| 150 | u16 mc_int; /* 0x0040 */ | |
| 151 | u16 mc_int_en; /* 0x0042 */ | |
| 152 | u16 mc_status; /* 0x0044 */ | |
| 153 | u16 mc_control; /* 0x0046 */ | |
| 154 | u16 mc_tx_data; /* 0x0048 */ | |
| 155 | u16 mc_tx_address; /* 0x004a */ | |
| 156 | u16 mc_tx_cmd; /* 0x004c */ | |
| 157 | u16 mc_res; /* 0x004e */ | |
| 158 | u16 mc_rx_cmd_status; /* 0x0050 */ | |
| 159 | u16 mc_rx_data; /* 0x0052 */ | |
| 160 | u16 reserved_4[62]; /* 0x0054 */ | |
| 161 | struct ihs_i2c i2c0; /* 0x00d0 */ | |
| 162 | }; | |
| 163 | #endif | |
| 164 | ||
| 165 | #ifdef CONFIG_STRIDER_CON | |
| 166 | struct ihs_fpga { | |
| 167 | u16 reflection_low; /* 0x0000 */ | |
| 168 | u16 versions; /* 0x0002 */ | |
| 169 | u16 fpga_version; /* 0x0004 */ | |
| 170 | u16 fpga_features; /* 0x0006 */ | |
| 171 | u16 reserved_0[1]; /* 0x0008 */ | |
| 172 | u16 top_interrupt; /* 0x000a */ | |
| 173 | u16 reserved_1[4]; /* 0x000c */ | |
| 174 | struct ihs_gpio gpio; /* 0x0014 */ | |
| 175 | u16 mpc3w_control; /* 0x001a */ | |
| 176 | u16 reserved_2[2]; /* 0x001c */ | |
| 177 | struct ihs_io_ep ep; /* 0x0020 */ | |
| 178 | u16 reserved_3[9]; /* 0x002e */ | |
| 179 | struct ihs_i2c i2c0; /* 0x0040 */ | |
| 180 | u16 reserved_4[10]; /* 0x004c */ | |
| 181 | u16 mc_int; /* 0x0060 */ | |
| 182 | u16 mc_int_en; /* 0x0062 */ | |
| 183 | u16 mc_status; /* 0x0064 */ | |
| 184 | u16 mc_control; /* 0x0066 */ | |
| 185 | u16 mc_tx_data; /* 0x0068 */ | |
| 186 | u16 mc_tx_address; /* 0x006a */ | |
| 187 | u16 mc_tx_cmd; /* 0x006c */ | |
| 188 | u16 mc_res; /* 0x006e */ | |
| 189 | u16 mc_rx_cmd_status; /* 0x0070 */ | |
| 190 | u16 mc_rx_data; /* 0x0072 */ | |
| 191 | u16 reserved_5[70]; /* 0x0074 */ | |
| 7ed45d3d | 192 | struct ihs_osd osd0; /* 0x0100 */ |
| a3f9d6c7 | 193 | u16 reserved_6[889]; /* 0x010e */ |
| 7ed45d3d | 194 | u16 videomem0[2048]; /* 0x0800 */ |
| a3f9d6c7 DE |
195 | }; |
| 196 | #endif | |
| 197 | ||
| 2da0fc0d | 198 | #endif |