[J-u-boot.git] / drivers / i2c / designware_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, [email protected].
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <i2c.h>
#include <pci.h>
#include <reset.h>
#include <asm/io.h>
#include "designware_i2c.h"

/**
 * struct dw_i2c_speed_config - timings to use for a particular speed
 *
 * This holds calculated values to be written to the I2C controller. Each value
 * is represented as a number of IC clock cycles.
 *
 * @scl_lcnt: Low count value for SCL
 * @scl_hcnt: High count value for SCL
 * @sda_hold: Data hold count
 */
struct dw_i2c_speed_config {
	/* SCL high and low period count */
	uint scl_lcnt;
	uint scl_hcnt;
	uint sda_hold;
};

#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;

	writel(ena, &i2c_base->ic_enable);

	return 0;
}
#else
static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;
	int timeout = 100;

	do {
		writel(ena, &i2c_base->ic_enable);
		if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
			return 0;

		/*
		 * Wait 10 times the signaling period of the highest I2C
		 * transfer supported by the driver (for 400KHz this is
		 * 25us) as described in the DesignWare I2C databook.
		 */
		udelay(25);
	} while (timeout--);
	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");

	return -ETIMEDOUT;
}
#endif

/*
 * i2c_set_bus_speed - Set the i2c speed
 * @speed:	required i2c speed
 *
 * Set the i2c speed.
 */
static unsigned int __dw_i2c_set_bus_speed(struct dw_i2c *priv,
					   struct i2c_regs *i2c_base,
					   unsigned int speed,
					   unsigned int bus_clk)
{
	const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
	struct dw_i2c_speed_config config;
	ulong bus_khz = bus_clk / 1000;
	enum i2c_speed_mode i2c_spd;
	unsigned int cntl;
	unsigned int ena;

	if (priv)
		scl_sda_cfg = priv->scl_sda_cfg;
	/* Allow high speed if there is no config, or the config allows it */
	if (speed >= I2C_HIGH_SPEED &&
	    (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
		i2c_spd = IC_SPEED_MODE_HIGH;
	else if (speed >= I2C_FAST_SPEED)
		i2c_spd = IC_SPEED_MODE_FAST;
	else
		i2c_spd = IC_SPEED_MODE_STANDARD;

	/* Get enable setting for restore later */
	ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;

	/* to set speed cltr must be disabled */
	dw_i2c_enable(i2c_base, false);

	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

	config.scl_hcnt = 0;
	config.scl_lcnt = 0;
	config.sda_hold = 0;
	if (scl_sda_cfg) {
		config.sda_hold = scl_sda_cfg->sda_hold;
		if (i2c_spd == IC_SPEED_MODE_STANDARD) {
			config.scl_hcnt = scl_sda_cfg->ss_hcnt;
			config.scl_lcnt = scl_sda_cfg->ss_lcnt;
		} else {
			config.scl_hcnt = scl_sda_cfg->fs_hcnt;
			config.scl_lcnt = scl_sda_cfg->fs_lcnt;
		}
	}

	switch (i2c_spd) {
	case IC_SPEED_MODE_HIGH:
		cntl |= IC_CON_SPD_SS;
		if (!scl_sda_cfg) {
			config.scl_hcnt = (bus_khz * MIN_HS_SCL_HIGHTIME) /
				 NANO_TO_KILO;
			config.scl_lcnt = (bus_khz * MIN_HS_SCL_LOWTIME) /
				 NANO_TO_KILO;
		}
		writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
		writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
		break;

	case IC_SPEED_MODE_STANDARD:
		cntl |= IC_CON_SPD_SS;
		if (!scl_sda_cfg) {
			config.scl_hcnt = (bus_khz * MIN_SS_SCL_HIGHTIME) /
				 NANO_TO_KILO;
			config.scl_lcnt = (bus_khz * MIN_SS_SCL_LOWTIME) /
				 NANO_TO_KILO;
		}
		writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
		writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
		break;

	case IC_SPEED_MODE_FAST:
	default:
		cntl |= IC_CON_SPD_FS;
		if (!scl_sda_cfg) {
			config.scl_hcnt = (bus_khz * MIN_FS_SCL_HIGHTIME) /
				 NANO_TO_KILO;
			config.scl_lcnt = (bus_khz * MIN_FS_SCL_LOWTIME) /
				 NANO_TO_KILO;
		}
		writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
		writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
		break;
	}

	writel(cntl, &i2c_base->ic_con);

	/* Configure SDA Hold Time if required */
	if (config.sda_hold)
		writel(config.sda_hold, &i2c_base->ic_sda_hold);

	/* Restore back i2c now speed set */
	if (ena == IC_ENABLE_0B)
		dw_i2c_enable(i2c_base, true);

	return 0;
}

/*
 * i2c_setaddress - Sets the target slave address
 * @i2c_addr:	target i2c address
 *
 * Sets the target slave address.
 */
static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
{
	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel(i2c_addr, &i2c_base->ic_tar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 *
 * Flushes the i2c RX FIFO
 */
static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
{
	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
		readl(&i2c_base->ic_cmd_data);
}

/*
 * i2c_wait_for_bb - Waits for bus busy
 *
 * Waits for bus busy
 */
static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
{
	unsigned long start_time_bb = get_timer(0);

	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {

		/* Evaluate timeout */
		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
			return 1;
	}

	return 0;
}

static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
			 int alen)
{
	if (i2c_wait_for_bb(i2c_base))
		return 1;

	i2c_setaddress(i2c_base, chip);
	while (alen) {
		alen--;
		/* high byte address going out first */
		writel((addr >> (alen * 8)) & 0xff,
		       &i2c_base->ic_cmd_data);
	}
	return 0;
}

static int i2c_xfer_finish(struct i2c_regs *i2c_base)
{
	ulong start_stop_det = get_timer(0);

	while (1) {
		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
			readl(&i2c_base->ic_clr_stop_det);
			break;
		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
			break;
		}
	}

	if (i2c_wait_for_bb(i2c_base)) {
		printf("Timed out waiting for bus\n");
		return 1;
	}

	i2c_flush_rxfifo(i2c_base);

	return 0;
}

/*
 * i2c_read - Read from i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Read from i2c memory.
 */
static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
			 int alen, u8 *buffer, int len)
{
	unsigned long start_time_rx;
	unsigned int active = 0;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_rx = get_timer(0);
	while (len) {
		if (!active) {
			/*
			 * Avoid writing to ic_cmd_data multiple times
			 * in case this loop spins too quickly and the
			 * ic_status RFNE bit isn't set after the first
			 * write. Subsequent writes to ic_cmd_data can
			 * trigger spurious i2c transfer.
			 */
			if (len == 1)
				writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
			else
				writel(IC_CMD, &i2c_base->ic_cmd_data);
			active = 1;
		}

		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
			len--;
			start_time_rx = get_timer(0);
			active = 0;
		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
			return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * i2c_write - Write to i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Write to i2c memory.
 */
static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
			  int alen, u8 *buffer, int len)
{
	int nb = len;
	unsigned long start_time_tx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_tx = get_timer(0);
	while (len) {
		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
			if (--len == 0) {
				writel(*buffer | IC_STOP,
				       &i2c_base->ic_cmd_data);
			} else {
				writel(*buffer, &i2c_base->ic_cmd_data);
			}
			buffer++;
			start_time_tx = get_timer(0);

		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
				printf("Timed out. i2c write Failed\n");
				return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * __dw_i2c_init - Init function
 * @speed:	required i2c speed
 * @slaveaddr:	slave address for the device
 *
 * Initialization function.
 */
static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
{
	int ret;

	/* Disable i2c */
	ret = dw_i2c_enable(i2c_base, false);
	if (ret)
		return ret;

	writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
	       &i2c_base->ic_con);
	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
#ifndef CONFIG_DM_I2C
	__dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
	writel(slaveaddr, &i2c_base->ic_sar);
#endif

	/* Enable i2c */
	ret = dw_i2c_enable(i2c_base, true);
	if (ret)
		return ret;

	return 0;
}

#ifndef CONFIG_DM_I2C
/*
 * The legacy I2C functions. These need to get removed once
 * all users of this driver are converted to DM.
 */
static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 4
	case 3:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
	case 0:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	default:
		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	}

	return NULL;
}

static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
					 unsigned int speed)
{
	adap->speed = speed;
	return __dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
}

static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
}

static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
		       int alen, u8 *buffer, int len)
{
	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			int alen, u8 *buffer, int len)
{
	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

/* dw_i2c_probe - Probe the i2c chip */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	u32 tmp;
	int ret;

	/*
	 * Try to read the first location of the chip.
	 */
	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		dw_i2c_init(adap, adap->speed, adap->slaveaddr);

	return ret;
}

U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 4
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif

#else /* CONFIG_DM_I2C */
/* The DM I2C functions */

static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			       int nmsgs)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
					    msg->buf, msg->len);
		} else {
			ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
					     msg->buf, msg->len);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	return 0;
}

static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	ulong rate;

#if CONFIG_IS_ENABLED(CLK)
	rate = clk_get_rate(&i2c->clk);
	if (IS_ERR_VALUE(rate))
		return -EINVAL;
#else
	rate = IC_CLK;
#endif
	return __dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
}

static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
				     uint chip_flags)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	struct i2c_regs *i2c_base = i2c->regs;
	u32 tmp;
	int ret;

	/* Try to read the first location of the chip */
	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		__dw_i2c_init(i2c_base, 0, 0);

	return ret;
}

int designware_i2c_ofdata_to_platdata(struct udevice *bus)
{
	struct dw_i2c *priv = dev_get_priv(bus);

	if (!priv->regs)
		priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
	dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
	dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
	dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);

	return 0;
}

int designware_i2c_probe(struct udevice *bus)
{
	struct dw_i2c *priv = dev_get_priv(bus);
	int ret;

	ret = reset_get_bulk(bus, &priv->resets);
	if (ret)
		dev_warn(bus, "Can't get reset: %d\n", ret);
	else
		reset_deassert_bulk(&priv->resets);

#if CONFIG_IS_ENABLED(CLK)
	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret)
		return ret;

	ret = clk_enable(&priv->clk);
	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
		clk_free(&priv->clk);
		dev_err(bus, "failed to enable clock\n");
		return ret;
	}
#endif

	return __dw_i2c_init(priv->regs, 0, 0);
}

int designware_i2c_remove(struct udevice *dev)
{
	struct dw_i2c *priv = dev_get_priv(dev);

#if CONFIG_IS_ENABLED(CLK)
	clk_disable(&priv->clk);
	clk_free(&priv->clk);
#endif

	return reset_release_bulk(&priv->resets);
}

const struct dm_i2c_ops designware_i2c_ops = {
	.xfer		= designware_i2c_xfer,
	.probe_chip	= designware_i2c_probe_chip,
	.set_bus_speed	= designware_i2c_set_bus_speed,
};

static const struct udevice_id designware_i2c_ids[] = {
	{ .compatible = "snps,designware-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_designware) = {
	.name	= "i2c_designware",
	.id	= UCLASS_I2C,
	.of_match = designware_i2c_ids,
	.ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
	.probe	= designware_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct dw_i2c),
	.remove = designware_i2c_remove,
	.flags	= DM_FLAG_OS_PREPARE,
	.ops	= &designware_i2c_ops,
};

#endif /* CONFIG_DM_I2C */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
2403f8f4 VK	2	/*
	3	* (C) Copyright 2009
	4	* Vipin Kumar, ST Micoelectronics, [email protected].
2403f8f4 VK	5	*/
	6
	7	#include <common.h>
afb88651	8	#include <clk.h>
334b9b00	9	#include <dm.h>
678398b1	10	#include <i2c.h>
ba5da550	11	#include <pci.h>
622597de	12	#include <reset.h>
2403f8f4	13	#include <asm/io.h>
031ed2fa	14	#include "designware_i2c.h"
2403f8f4	15
31adb873 SG	16	/**
	17	* struct dw_i2c_speed_config - timings to use for a particular speed
	18	*
	19	* This holds calculated values to be written to the I2C controller. Each value
	20	* is represented as a number of IC clock cycles.
	21	*
	22	* @scl_lcnt: Low count value for SCL
	23	* @scl_hcnt: High count value for SCL
	24	* @sda_hold: Data hold count
	25	*/
	26	struct dw_i2c_speed_config {
	27	/* SCL high and low period count */
	28	uint scl_lcnt;
	29	uint scl_hcnt;
	30	uint sda_hold;
	31	};
	32
b6a77b0c	33	#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
2b5d029d	34	static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
b6a77b0c SR	35	{
	36	u32 ena = enable ? IC_ENABLE_0B : 0;
	37
	38	writel(ena, &i2c_base->ic_enable);
2b5d029d SG	39
2b5d029d SG	40	return 0;
b6a77b0c SR	41	}
b6a77b0c SR	42	#else
2b5d029d	43	static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
1c8b089b SR	44	{
	45	u32 ena = enable ? IC_ENABLE_0B : 0;
	46	int timeout = 100;
	47
	48	do {
	49	writel(ena, &i2c_base->ic_enable);
	50	if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
2b5d029d	51	return 0;
1c8b089b SR	52
	53	/*
	54	* Wait 10 times the signaling period of the highest I2C
	55	* transfer supported by the driver (for 400KHz this is
	56	* 25us) as described in the DesignWare I2C databook.
	57	*/
	58	udelay(25);
	59	} while (timeout--);
1c8b089b	60	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
2b5d029d SG	61
2b5d029d SG	62	return -ETIMEDOUT;
1c8b089b	63	}
b6a77b0c	64	#endif
1c8b089b	65
2403f8f4	66	/*
11b544ab SR	67	* i2c_set_bus_speed - Set the i2c speed
11b544ab SR	68	* @speed: required i2c speed
2403f8f4	69	*
11b544ab	70	* Set the i2c speed.
2403f8f4	71	*/
d22409e2 SG	72	static unsigned int __dw_i2c_set_bus_speed(struct dw_i2c *priv,
d22409e2 SG	73	struct i2c_regs *i2c_base,
2d1e879c	74	unsigned int speed,
dd3c1602	75	unsigned int bus_clk)
2403f8f4	76	{
d22409e2	77	const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
31adb873	78	struct dw_i2c_speed_config config;
dd3c1602	79	ulong bus_khz = bus_clk / 1000;
65190d15	80	enum i2c_speed_mode i2c_spd;
2403f8f4	81	unsigned int cntl;
e3b93dce	82	unsigned int ena;
11b544ab	83
d22409e2 SG	84	if (priv)
d22409e2 SG	85	scl_sda_cfg = priv->scl_sda_cfg;
6db7943b SG	86	/* Allow high speed if there is no config, or the config allows it */
	87	if (speed >= I2C_HIGH_SPEED &&
	88	(!scl_sda_cfg \|\| scl_sda_cfg->has_high_speed))
	89	i2c_spd = IC_SPEED_MODE_HIGH;
11b544ab SR	90	else if (speed >= I2C_FAST_SPEED)
	91	i2c_spd = IC_SPEED_MODE_FAST;
	92	else
	93	i2c_spd = IC_SPEED_MODE_STANDARD;
5e3e8dda	94
e3b93dce JC	95	/* Get enable setting for restore later */
	96	ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
	97
5e3e8dda	98	/* to set speed cltr must be disabled */
1c8b089b	99	dw_i2c_enable(i2c_base, false);
5e3e8dda	100
678398b1	101	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
2403f8f4	102
31adb873 SG	103	config.scl_hcnt = 0;
	104	config.scl_lcnt = 0;
	105	config.sda_hold = 0;
	106	if (scl_sda_cfg) {
	107	config.sda_hold = scl_sda_cfg->sda_hold;
	108	if (i2c_spd == IC_SPEED_MODE_STANDARD) {
	109	config.scl_hcnt = scl_sda_cfg->ss_hcnt;
	110	config.scl_lcnt = scl_sda_cfg->ss_lcnt;
	111	} else {
	112	config.scl_hcnt = scl_sda_cfg->fs_hcnt;
	113	config.scl_lcnt = scl_sda_cfg->fs_lcnt;
	114	}
	115	}
	116
2403f8f4	117	switch (i2c_spd) {
6db7943b	118	case IC_SPEED_MODE_HIGH:
ba5da550	119	cntl \|= IC_CON_SPD_SS;
31adb873 SG	120	if (!scl_sda_cfg) {
	121	config.scl_hcnt = (bus_khz * MIN_HS_SCL_HIGHTIME) /
	122	NANO_TO_KILO;
	123	config.scl_lcnt = (bus_khz * MIN_HS_SCL_LOWTIME) /
	124	NANO_TO_KILO;
ba5da550	125	}
31adb873 SG	126	writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
31adb873 SG	127	writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
2403f8f4 VK	128	break;
	129
	130	case IC_SPEED_MODE_STANDARD:
	131	cntl \|= IC_CON_SPD_SS;
31adb873 SG	132	if (!scl_sda_cfg) {
	133	config.scl_hcnt = (bus_khz * MIN_SS_SCL_HIGHTIME) /
	134	NANO_TO_KILO;
	135	config.scl_lcnt = (bus_khz * MIN_SS_SCL_LOWTIME) /
	136	NANO_TO_KILO;
ba5da550	137	}
31adb873 SG	138	writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
31adb873 SG	139	writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
2403f8f4 VK	140	break;
	141
	142	case IC_SPEED_MODE_FAST:
	143	default:
	144	cntl \|= IC_CON_SPD_FS;
31adb873 SG	145	if (!scl_sda_cfg) {
	146	config.scl_hcnt = (bus_khz * MIN_FS_SCL_HIGHTIME) /
	147	NANO_TO_KILO;
	148	config.scl_lcnt = (bus_khz * MIN_FS_SCL_LOWTIME) /
	149	NANO_TO_KILO;
ba5da550	150	}
31adb873 SG	151	writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
31adb873 SG	152	writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
2403f8f4 VK	153	break;
	154	}
	155
678398b1	156	writel(cntl, &i2c_base->ic_con);
2403f8f4	157
ba5da550	158	/* Configure SDA Hold Time if required */
31adb873 SG	159	if (config.sda_hold)
31adb873 SG	160	writel(config.sda_hold, &i2c_base->ic_sda_hold);
ba5da550	161
e3b93dce JC	162	/* Restore back i2c now speed set */
	163	if (ena == IC_ENABLE_0B)
	164	dw_i2c_enable(i2c_base, true);
496ba48f	165
2403f8f4 VK	166	return 0;
	167	}
	168
2403f8f4 VK	169	/*
	170	* i2c_setaddress - Sets the target slave address
	171	* @i2c_addr: target i2c address
	172	*
	173	* Sets the target slave address.
	174	*/
3f4358da	175	static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
2403f8f4	176	{
8b7c8725	177	/* Disable i2c */
1c8b089b	178	dw_i2c_enable(i2c_base, false);
8b7c8725	179
678398b1	180	writel(i2c_addr, &i2c_base->ic_tar);
8b7c8725 AB	181
8b7c8725 AB	182	/* Enable i2c */
1c8b089b	183	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	184	}
	185
	186	/*
	187	* i2c_flush_rxfifo - Flushes the i2c RX FIFO
	188	*
	189	* Flushes the i2c RX FIFO
	190	*/
3f4358da	191	static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
2403f8f4	192	{
678398b1 SR	193	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
678398b1 SR	194	readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	195	}
	196
	197	/*
	198	* i2c_wait_for_bb - Waits for bus busy
	199	*
	200	* Waits for bus busy
	201	*/
3f4358da	202	static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
2403f8f4 VK	203	{
	204	unsigned long start_time_bb = get_timer(0);
	205
678398b1 SR	206	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) \|\|
678398b1 SR	207	!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
2403f8f4 VK	208
	209	/* Evaluate timeout */
	210	if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	211	return 1;
	212	}
	213
	214	return 0;
	215	}
	216
3f4358da	217	static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
678398b1	218	int alen)
2403f8f4	219	{
3f4358da	220	if (i2c_wait_for_bb(i2c_base))
2403f8f4	221	return 1;
2403f8f4	222
3f4358da	223	i2c_setaddress(i2c_base, chip);
070cbaf8 CLS	224	while (alen) {
	225	alen--;
	226	/* high byte address going out first */
	227	writel((addr >> (alen * 8)) & 0xff,
678398b1	228	&i2c_base->ic_cmd_data);
070cbaf8	229	}
2403f8f4 VK	230	return 0;
	231	}
	232
3f4358da	233	static int i2c_xfer_finish(struct i2c_regs *i2c_base)
2403f8f4 VK	234	{
	235	ulong start_stop_det = get_timer(0);
	236
	237	while (1) {
678398b1 SR	238	if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
678398b1 SR	239	readl(&i2c_base->ic_clr_stop_det);
2403f8f4 VK	240	break;
	241	} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	242	break;
	243	}
	244	}
	245
3f4358da	246	if (i2c_wait_for_bb(i2c_base)) {
2403f8f4 VK	247	printf("Timed out waiting for bus\n");
	248	return 1;
	249	}
	250
3f4358da	251	i2c_flush_rxfifo(i2c_base);
2403f8f4	252
2403f8f4 VK	253	return 0;
	254	}
	255
	256	/*
	257	* i2c_read - Read from i2c memory
	258	* @chip: target i2c address
	259	* @addr: address to read from
	260	* @alen:
	261	* @buffer: buffer for read data
	262	* @len: no of bytes to be read
	263	*
	264	* Read from i2c memory.
	265	*/
3f4358da SR	266	static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	267	int alen, u8 *buffer, int len)
2403f8f4 VK	268	{
2403f8f4 VK	269	unsigned long start_time_rx;
b0338080	270	unsigned int active = 0;
2403f8f4	271
32d041e2 AB	272	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	273	/*
	274	* EEPROM chips that implement "address overflow" are ones
	275	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	276	* address and the extra bits end up in the "chip address"
	277	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	278	* four 256 byte chips.
	279	*
	280	* Note that we consider the length of the address field to
	281	* still be one byte because the extra address bits are
	282	* hidden in the chip address.
	283	*/
678398b1	284	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	285	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	286
678398b1	287	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	288	addr);
	289	#endif
	290
3f4358da	291	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	292	return 1;
	293
	294	start_time_rx = get_timer(0);
	295	while (len) {
b0338080 MV	296	if (!active) {
	297	/*
	298	* Avoid writing to ic_cmd_data multiple times
	299	* in case this loop spins too quickly and the
	300	* ic_status RFNE bit isn't set after the first
	301	* write. Subsequent writes to ic_cmd_data can
	302	* trigger spurious i2c transfer.
	303	*/
	304	if (len == 1)
	305	writel(IC_CMD \| IC_STOP, &i2c_base->ic_cmd_data);
	306	else
	307	writel(IC_CMD, &i2c_base->ic_cmd_data);
	308	active = 1;
	309	}
2403f8f4	310
678398b1 SR	311	if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
678398b1 SR	312	*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	313	len--;
2403f8f4 VK	314	start_time_rx = get_timer(0);
b0338080	315	active = 0;
2403f8f4	316	} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
b0338080	317	return 1;
2403f8f4 VK	318	}
	319	}
	320
3f4358da	321	return i2c_xfer_finish(i2c_base);
2403f8f4 VK	322	}
	323
	324	/*
	325	* i2c_write - Write to i2c memory
	326	* @chip: target i2c address
	327	* @addr: address to read from
	328	* @alen:
	329	* @buffer: buffer for read data
	330	* @len: no of bytes to be read
	331	*
	332	* Write to i2c memory.
	333	*/
3f4358da SR	334	static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	335	int alen, u8 *buffer, int len)
2403f8f4 VK	336	{
	337	int nb = len;
	338	unsigned long start_time_tx;
	339
32d041e2 AB	340	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	341	/*
	342	* EEPROM chips that implement "address overflow" are ones
	343	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	344	* address and the extra bits end up in the "chip address"
	345	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	346	* four 256 byte chips.
	347	*
	348	* Note that we consider the length of the address field to
	349	* still be one byte because the extra address bits are
	350	* hidden in the chip address.
	351	*/
678398b1	352	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	353	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	354
678398b1	355	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	356	addr);
	357	#endif
	358
3f4358da	359	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	360	return 1;
	361
	362	start_time_tx = get_timer(0);
	363	while (len) {
678398b1 SR	364	if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
	365	if (--len == 0) {
	366	writel(*buffer \| IC_STOP,
	367	&i2c_base->ic_cmd_data);
	368	} else {
	369	writel(*buffer, &i2c_base->ic_cmd_data);
	370	}
2403f8f4	371	buffer++;
2403f8f4 VK	372	start_time_tx = get_timer(0);
	373
	374	} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	375	printf("Timed out. i2c write Failed\n");
	376	return 1;
	377	}
	378	}
	379
3f4358da SR	380	return i2c_xfer_finish(i2c_base);
	381	}
	382
334b9b00 SR	383	/*
	384	* __dw_i2c_init - Init function
	385	* @speed: required i2c speed
	386	* @slaveaddr: slave address for the device
	387	*
	388	* Initialization function.
	389	*/
2b5d029d	390	static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
334b9b00	391	{
2b5d029d SG	392	int ret;
2b5d029d SG	393
334b9b00	394	/* Disable i2c */
2b5d029d SG	395	ret = dw_i2c_enable(i2c_base, false);
	396	if (ret)
	397	return ret;
334b9b00	398
014e47f0 MV	399	writel(IC_CON_SD \| IC_CON_RE \| IC_CON_SPD_FS \| IC_CON_MM,
014e47f0 MV	400	&i2c_base->ic_con);
334b9b00 SR	401	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	402	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	403	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	404	#ifndef CONFIG_DM_I2C
d22409e2	405	__dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
334b9b00 SR	406	writel(slaveaddr, &i2c_base->ic_sar);
	407	#endif
	408
	409	/* Enable i2c */
2b5d029d SG	410	ret = dw_i2c_enable(i2c_base, true);
	411	if (ret)
	412	return ret;
	413
	414	return 0;
334b9b00 SR	415	}
	416
	417	#ifndef CONFIG_DM_I2C
	418	/*
	419	* The legacy I2C functions. These need to get removed once
	420	* all users of this driver are converted to DM.
	421	*/
3f4358da SR	422	static struct i2c_regs i2c_get_base(struct i2c_adapter adap)
	423	{
	424	switch (adap->hwadapnr) {
	425	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	426	case 3:
	427	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
	428	#endif
	429	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	430	case 2:
	431	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
	432	#endif
	433	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	434	case 1:
	435	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
	436	#endif
	437	case 0:
	438	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	439	default:
	440	printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	441	}
	442
	443	return NULL;
	444	}
	445
	446	static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
	447	unsigned int speed)
	448	{
	449	adap->speed = speed;
d22409e2	450	return __dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
3f4358da SR	451	}
3f4358da SR	452
334b9b00	453	static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
3f4358da	454	{
334b9b00	455	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
3f4358da SR	456	}
	457
	458	static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
	459	int alen, u8 *buffer, int len)
	460	{
	461	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
	462	}
	463
	464	static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
	465	int alen, u8 *buffer, int len)
	466	{
	467	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
2403f8f4 VK	468	}
2403f8f4 VK	469
334b9b00	470	/* dw_i2c_probe - Probe the i2c chip */
678398b1	471	static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
2403f8f4	472	{
3f4358da	473	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4	474	u32 tmp;
496ba48f	475	int ret;
2403f8f4 VK	476
	477	/*
	478	* Try to read the first location of the chip.
	479	*/
3f4358da	480	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
496ba48f	481	if (ret)
678398b1	482	dw_i2c_init(adap, adap->speed, adap->slaveaddr);
496ba48f SR	483
496ba48f SR	484	return ret;
2403f8f4	485	}
ac6e2fe6	486
678398b1 SR	487	U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	488	dw_i2c_write, dw_i2c_set_bus_speed,
	489	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
ac6e2fe6	490
678398b1 SR	491	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	492	U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	493	dw_i2c_write, dw_i2c_set_bus_speed,
	494	CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
	495	#endif
ac6e2fe6	496
678398b1 SR	497	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	498	U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	499	dw_i2c_write, dw_i2c_set_bus_speed,
	500	CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
	501	#endif
ac6e2fe6	502
678398b1 SR	503	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	504	U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	505	dw_i2c_write, dw_i2c_set_bus_speed,
	506	CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
ac6e2fe6	507	#endif
334b9b00 SR	508
	509	#else /* CONFIG_DM_I2C */
	510	/* The DM I2C functions */
	511
	512	static int designware_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	513	int nmsgs)
	514	{
	515	struct dw_i2c *i2c = dev_get_priv(bus);
	516	int ret;
	517
	518	debug("i2c_xfer: %d messages\n", nmsgs);
	519	for (; nmsgs > 0; nmsgs--, msg++) {
	520	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	521	if (msg->flags & I2C_M_RD) {
	522	ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
	523	msg->buf, msg->len);
	524	} else {
	525	ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
	526	msg->buf, msg->len);
	527	}
	528	if (ret) {
	529	debug("i2c_write: error sending\n");
	530	return -EREMOTEIO;
	531	}
	532	}
	533
	534	return 0;
	535	}
	536
	537	static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	538	{
	539	struct dw_i2c *i2c = dev_get_priv(bus);
2d1e879c LFT	540	ulong rate;
	541
	542	#if CONFIG_IS_ENABLED(CLK)
	543	rate = clk_get_rate(&i2c->clk);
	544	if (IS_ERR_VALUE(rate))
	545	return -EINVAL;
2d1e879c LFT	546	#else
	547	rate = IC_CLK;
	548	#endif
d22409e2	549	return __dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
334b9b00 SR	550	}
	551
	552	static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
	553	uint chip_flags)
	554	{
	555	struct dw_i2c *i2c = dev_get_priv(bus);
	556	struct i2c_regs *i2c_base = i2c->regs;
	557	u32 tmp;
	558	int ret;
	559
	560	/* Try to read the first location of the chip */
	561	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	562	if (ret)
	563	__dw_i2c_init(i2c_base, 0, 0);
	564
	565	return ret;
	566	}
	567
80a03db4	568	int designware_i2c_ofdata_to_platdata(struct udevice *bus)
334b9b00 SR	569	{
	570	struct dw_i2c *priv = dev_get_priv(bus);
	571
80a03db4 SG	572	if (!priv->regs)
	573	priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
	574	dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
	575	dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
	576	dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
457df233 SG	577
	578	return 0;
	579	}
	580
	581	int designware_i2c_probe(struct udevice *bus)
	582	{
	583	struct dw_i2c *priv = dev_get_priv(bus);
	584	int ret;
334b9b00	585
36821b3f	586	ret = reset_get_bulk(bus, &priv->resets);
622597de	587	if (ret)
36821b3f SG	588	dev_warn(bus, "Can't get reset: %d\n", ret);
	589	else
	590	reset_deassert_bulk(&priv->resets);
622597de	591
2d1e879c LFT	592	#if CONFIG_IS_ENABLED(CLK)
	593	ret = clk_get_by_index(bus, 0, &priv->clk);
	594	if (ret)
	595	return ret;
	596
	597	ret = clk_enable(&priv->clk);
	598	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
	599	clk_free(&priv->clk);
	600	dev_err(bus, "failed to enable clock\n");
	601	return ret;
	602	}
	603	#endif
	604
2b5d029d	605	return __dw_i2c_init(priv->regs, 0, 0);
334b9b00 SR	606	}
334b9b00 SR	607
457df233	608	int designware_i2c_remove(struct udevice *dev)
36821b3f SG	609	{
	610	struct dw_i2c *priv = dev_get_priv(dev);
	611
2d1e879c LFT	612	#if CONFIG_IS_ENABLED(CLK)
	613	clk_disable(&priv->clk);
	614	clk_free(&priv->clk);
	615	#endif
	616
36821b3f SG	617	return reset_release_bulk(&priv->resets);
	618	}
	619
457df233	620	const struct dm_i2c_ops designware_i2c_ops = {
334b9b00 SR	621	.xfer = designware_i2c_xfer,
	622	.probe_chip = designware_i2c_probe_chip,
	623	.set_bus_speed = designware_i2c_set_bus_speed,
	624	};
	625
	626	static const struct udevice_id designware_i2c_ids[] = {
	627	{ .compatible = "snps,designware-i2c" },
	628	{ }
	629	};
	630
	631	U_BOOT_DRIVER(i2c_designware) = {
	632	.name = "i2c_designware",
	633	.id = UCLASS_I2C,
	634	.of_match = designware_i2c_ids,
457df233	635	.ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
334b9b00 SR	636	.probe = designware_i2c_probe,
334b9b00 SR	637	.priv_auto_alloc_size = sizeof(struct dw_i2c),
36821b3f	638	.remove = designware_i2c_remove,
457df233	639	.flags = DM_FLAG_OS_PREPARE,
334b9b00 SR	640	.ops = &designware_i2c_ops,
	641	};
	642
	643	#endif /* CONFIG_DM_I2C */