[J-u-boot.git] / drivers / i2c / designware_i2c.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2009
 * Vipin Kumar, ST Micoelectronics, [email protected].
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <i2c.h>
#include <pci.h>
#include <reset.h>
#include <asm/io.h>
#include "designware_i2c.h"

#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;

	writel(ena, &i2c_base->ic_enable);

	return 0;
}
#else
static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
{
	u32 ena = enable ? IC_ENABLE_0B : 0;
	int timeout = 100;

	do {
		writel(ena, &i2c_base->ic_enable);
		if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
			return 0;

		/*
		 * Wait 10 times the signaling period of the highest I2C
		 * transfer supported by the driver (for 400KHz this is
		 * 25us) as described in the DesignWare I2C databook.
		 */
		udelay(25);
	} while (timeout--);
	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");

	return -ETIMEDOUT;
}
#endif

/*
 * i2c_set_bus_speed - Set the i2c speed
 * @speed:	required i2c speed
 *
 * Set the i2c speed.
 */
static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
					   struct dw_scl_sda_cfg *scl_sda_cfg,
					   unsigned int speed,
					   unsigned int bus_clk)
{
	ulong bus_khz = bus_clk / 1000;
	enum i2c_speed_mode i2c_spd;
	unsigned int cntl;
	unsigned int hcnt, lcnt;
	unsigned int ena;

	/* Allow high speed if there is no config, or the config allows it */
	if (speed >= I2C_HIGH_SPEED &&
	    (!scl_sda_cfg || scl_sda_cfg->has_high_speed))
		i2c_spd = IC_SPEED_MODE_HIGH;
	else if (speed >= I2C_FAST_SPEED)
		i2c_spd = IC_SPEED_MODE_FAST;
	else
		i2c_spd = IC_SPEED_MODE_STANDARD;

	/* Get enable setting for restore later */
	ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;

	/* to set speed cltr must be disabled */
	dw_i2c_enable(i2c_base, false);

	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));

	switch (i2c_spd) {
	case IC_SPEED_MODE_HIGH:
		cntl |= IC_CON_SPD_SS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->fs_hcnt;
			lcnt = scl_sda_cfg->fs_lcnt;
		} else {
			hcnt = (bus_khz * MIN_HS_SCL_HIGHTIME) / NANO_TO_KILO;
			lcnt = (bus_khz * MIN_HS_SCL_LOWTIME) / NANO_TO_KILO;
		}
		writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
		writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
		break;

	case IC_SPEED_MODE_STANDARD:
		cntl |= IC_CON_SPD_SS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->ss_hcnt;
			lcnt = scl_sda_cfg->ss_lcnt;
		} else {
			hcnt = (bus_khz * MIN_SS_SCL_HIGHTIME) / NANO_TO_KILO;
			lcnt = (bus_khz * MIN_SS_SCL_LOWTIME) / NANO_TO_KILO;
		}
		writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
		writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
		break;

	case IC_SPEED_MODE_FAST:
	default:
		cntl |= IC_CON_SPD_FS;
		if (scl_sda_cfg) {
			hcnt = scl_sda_cfg->fs_hcnt;
			lcnt = scl_sda_cfg->fs_lcnt;
		} else {
			hcnt = (bus_khz * MIN_FS_SCL_HIGHTIME) / NANO_TO_KILO;
			lcnt = (bus_khz * MIN_FS_SCL_LOWTIME) / NANO_TO_KILO;
		}
		writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
		writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
		break;
	}

	writel(cntl, &i2c_base->ic_con);

	/* Configure SDA Hold Time if required */
	if (scl_sda_cfg)
		writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);

	/* Restore back i2c now speed set */
	if (ena == IC_ENABLE_0B)
		dw_i2c_enable(i2c_base, true);

	return 0;
}

/*
 * i2c_setaddress - Sets the target slave address
 * @i2c_addr:	target i2c address
 *
 * Sets the target slave address.
 */
static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
{
	/* Disable i2c */
	dw_i2c_enable(i2c_base, false);

	writel(i2c_addr, &i2c_base->ic_tar);

	/* Enable i2c */
	dw_i2c_enable(i2c_base, true);
}

/*
 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 *
 * Flushes the i2c RX FIFO
 */
static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
{
	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
		readl(&i2c_base->ic_cmd_data);
}

/*
 * i2c_wait_for_bb - Waits for bus busy
 *
 * Waits for bus busy
 */
static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
{
	unsigned long start_time_bb = get_timer(0);

	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
	       !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {

		/* Evaluate timeout */
		if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
			return 1;
	}

	return 0;
}

static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
			 int alen)
{
	if (i2c_wait_for_bb(i2c_base))
		return 1;

	i2c_setaddress(i2c_base, chip);
	while (alen) {
		alen--;
		/* high byte address going out first */
		writel((addr >> (alen * 8)) & 0xff,
		       &i2c_base->ic_cmd_data);
	}
	return 0;
}

static int i2c_xfer_finish(struct i2c_regs *i2c_base)
{
	ulong start_stop_det = get_timer(0);

	while (1) {
		if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
			readl(&i2c_base->ic_clr_stop_det);
			break;
		} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
			break;
		}
	}

	if (i2c_wait_for_bb(i2c_base)) {
		printf("Timed out waiting for bus\n");
		return 1;
	}

	i2c_flush_rxfifo(i2c_base);

	return 0;
}

/*
 * i2c_read - Read from i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Read from i2c memory.
 */
static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
			 int alen, u8 *buffer, int len)
{
	unsigned long start_time_rx;
	unsigned int active = 0;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_rx = get_timer(0);
	while (len) {
		if (!active) {
			/*
			 * Avoid writing to ic_cmd_data multiple times
			 * in case this loop spins too quickly and the
			 * ic_status RFNE bit isn't set after the first
			 * write. Subsequent writes to ic_cmd_data can
			 * trigger spurious i2c transfer.
			 */
			if (len == 1)
				writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
			else
				writel(IC_CMD, &i2c_base->ic_cmd_data);
			active = 1;
		}

		if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
			*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
			len--;
			start_time_rx = get_timer(0);
			active = 0;
		} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
			return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * i2c_write - Write to i2c memory
 * @chip:	target i2c address
 * @addr:	address to read from
 * @alen:
 * @buffer:	buffer for read data
 * @len:	no of bytes to be read
 *
 * Write to i2c memory.
 */
static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
			  int alen, u8 *buffer, int len)
{
	int nb = len;
	unsigned long start_time_tx;

#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones
	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	 * address and the extra bits end up in the "chip address"
	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
	 * four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to
	 * still be one byte because the extra address bits are
	 * hidden in the chip address.
	 */
	dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));

	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
	      addr);
#endif

	if (i2c_xfer_init(i2c_base, dev, addr, alen))
		return 1;

	start_time_tx = get_timer(0);
	while (len) {
		if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
			if (--len == 0) {
				writel(*buffer | IC_STOP,
				       &i2c_base->ic_cmd_data);
			} else {
				writel(*buffer, &i2c_base->ic_cmd_data);
			}
			buffer++;
			start_time_tx = get_timer(0);

		} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
				printf("Timed out. i2c write Failed\n");
				return 1;
		}
	}

	return i2c_xfer_finish(i2c_base);
}

/*
 * __dw_i2c_init - Init function
 * @speed:	required i2c speed
 * @slaveaddr:	slave address for the device
 *
 * Initialization function.
 */
static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
{
	int ret;

	/* Disable i2c */
	ret = dw_i2c_enable(i2c_base, false);
	if (ret)
		return ret;

	writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
	       &i2c_base->ic_con);
	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
#ifndef CONFIG_DM_I2C
	__dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK);
	writel(slaveaddr, &i2c_base->ic_sar);
#endif

	/* Enable i2c */
	ret = dw_i2c_enable(i2c_base, true);
	if (ret)
		return ret;

	return 0;
}

#ifndef CONFIG_DM_I2C
/*
 * The legacy I2C functions. These need to get removed once
 * all users of this driver are converted to DM.
 */
static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
{
	switch (adap->hwadapnr) {
#if CONFIG_SYS_I2C_BUS_MAX >= 4
	case 3:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 3
	case 2:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
#endif
#if CONFIG_SYS_I2C_BUS_MAX >= 2
	case 1:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
#endif
	case 0:
		return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	default:
		printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	}

	return NULL;
}

static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
					 unsigned int speed)
{
	adap->speed = speed;
	return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK);
}

static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
{
	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
}

static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
		       int alen, u8 *buffer, int len)
{
	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
			int alen, u8 *buffer, int len)
{
	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
}

/* dw_i2c_probe - Probe the i2c chip */
static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
{
	struct i2c_regs *i2c_base = i2c_get_base(adap);
	u32 tmp;
	int ret;

	/*
	 * Try to read the first location of the chip.
	 */
	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		dw_i2c_init(adap, adap->speed, adap->slaveaddr);

	return ret;
}

U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)

#if CONFIG_SYS_I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
#endif

#if CONFIG_SYS_I2C_BUS_MAX >= 4
U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
			 dw_i2c_write, dw_i2c_set_bus_speed,
			 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
#endif

#else /* CONFIG_DM_I2C */
/* The DM I2C functions */

static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
			       int nmsgs)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	int ret;

	debug("i2c_xfer: %d messages\n", nmsgs);
	for (; nmsgs > 0; nmsgs--, msg++) {
		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
		if (msg->flags & I2C_M_RD) {
			ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
					    msg->buf, msg->len);
		} else {
			ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
					     msg->buf, msg->len);
		}
		if (ret) {
			debug("i2c_write: error sending\n");
			return -EREMOTEIO;
		}
	}

	return 0;
}

static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	ulong rate;

#if CONFIG_IS_ENABLED(CLK)
	rate = clk_get_rate(&i2c->clk);
	if (IS_ERR_VALUE(rate))
		return -EINVAL;
#else
	rate = IC_CLK;
#endif
	return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed,
				      rate);
}

static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
				     uint chip_flags)
{
	struct dw_i2c *i2c = dev_get_priv(bus);
	struct i2c_regs *i2c_base = i2c->regs;
	u32 tmp;
	int ret;

	/* Try to read the first location of the chip */
	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	if (ret)
		__dw_i2c_init(i2c_base, 0, 0);

	return ret;
}

int designware_i2c_ofdata_to_platdata(struct udevice *bus)
{
	struct dw_i2c *priv = dev_get_priv(bus);

	if (!priv->regs)
		priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
	dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
	dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
	dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);

	return 0;
}

int designware_i2c_probe(struct udevice *bus)
{
	struct dw_i2c *priv = dev_get_priv(bus);
	int ret;

	ret = reset_get_bulk(bus, &priv->resets);
	if (ret)
		dev_warn(bus, "Can't get reset: %d\n", ret);
	else
		reset_deassert_bulk(&priv->resets);

#if CONFIG_IS_ENABLED(CLK)
	ret = clk_get_by_index(bus, 0, &priv->clk);
	if (ret)
		return ret;

	ret = clk_enable(&priv->clk);
	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
		clk_free(&priv->clk);
		dev_err(bus, "failed to enable clock\n");
		return ret;
	}
#endif

	return __dw_i2c_init(priv->regs, 0, 0);
}

int designware_i2c_remove(struct udevice *dev)
{
	struct dw_i2c *priv = dev_get_priv(dev);

#if CONFIG_IS_ENABLED(CLK)
	clk_disable(&priv->clk);
	clk_free(&priv->clk);
#endif

	return reset_release_bulk(&priv->resets);
}

const struct dm_i2c_ops designware_i2c_ops = {
	.xfer		= designware_i2c_xfer,
	.probe_chip	= designware_i2c_probe_chip,
	.set_bus_speed	= designware_i2c_set_bus_speed,
};

static const struct udevice_id designware_i2c_ids[] = {
	{ .compatible = "snps,designware-i2c" },
	{ }
};

U_BOOT_DRIVER(i2c_designware) = {
	.name	= "i2c_designware",
	.id	= UCLASS_I2C,
	.of_match = designware_i2c_ids,
	.ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
	.probe	= designware_i2c_probe,
	.priv_auto_alloc_size = sizeof(struct dw_i2c),
	.remove = designware_i2c_remove,
	.flags	= DM_FLAG_OS_PREPARE,
	.ops	= &designware_i2c_ops,
};

#endif /* CONFIG_DM_I2C */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
2403f8f4 VK	2	/*
	3	* (C) Copyright 2009
	4	* Vipin Kumar, ST Micoelectronics, [email protected].
2403f8f4 VK	5	*/
	6
	7	#include <common.h>
afb88651	8	#include <clk.h>
334b9b00	9	#include <dm.h>
678398b1	10	#include <i2c.h>
ba5da550	11	#include <pci.h>
622597de	12	#include <reset.h>
2403f8f4	13	#include <asm/io.h>
031ed2fa	14	#include "designware_i2c.h"
2403f8f4	15
b6a77b0c	16	#ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
2b5d029d	17	static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
b6a77b0c SR	18	{
	19	u32 ena = enable ? IC_ENABLE_0B : 0;
	20
	21	writel(ena, &i2c_base->ic_enable);
2b5d029d SG	22
2b5d029d SG	23	return 0;
b6a77b0c SR	24	}
b6a77b0c SR	25	#else
2b5d029d	26	static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
1c8b089b SR	27	{
	28	u32 ena = enable ? IC_ENABLE_0B : 0;
	29	int timeout = 100;
	30
	31	do {
	32	writel(ena, &i2c_base->ic_enable);
	33	if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
2b5d029d	34	return 0;
1c8b089b SR	35
	36	/*
	37	* Wait 10 times the signaling period of the highest I2C
	38	* transfer supported by the driver (for 400KHz this is
	39	* 25us) as described in the DesignWare I2C databook.
	40	*/
	41	udelay(25);
	42	} while (timeout--);
1c8b089b	43	printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
2b5d029d SG	44
2b5d029d SG	45	return -ETIMEDOUT;
1c8b089b	46	}
b6a77b0c	47	#endif
1c8b089b	48
2403f8f4	49	/*
11b544ab SR	50	* i2c_set_bus_speed - Set the i2c speed
11b544ab SR	51	* @speed: required i2c speed
2403f8f4	52	*
11b544ab	53	* Set the i2c speed.
2403f8f4	54	*/
3f4358da	55	static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
ba5da550	56	struct dw_scl_sda_cfg *scl_sda_cfg,
2d1e879c	57	unsigned int speed,
dd3c1602	58	unsigned int bus_clk)
2403f8f4	59	{
dd3c1602	60	ulong bus_khz = bus_clk / 1000;
65190d15	61	enum i2c_speed_mode i2c_spd;
2403f8f4 VK	62	unsigned int cntl;
2403f8f4 VK	63	unsigned int hcnt, lcnt;
e3b93dce	64	unsigned int ena;
11b544ab	65
6db7943b SG	66	/* Allow high speed if there is no config, or the config allows it */
	67	if (speed >= I2C_HIGH_SPEED &&
	68	(!scl_sda_cfg \|\| scl_sda_cfg->has_high_speed))
	69	i2c_spd = IC_SPEED_MODE_HIGH;
11b544ab SR	70	else if (speed >= I2C_FAST_SPEED)
	71	i2c_spd = IC_SPEED_MODE_FAST;
	72	else
	73	i2c_spd = IC_SPEED_MODE_STANDARD;
5e3e8dda	74
e3b93dce JC	75	/* Get enable setting for restore later */
	76	ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
	77
5e3e8dda	78	/* to set speed cltr must be disabled */
1c8b089b	79	dw_i2c_enable(i2c_base, false);
5e3e8dda	80
678398b1	81	cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
2403f8f4 VK	82
2403f8f4 VK	83	switch (i2c_spd) {
6db7943b	84	case IC_SPEED_MODE_HIGH:
ba5da550 SR	85	cntl \|= IC_CON_SPD_SS;
	86	if (scl_sda_cfg) {
	87	hcnt = scl_sda_cfg->fs_hcnt;
	88	lcnt = scl_sda_cfg->fs_lcnt;
	89	} else {
dd3c1602 SG	90	hcnt = (bus_khz * MIN_HS_SCL_HIGHTIME) / NANO_TO_KILO;
dd3c1602 SG	91	lcnt = (bus_khz * MIN_HS_SCL_LOWTIME) / NANO_TO_KILO;
ba5da550	92	}
678398b1	93	writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
678398b1	94	writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
2403f8f4 VK	95	break;
	96
	97	case IC_SPEED_MODE_STANDARD:
	98	cntl \|= IC_CON_SPD_SS;
ba5da550 SR	99	if (scl_sda_cfg) {
	100	hcnt = scl_sda_cfg->ss_hcnt;
	101	lcnt = scl_sda_cfg->ss_lcnt;
	102	} else {
dd3c1602 SG	103	hcnt = (bus_khz * MIN_SS_SCL_HIGHTIME) / NANO_TO_KILO;
dd3c1602 SG	104	lcnt = (bus_khz * MIN_SS_SCL_LOWTIME) / NANO_TO_KILO;
ba5da550	105	}
678398b1	106	writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
678398b1	107	writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
2403f8f4 VK	108	break;
	109
	110	case IC_SPEED_MODE_FAST:
	111	default:
	112	cntl \|= IC_CON_SPD_FS;
ba5da550 SR	113	if (scl_sda_cfg) {
	114	hcnt = scl_sda_cfg->fs_hcnt;
	115	lcnt = scl_sda_cfg->fs_lcnt;
	116	} else {
dd3c1602 SG	117	hcnt = (bus_khz * MIN_FS_SCL_HIGHTIME) / NANO_TO_KILO;
dd3c1602 SG	118	lcnt = (bus_khz * MIN_FS_SCL_LOWTIME) / NANO_TO_KILO;
ba5da550	119	}
678398b1	120	writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
678398b1	121	writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
2403f8f4 VK	122	break;
	123	}
	124
678398b1	125	writel(cntl, &i2c_base->ic_con);
2403f8f4	126
ba5da550 SR	127	/* Configure SDA Hold Time if required */
	128	if (scl_sda_cfg)
	129	writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
	130
e3b93dce JC	131	/* Restore back i2c now speed set */
	132	if (ena == IC_ENABLE_0B)
	133	dw_i2c_enable(i2c_base, true);
496ba48f	134
2403f8f4 VK	135	return 0;
	136	}
	137
2403f8f4 VK	138	/*
	139	* i2c_setaddress - Sets the target slave address
	140	* @i2c_addr: target i2c address
	141	*
	142	* Sets the target slave address.
	143	*/
3f4358da	144	static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
2403f8f4	145	{
8b7c8725	146	/* Disable i2c */
1c8b089b	147	dw_i2c_enable(i2c_base, false);
8b7c8725	148
678398b1	149	writel(i2c_addr, &i2c_base->ic_tar);
8b7c8725 AB	150
8b7c8725 AB	151	/* Enable i2c */
1c8b089b	152	dw_i2c_enable(i2c_base, true);
2403f8f4 VK	153	}
	154
	155	/*
	156	* i2c_flush_rxfifo - Flushes the i2c RX FIFO
	157	*
	158	* Flushes the i2c RX FIFO
	159	*/
3f4358da	160	static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
2403f8f4	161	{
678398b1 SR	162	while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
678398b1 SR	163	readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	164	}
	165
	166	/*
	167	* i2c_wait_for_bb - Waits for bus busy
	168	*
	169	* Waits for bus busy
	170	*/
3f4358da	171	static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
2403f8f4 VK	172	{
	173	unsigned long start_time_bb = get_timer(0);
	174
678398b1 SR	175	while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) \|\|
678398b1 SR	176	!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
2403f8f4 VK	177
	178	/* Evaluate timeout */
	179	if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
	180	return 1;
	181	}
	182
	183	return 0;
	184	}
	185
3f4358da	186	static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
678398b1	187	int alen)
2403f8f4	188	{
3f4358da	189	if (i2c_wait_for_bb(i2c_base))
2403f8f4	190	return 1;
2403f8f4	191
3f4358da	192	i2c_setaddress(i2c_base, chip);
070cbaf8 CLS	193	while (alen) {
	194	alen--;
	195	/* high byte address going out first */
	196	writel((addr >> (alen * 8)) & 0xff,
678398b1	197	&i2c_base->ic_cmd_data);
070cbaf8	198	}
2403f8f4 VK	199	return 0;
	200	}
	201
3f4358da	202	static int i2c_xfer_finish(struct i2c_regs *i2c_base)
2403f8f4 VK	203	{
	204	ulong start_stop_det = get_timer(0);
	205
	206	while (1) {
678398b1 SR	207	if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
678398b1 SR	208	readl(&i2c_base->ic_clr_stop_det);
2403f8f4 VK	209	break;
	210	} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
	211	break;
	212	}
	213	}
	214
3f4358da	215	if (i2c_wait_for_bb(i2c_base)) {
2403f8f4 VK	216	printf("Timed out waiting for bus\n");
	217	return 1;
	218	}
	219
3f4358da	220	i2c_flush_rxfifo(i2c_base);
2403f8f4	221
2403f8f4 VK	222	return 0;
	223	}
	224
	225	/*
	226	* i2c_read - Read from i2c memory
	227	* @chip: target i2c address
	228	* @addr: address to read from
	229	* @alen:
	230	* @buffer: buffer for read data
	231	* @len: no of bytes to be read
	232	*
	233	* Read from i2c memory.
	234	*/
3f4358da SR	235	static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	236	int alen, u8 *buffer, int len)
2403f8f4 VK	237	{
2403f8f4 VK	238	unsigned long start_time_rx;
b0338080	239	unsigned int active = 0;
2403f8f4	240
32d041e2 AB	241	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	242	/*
	243	* EEPROM chips that implement "address overflow" are ones
	244	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	245	* address and the extra bits end up in the "chip address"
	246	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	247	* four 256 byte chips.
	248	*
	249	* Note that we consider the length of the address field to
	250	* still be one byte because the extra address bits are
	251	* hidden in the chip address.
	252	*/
678398b1	253	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	254	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	255
678398b1	256	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	257	addr);
	258	#endif
	259
3f4358da	260	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	261	return 1;
	262
	263	start_time_rx = get_timer(0);
	264	while (len) {
b0338080 MV	265	if (!active) {
	266	/*
	267	* Avoid writing to ic_cmd_data multiple times
	268	* in case this loop spins too quickly and the
	269	* ic_status RFNE bit isn't set after the first
	270	* write. Subsequent writes to ic_cmd_data can
	271	* trigger spurious i2c transfer.
	272	*/
	273	if (len == 1)
	274	writel(IC_CMD \| IC_STOP, &i2c_base->ic_cmd_data);
	275	else
	276	writel(IC_CMD, &i2c_base->ic_cmd_data);
	277	active = 1;
	278	}
2403f8f4	279
678398b1 SR	280	if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
678398b1 SR	281	*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
2403f8f4 VK	282	len--;
2403f8f4 VK	283	start_time_rx = get_timer(0);
b0338080	284	active = 0;
2403f8f4	285	} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
b0338080	286	return 1;
2403f8f4 VK	287	}
	288	}
	289
3f4358da	290	return i2c_xfer_finish(i2c_base);
2403f8f4 VK	291	}
	292
	293	/*
	294	* i2c_write - Write to i2c memory
	295	* @chip: target i2c address
	296	* @addr: address to read from
	297	* @alen:
	298	* @buffer: buffer for read data
	299	* @len: no of bytes to be read
	300	*
	301	* Write to i2c memory.
	302	*/
3f4358da SR	303	static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
3f4358da SR	304	int alen, u8 *buffer, int len)
2403f8f4 VK	305	{
	306	int nb = len;
	307	unsigned long start_time_tx;
	308
32d041e2 AB	309	#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
	310	/*
	311	* EEPROM chips that implement "address overflow" are ones
	312	* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
	313	* address and the extra bits end up in the "chip address"
	314	* bit slots. This makes a 24WC08 (1Kbyte) chip look like
	315	* four 256 byte chips.
	316	*
	317	* Note that we consider the length of the address field to
	318	* still be one byte because the extra address bits are
	319	* hidden in the chip address.
	320	*/
678398b1	321	dev \|= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
32d041e2 AB	322	addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
32d041e2 AB	323
678398b1	324	debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
32d041e2 AB	325	addr);
	326	#endif
	327
3f4358da	328	if (i2c_xfer_init(i2c_base, dev, addr, alen))
2403f8f4 VK	329	return 1;
	330
	331	start_time_tx = get_timer(0);
	332	while (len) {
678398b1 SR	333	if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
	334	if (--len == 0) {
	335	writel(*buffer \| IC_STOP,
	336	&i2c_base->ic_cmd_data);
	337	} else {
	338	writel(*buffer, &i2c_base->ic_cmd_data);
	339	}
2403f8f4	340	buffer++;
2403f8f4 VK	341	start_time_tx = get_timer(0);
	342
	343	} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
	344	printf("Timed out. i2c write Failed\n");
	345	return 1;
	346	}
	347	}
	348
3f4358da SR	349	return i2c_xfer_finish(i2c_base);
	350	}
	351
334b9b00 SR	352	/*
	353	* __dw_i2c_init - Init function
	354	* @speed: required i2c speed
	355	* @slaveaddr: slave address for the device
	356	*
	357	* Initialization function.
	358	*/
2b5d029d	359	static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
334b9b00	360	{
2b5d029d SG	361	int ret;
2b5d029d SG	362
334b9b00	363	/* Disable i2c */
2b5d029d SG	364	ret = dw_i2c_enable(i2c_base, false);
	365	if (ret)
	366	return ret;
334b9b00	367
014e47f0 MV	368	writel(IC_CON_SD \| IC_CON_RE \| IC_CON_SPD_FS \| IC_CON_MM,
014e47f0 MV	369	&i2c_base->ic_con);
334b9b00 SR	370	writel(IC_RX_TL, &i2c_base->ic_rx_tl);
	371	writel(IC_TX_TL, &i2c_base->ic_tx_tl);
	372	writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
	373	#ifndef CONFIG_DM_I2C
2d1e879c	374	__dw_i2c_set_bus_speed(i2c_base, NULL, speed, IC_CLK);
334b9b00 SR	375	writel(slaveaddr, &i2c_base->ic_sar);
	376	#endif
	377
	378	/* Enable i2c */
2b5d029d SG	379	ret = dw_i2c_enable(i2c_base, true);
	380	if (ret)
	381	return ret;
	382
	383	return 0;
334b9b00 SR	384	}
	385
	386	#ifndef CONFIG_DM_I2C
	387	/*
	388	* The legacy I2C functions. These need to get removed once
	389	* all users of this driver are converted to DM.
	390	*/
3f4358da SR	391	static struct i2c_regs i2c_get_base(struct i2c_adapter adap)
	392	{
	393	switch (adap->hwadapnr) {
	394	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	395	case 3:
	396	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
	397	#endif
	398	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	399	case 2:
	400	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
	401	#endif
	402	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	403	case 1:
	404	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
	405	#endif
	406	case 0:
	407	return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
	408	default:
	409	printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
	410	}
	411
	412	return NULL;
	413	}
	414
	415	static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
	416	unsigned int speed)
	417	{
	418	adap->speed = speed;
2d1e879c	419	return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed, IC_CLK);
3f4358da SR	420	}
3f4358da SR	421
334b9b00	422	static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
3f4358da	423	{
334b9b00	424	__dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
3f4358da SR	425	}
	426
	427	static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
	428	int alen, u8 *buffer, int len)
	429	{
	430	return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
	431	}
	432
	433	static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
	434	int alen, u8 *buffer, int len)
	435	{
	436	return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
2403f8f4 VK	437	}
2403f8f4 VK	438
334b9b00	439	/* dw_i2c_probe - Probe the i2c chip */
678398b1	440	static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
2403f8f4	441	{
3f4358da	442	struct i2c_regs *i2c_base = i2c_get_base(adap);
2403f8f4	443	u32 tmp;
496ba48f	444	int ret;
2403f8f4 VK	445
	446	/*
	447	* Try to read the first location of the chip.
	448	*/
3f4358da	449	ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
496ba48f	450	if (ret)
678398b1	451	dw_i2c_init(adap, adap->speed, adap->slaveaddr);
496ba48f SR	452
496ba48f SR	453	return ret;
2403f8f4	454	}
ac6e2fe6	455
678398b1 SR	456	U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	457	dw_i2c_write, dw_i2c_set_bus_speed,
	458	CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
ac6e2fe6	459
678398b1 SR	460	#if CONFIG_SYS_I2C_BUS_MAX >= 2
	461	U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	462	dw_i2c_write, dw_i2c_set_bus_speed,
	463	CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
	464	#endif
ac6e2fe6	465
678398b1 SR	466	#if CONFIG_SYS_I2C_BUS_MAX >= 3
	467	U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	468	dw_i2c_write, dw_i2c_set_bus_speed,
	469	CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
	470	#endif
ac6e2fe6	471
678398b1 SR	472	#if CONFIG_SYS_I2C_BUS_MAX >= 4
	473	U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
	474	dw_i2c_write, dw_i2c_set_bus_speed,
	475	CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
ac6e2fe6	476	#endif
334b9b00 SR	477
	478	#else /* CONFIG_DM_I2C */
	479	/* The DM I2C functions */
	480
	481	static int designware_i2c_xfer(struct udevice bus, struct i2c_msg msg,
	482	int nmsgs)
	483	{
	484	struct dw_i2c *i2c = dev_get_priv(bus);
	485	int ret;
	486
	487	debug("i2c_xfer: %d messages\n", nmsgs);
	488	for (; nmsgs > 0; nmsgs--, msg++) {
	489	debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
	490	if (msg->flags & I2C_M_RD) {
	491	ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
	492	msg->buf, msg->len);
	493	} else {
	494	ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
	495	msg->buf, msg->len);
	496	}
	497	if (ret) {
	498	debug("i2c_write: error sending\n");
	499	return -EREMOTEIO;
	500	}
	501	}
	502
	503	return 0;
	504	}
	505
	506	static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
	507	{
	508	struct dw_i2c *i2c = dev_get_priv(bus);
2d1e879c LFT	509	ulong rate;
	510
	511	#if CONFIG_IS_ENABLED(CLK)
	512	rate = clk_get_rate(&i2c->clk);
	513	if (IS_ERR_VALUE(rate))
	514	return -EINVAL;
2d1e879c LFT	515	#else
	516	rate = IC_CLK;
	517	#endif
	518	return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed,
	519	rate);
334b9b00 SR	520	}
	521
	522	static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
	523	uint chip_flags)
	524	{
	525	struct dw_i2c *i2c = dev_get_priv(bus);
	526	struct i2c_regs *i2c_base = i2c->regs;
	527	u32 tmp;
	528	int ret;
	529
	530	/* Try to read the first location of the chip */
	531	ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
	532	if (ret)
	533	__dw_i2c_init(i2c_base, 0, 0);
	534
	535	return ret;
	536	}
	537
80a03db4	538	int designware_i2c_ofdata_to_platdata(struct udevice *bus)
334b9b00 SR	539	{
	540	struct dw_i2c *priv = dev_get_priv(bus);
	541
80a03db4 SG	542	if (!priv->regs)
	543	priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
	544	dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
	545	dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
	546	dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
457df233 SG	547
	548	return 0;
	549	}
	550
	551	int designware_i2c_probe(struct udevice *bus)
	552	{
	553	struct dw_i2c *priv = dev_get_priv(bus);
	554	int ret;
334b9b00	555
36821b3f	556	ret = reset_get_bulk(bus, &priv->resets);
622597de	557	if (ret)
36821b3f SG	558	dev_warn(bus, "Can't get reset: %d\n", ret);
	559	else
	560	reset_deassert_bulk(&priv->resets);
622597de	561
2d1e879c LFT	562	#if CONFIG_IS_ENABLED(CLK)
	563	ret = clk_get_by_index(bus, 0, &priv->clk);
	564	if (ret)
	565	return ret;
	566
	567	ret = clk_enable(&priv->clk);
	568	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
	569	clk_free(&priv->clk);
	570	dev_err(bus, "failed to enable clock\n");
	571	return ret;
	572	}
	573	#endif
	574
2b5d029d	575	return __dw_i2c_init(priv->regs, 0, 0);
334b9b00 SR	576	}
334b9b00 SR	577
457df233	578	int designware_i2c_remove(struct udevice *dev)
36821b3f SG	579	{
	580	struct dw_i2c *priv = dev_get_priv(dev);
	581
2d1e879c LFT	582	#if CONFIG_IS_ENABLED(CLK)
	583	clk_disable(&priv->clk);
	584	clk_free(&priv->clk);
	585	#endif
	586
36821b3f SG	587	return reset_release_bulk(&priv->resets);
	588	}
	589
457df233	590	const struct dm_i2c_ops designware_i2c_ops = {
334b9b00 SR	591	.xfer = designware_i2c_xfer,
	592	.probe_chip = designware_i2c_probe_chip,
	593	.set_bus_speed = designware_i2c_set_bus_speed,
	594	};
	595
	596	static const struct udevice_id designware_i2c_ids[] = {
	597	{ .compatible = "snps,designware-i2c" },
	598	{ }
	599	};
	600
	601	U_BOOT_DRIVER(i2c_designware) = {
	602	.name = "i2c_designware",
	603	.id = UCLASS_I2C,
	604	.of_match = designware_i2c_ids,
457df233	605	.ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
334b9b00 SR	606	.probe = designware_i2c_probe,
334b9b00 SR	607	.priv_auto_alloc_size = sizeof(struct dw_i2c),
36821b3f	608	.remove = designware_i2c_remove,
457df233	609	.flags = DM_FLAG_OS_PREPARE,
334b9b00 SR	610	.ops = &designware_i2c_ops,
	611	};
	612
	613	#endif /* CONFIG_DM_I2C */