[J-u-boot.git] / include / configs / T208xQDS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011-2013 Freescale Semiconductor, Inc.
 * Copyright 2020-2021 NXP
 */

/*
 * T2080/T2081 QDS board configuration file
 */

#ifndef __T208xQDS_H
#define __T208xQDS_H

#include <linux/stringify.h>

#define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_SRIO		/* Enable Serial RapidIO Support */
#define CONFIG_SRIO1		/* SRIO port 1 */
#define CONFIG_SRIO2		/* SRIO port 2 */
#endif

/* High Level Configuration Options */

#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS

#ifdef CONFIG_RAMBOOT_PBL
#define RESET_VECTOR_OFFSET		0x27FFC
#define BOOT_PAGE_OFFSET		0x27000

#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
#endif

#ifdef CONFIG_SPIFLASH
#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST		(0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START	(0x00200000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS	(256 << 10)
#endif

#ifdef CONFIG_SDCARD
#define	CONFIG_RESET_VECTOR_ADDRESS		0x200FFC
#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST	(0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_START	(0x00200000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
#endif

#endif /* CONFIG_RAMBOOT_PBL */

#define CONFIG_SRIO_PCIE_BOOT_MASTER
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#ifdef CONFIG_DDR_ECC
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

/*
 * Config the L3 Cache as L3 SRAM
 */
#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)

#define CONFIG_SYS_DCSRBAR	0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull

/*
 * DDR Setup
 */
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
#define SPD_EEPROM_ADDRESS1	0x51
#define SPD_EEPROM_ADDRESS2	0x52
#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
#define CTRL_INTLV_PREFERED	cacheline

/*
 * IFC Definitions
 */
#define CONFIG_SYS_FLASH_BASE		0xe0000000
#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
				+ 0x8000000) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
				CSPR_PORT_SIZE_16 | \
				CSPR_MSEL_NOR | \
				CSPR_V)
#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR	CSOR_NAND_TRHZ_80

#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
				FTIM0_NOR_TEADC(0x5) | \
				FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
				FTIM1_NOR_TRAD_NOR(0x1A) |\
				FTIM1_NOR_TSEQRAD_NOR(0x13))
#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
				FTIM2_NOR_TCH(0x4) | \
				FTIM2_NOR_TWPH(0x0E) | \
				FTIM2_NOR_TWP(0x1c))
#define CONFIG_SYS_NOR_FTIM3	0x0

#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}

#define QIXIS_BASE			0xffdf0000
#define QIXIS_LBMAP_SWITCH		6
#define QIXIS_LBMAP_MASK		0x0f
#define QIXIS_LBMAP_SHIFT		0
#define QIXIS_LBMAP_DFLTBANK		0x00
#define QIXIS_LBMAP_ALTBANK		0x04
#define QIXIS_LBMAP_NAND		0x09
#define QIXIS_LBMAP_SD			0x00
#define QIXIS_RCW_SRC_NAND		0x104
#define QIXIS_RCW_SRC_SD		0x040
#define QIXIS_RST_CTL_RESET		0x83
#define QIXIS_RST_FORCE_MEM		0x1
#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)

#define CONFIG_SYS_CSPR3_EXT	(0xf)
#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 \
				| CSPR_MSEL_GPCM \
				| CSPR_V)
#define CONFIG_SYS_AMASK3	IFC_AMASK(64 * 1024)
#define CONFIG_SYS_CSOR3	0x0
/* QIXIS Timing parameters for IFC CS3 */
#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
					FTIM0_GPCM_TEADC(0x0e) | \
					FTIM0_GPCM_TEAHC(0x0e))
#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0xff) | \
					FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
					FTIM2_GPCM_TCH(0x8) | \
					FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3		0x0

/* NAND Flash on IFC */
#define CONFIG_SYS_NAND_BASE		0xff800000
#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)

#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
				| CSPR_MSEL_NAND	 /* MSEL = NAND */ \
				| CSPR_V)
#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)

#define CONFIG_SYS_NAND_CSOR	(CSOR_NAND_ECC_ENC_EN	/* ECC on encode */ \
				| CSOR_NAND_ECC_DEC_EN	/* ECC on decode */ \
				| CSOR_NAND_ECC_MODE_4	/* 4-bit ECC */	    \
				| CSOR_NAND_RAL_3	/* RAL = 2Byes */   \
				| CSOR_NAND_PGS_2K	/* Page Size = 2K */\
				| CSOR_NAND_SPRZ_64	/* Spare size = 64 */\
				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/

/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
					FTIM0_NAND_TWP(0x18)    | \
					FTIM0_NAND_TWCHT(0x07)  | \
					FTIM0_NAND_TWH(0x0a))
#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
					FTIM1_NAND_TWBE(0x39)   | \
					FTIM1_NAND_TRR(0x0e)    | \
					FTIM1_NAND_TRP(0x18))
#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f)  | \
					FTIM2_NAND_TREH(0x0a)   | \
					FTIM2_NAND_TWHRE(0x1e))
#define CONFIG_SYS_NAND_FTIM3		0x0

#define CONFIG_SYS_NAND_DDR_LAW		11
#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
#else
#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
#endif

#define CONFIG_HWCONFIG

/* define to use L1 as initial stack */
#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
/* The assembler doesn't like typecast */
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
			((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
			CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)

/*
 * Serial Port
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)

/*
 * I2C
 */

#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
#define I2C_MUX_CH_DEFAULT	0x8

#define I2C_MUX_CH_VOL_MONITOR 0xa

/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR           0x40
#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT    3

/* The lowest and highest voltage allowed for T208xQDS */
#define VDD_MV_MIN			819
#define VDD_MV_MAX			1212

/*
 * RapidIO
 */
#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000 /* 256M */
/*
 * for slave u-boot IMAGE instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
 * for slave UCODE and ENV instored in master memory space,
 * PHYS must be aligned based on the SIZE
 */
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000	/* 256K */

/* slave core release by master*/
#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */

/*
 * SRIO_PCIE_BOOT - SLAVE
 */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif

/*
 * eSPI - Enhanced SPI
 */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull

/* controller 2, Slot 2, tgtid 2, Base address 201000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull

/* controller 3, Slot 1, tgtid 1, Base address 202000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull

/* controller 4, Base address 203000 */
#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull

/* Qman/Bman */
#ifndef CONFIG_NOBQFMAN
#define CONFIG_SYS_BMAN_NUM_PORTALS	18
#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
					CONFIG_SYS_BMAN_CENA_SIZE)
#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
#define CONFIG_SYS_QMAN_NUM_PORTALS	18
#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
					CONFIG_SYS_QMAN_CENA_SIZE)
#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08

#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
#define CONFIG_SYS_PMAN
#define CONFIG_SYS_DPAA_DCE
#define CONFIG_SYS_DPAA_RMAN		/* RMan */
#endif /* CONFIG_NOBQFMAN */

#ifdef CONFIG_SYS_DPAA_FMAN
#define RGMII_PHY1_ADDR	0x1
#define RGMII_PHY2_ADDR	0x2
#define FM1_10GEC1_PHY_ADDR	  0x3
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
#endif

/*
 * USB
 */

/*
 * SDHC
 */
#ifdef CONFIG_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

/*
 * Dynamic MTD Partition support with mtdparts
 */

/*
 * Miscellaneous configurable options
 */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/

/*
 * Environment Configuration
 */
#define CONFIG_ROOTPATH	 "/opt/nfsroot"
#define CONFIG_UBOOTPATH "u-boot.bin"	/* U-Boot image on TFTP server */

#define __USB_PHY_TYPE		utmi

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hwconfig=fsl_ddr:"					\
	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","	\
	"bank_intlv=auto;"					\
	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
	"protect off $ubootaddr +$filesize && "			\
	"erase $ubootaddr +$filesize && "			\
	"cp.b $loadaddr $ubootaddr $filesize && "		\
	"protect on $ubootaddr +$filesize && "			\
	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
	"consoledev=ttyS0\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=t2080qds/ramdisk.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=t2080qds/t2080qds.dtb\0"			\
	"bdev=sda3\0"

/*
 * For emulation this causes u-boot to jump to the start of the
 * proof point app code automatically
 */
#define PROOF_POINTS				\
	"setenv bootargs root=/dev/$bdev rw "		\
	"console=$consoledev,$baudrate $othbootargs;"	\
	"cpu 1 release 0x29000000 - - -;"		\
	"cpu 2 release 0x29000000 - - -;"		\
	"cpu 3 release 0x29000000 - - -;"		\
	"cpu 4 release 0x29000000 - - -;"		\
	"cpu 5 release 0x29000000 - - -;"		\
	"cpu 6 release 0x29000000 - - -;"		\
	"cpu 7 release 0x29000000 - - -;"		\
	"go 0x29000000"

#define HVBOOT				\
	"setenv bootargs config-addr=0x60000000; "	\
	"bootm 0x01000000 - 0x00f00000"

#define ALU				\
	"setenv bootargs root=/dev/$bdev rw "		\
	"console=$consoledev,$baudrate $othbootargs;"	\
	"cpu 1 release 0x01000000 - - -;"		\
	"cpu 2 release 0x01000000 - - -;"		\
	"cpu 3 release 0x01000000 - - -;"		\
	"cpu 4 release 0x01000000 - - -;"		\
	"cpu 5 release 0x01000000 - - -;"		\
	"cpu 6 release 0x01000000 - - -;"		\
	"cpu 7 release 0x01000000 - - -;"		\
	"go 0x01000000"

#include <asm/fsl_secure_boot.h>

#endif	/* __T208xQDS_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
c4d0e811 SL	2	/*
c4d0e811 SL	3	* Copyright 2011-2013 Freescale Semiconductor, Inc.
34f39ce8	4	* Copyright 2020-2021 NXP
c4d0e811 SL	5	*/
	6
	7	/*
254887a5	8	* T2080/T2081 QDS board configuration file
c4d0e811 SL	9	*/
c4d0e811 SL	10
254887a5 SL	11	#ifndef __T208xQDS_H
254887a5 SL	12	#define __T208xQDS_H
c4d0e811	13
1af3c7f4 SG	14	#include <linux/stringify.h>
1af3c7f4 SG	15
c4d0e811	16	#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
0f3d80e9	17	#if defined(CONFIG_ARCH_T2080)
c4d0e811 SL	18	#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
	19	#define CONFIG_SRIO1 /* SRIO port 1 */
	20	#define CONFIG_SRIO2 /* SRIO port 2 */
254887a5	21	#endif
c4d0e811 SL	22
c4d0e811 SL	23	/* High Level Configuration Options */
c4d0e811	24
51370d56	25	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
c4d0e811 SL	26
c4d0e811 SL	27	#ifdef CONFIG_RAMBOOT_PBL
b19e288f SL	28	#define RESET_VECTOR_OFFSET 0x27FFC
b19e288f SL	29	#define BOOT_PAGE_OFFSET 0x27000
b19e288f	30
88718be3	31	#ifdef CONFIG_MTD_RAW_NAND
b19e288f SL	32	#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	33	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
	34	#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
b19e288f SL	35	#endif
	36
	37	#ifdef CONFIG_SPIFLASH
	38	#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
b19e288f SL	39	#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
	40	#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
	41	#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
	42	#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
b19e288f SL	43	#endif
	44
	45	#ifdef CONFIG_SDCARD
	46	#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
b19e288f SL	47	#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	48	#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
	49	#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
	50	#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
b19e288f SL	51	#endif
	52
	53	#endif /* CONFIG_RAMBOOT_PBL */
c4d0e811 SL	54
	55	#define CONFIG_SRIO_PCIE_BOOT_MASTER
	56	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
	57	/* Set 1M boot space */
98463903	58	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
c4d0e811 SL	59	#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
	60	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
	61	#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
c4d0e811 SL	62	#endif
c4d0e811 SL	63
c4d0e811 SL	64	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	65	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	66	#endif
	67
	68	/*
	69	* These can be toggled for performance analysis, otherwise use default.
	70	*/
c4d0e811	71	#ifdef CONFIG_DDR_ECC
c4d0e811 SL	72	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	73	#endif
	74
c4d0e811 SL	75	/*
	76	* Config the L3 Cache as L3 SRAM
	77	*/
b19e288f	78	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
a09fea1d	79	#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
c4d0e811 SL	80
	81	#define CONFIG_SYS_DCSRBAR 0xf0000000
	82	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
	83
c4d0e811 SL	84	/*
	85	* DDR Setup
	86	*/
	87	#define CONFIG_VERY_BIG_RAM
	88	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	89	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
c4d0e811 SL	90	#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
	91	#define SPD_EEPROM_ADDRESS1 0x51
	92	#define SPD_EEPROM_ADDRESS2 0x52
	93	#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
	94	#define CTRL_INTLV_PREFERED cacheline
	95
	96	/*
	97	* IFC Definitions
	98	*/
	99	#define CONFIG_SYS_FLASH_BASE 0xe0000000
	100	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)
	101	#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
	102	#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
	103	+ 0x8000000) \| \
	104	CSPR_PORT_SIZE_16 \| \
	105	CSPR_MSEL_NOR \| \
	106	CSPR_V)
	107	#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
	108	#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| \
	109	CSPR_PORT_SIZE_16 \| \
	110	CSPR_MSEL_NOR \| \
	111	CSPR_V)
	112	#define CONFIG_SYS_NOR_AMASK IFC_AMASK(12810241024)
	113	/* NOR Flash Timing Params */
	114	#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
	115
	116	#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) \| \
	117	FTIM0_NOR_TEADC(0x5) \| \
	118	FTIM0_NOR_TEAHC(0x5))
	119	#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) \| \
	120	FTIM1_NOR_TRAD_NOR(0x1A) \|\
	121	FTIM1_NOR_TSEQRAD_NOR(0x13))
	122	#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) \| \
	123	FTIM2_NOR_TCH(0x4) \| \
	124	FTIM2_NOR_TWPH(0x0E) \| \
	125	FTIM2_NOR_TWP(0x1c))
	126	#define CONFIG_SYS_NOR_FTIM3 0x0
	127
c4d0e811 SL	128	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
c4d0e811 SL	129
c4d0e811 SL	130	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
	131	+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
	132
c4d0e811 SL	133	#define QIXIS_BASE 0xffdf0000
	134	#define QIXIS_LBMAP_SWITCH 6
	135	#define QIXIS_LBMAP_MASK 0x0f
	136	#define QIXIS_LBMAP_SHIFT 0
	137	#define QIXIS_LBMAP_DFLTBANK 0x00
	138	#define QIXIS_LBMAP_ALTBANK 0x04
46caebc1 YS	139	#define QIXIS_LBMAP_NAND 0x09
	140	#define QIXIS_LBMAP_SD 0x00
	141	#define QIXIS_RCW_SRC_NAND 0x104
	142	#define QIXIS_RCW_SRC_SD 0x040
c4d0e811 SL	143	#define QIXIS_RST_CTL_RESET 0x83
	144	#define QIXIS_RST_FORCE_MEM 0x1
	145	#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
	146	#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
	147	#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
	148	#define QIXIS_BASE_PHYS (0xf00000000ull \| QIXIS_BASE)
	149
	150	#define CONFIG_SYS_CSPR3_EXT (0xf)
	151	#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
	152	\| CSPR_PORT_SIZE_8 \
	153	\| CSPR_MSEL_GPCM \
	154	\| CSPR_V)
088d52cf	155	#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
c4d0e811 SL	156	#define CONFIG_SYS_CSOR3 0x0
	157	/* QIXIS Timing parameters for IFC CS3 */
	158	#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) \| \
	159	FTIM0_GPCM_TEADC(0x0e) \| \
	160	FTIM0_GPCM_TEAHC(0x0e))
	161	#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) \| \
	162	FTIM1_GPCM_TRAD(0x3f))
	163	#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) \| \
6b7679c8	164	FTIM2_GPCM_TCH(0x8) \| \
c4d0e811 SL	165	FTIM2_GPCM_TWP(0x1f))
	166	#define CONFIG_SYS_CS3_FTIM3 0x0
	167
	168	/* NAND Flash on IFC */
c4d0e811 SL	169	#define CONFIG_SYS_NAND_BASE 0xff800000
	170	#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_NAND_BASE)
	171
	172	#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
	173	#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
	174	\| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
	175	\| CSPR_MSEL_NAND /* MSEL = NAND */ \
	176	\| CSPR_V)
	177	#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
	178
	179	#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
	180	\| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
	181	\| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
	182	\| CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
	183	\| CSOR_NAND_PGS_2K /* Page Size = 2K */\
	184	\| CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
	185	\| CSOR_NAND_PB(64)) /Pages Per Block = 64/
	186
c4d0e811 SL	187	/* ONFI NAND Flash mode0 Timing Params */
	188	#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) \| \
	189	FTIM0_NAND_TWP(0x18) \| \
	190	FTIM0_NAND_TWCHT(0x07) \| \
	191	FTIM0_NAND_TWH(0x0a))
	192	#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) \| \
	193	FTIM1_NAND_TWBE(0x39) \| \
	194	FTIM1_NAND_TRR(0x0e) \| \
	195	FTIM1_NAND_TRP(0x18))
	196	#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) \| \
	197	FTIM2_NAND_TREH(0x0a) \| \
	198	FTIM2_NAND_TWHRE(0x1e))
	199	#define CONFIG_SYS_NAND_FTIM3 0x0
	200
	201	#define CONFIG_SYS_NAND_DDR_LAW 11
	202	#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
	203	#define CONFIG_SYS_MAX_NAND_DEVICE 1
c4d0e811	204
88718be3	205	#if defined(CONFIG_MTD_RAW_NAND)
c4d0e811 SL	206	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
	207	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
	208	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
	209	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
	210	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
	211	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
	212	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
	213	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
22cbf964 SL	214	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
	215	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
	216	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	217	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	218	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	219	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	220	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	221	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
	222	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
	223	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
c4d0e811 SL	224	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
	225	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
	226	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
	227	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
	228	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
	229	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
	230	#else
	231	#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
	232	#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
	233	#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
	234	#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
	235	#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
	236	#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
	237	#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
	238	#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
22cbf964 SL	239	#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
	240	#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
	241	#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
	242	#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
	243	#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
	244	#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
	245	#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
	246	#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
c4d0e811 SL	247	#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
	248	#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
	249	#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
	250	#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
	251	#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
	252	#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
	253	#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
	254	#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
	255	#endif
c4d0e811	256
c4d0e811 SL	257	#define CONFIG_HWCONFIG
	258
	259	/* define to use L1 as initial stack */
	260	#define CONFIG_L1_INIT_RAM
c4d0e811 SL	261	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
c4d0e811 SL	262	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
b3142e2c	263	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
c4d0e811 SL	264	/* The assembler doesn't like typecast */
	265	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	266	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	267	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	268	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
4c97c8cd	269	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
9307cbab	270	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
c4d0e811 SL	271
	272	/*
	273	* Serial Port
	274	*/
c4d0e811 SL	275	#define CONFIG_SYS_NS16550_SERIAL
	276	#define CONFIG_SYS_NS16550_REG_SIZE 1
	277	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
	278	#define CONFIG_SYS_BAUDRATE_TABLE \
	279	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	280	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	281	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	282	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	283	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
	284
c4d0e811 SL	285	/*
	286	* I2C
	287	*/
8e4be6df	288
c4d0e811 SL	289	#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
	290	#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
	291	#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
	292	#define I2C_MUX_CH_DEFAULT 0x8
	293
3ad2737e YZ	294	#define I2C_MUX_CH_VOL_MONITOR 0xa
	295
	296	/* Voltage monitor on channel 2*/
	297	#define I2C_VOL_MONITOR_ADDR 0x40
	298	#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
	299	#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
	300	#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
	301
3ad2737e YZ	302	/* The lowest and highest voltage allowed for T208xQDS */
	303	#define VDD_MV_MIN 819
	304	#define VDD_MV_MAX 1212
c4d0e811 SL	305
	306	/*
	307	* RapidIO
	308	*/
	309	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
	310	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
	311	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
	312	#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
	313	#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
	314	#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
	315	/*
	316	* for slave u-boot IMAGE instored in master memory space,
	317	* PHYS must be aligned based on the SIZE
	318	*/
e4911815 LG	319	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
	320	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
	321	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
	322	#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
c4d0e811 SL	323	/*
	324	* for slave UCODE and ENV instored in master memory space,
	325	* PHYS must be aligned based on the SIZE
	326	*/
e4911815	327	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
c4d0e811 SL	328	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
	329	#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
	330
	331	/* slave core release by master*/
	332	#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
	333	#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
	334
	335	/*
	336	* SRIO_PCIE_BOOT - SLAVE
	337	*/
	338	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
	339	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
	340	#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
	341	(0x300000000ull \| CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
	342	#endif
	343
	344	/*
	345	* eSPI - Enhanced SPI
	346	*/
c4d0e811 SL	347
	348	/*
	349	* General PCI
	350	* Memory space is mapped 1-1, but I/O space must start from 0.
	351	*/
c4d0e811 SL	352	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
c4d0e811 SL	353	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
c4d0e811	354	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
c4d0e811	355	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
c4d0e811	356	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
c4d0e811 SL	357
	358	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	359	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
c4d0e811	360	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
c4d0e811	361	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
c4d0e811	362	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
c4d0e811 SL	363
	364	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	365	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
c4d0e811	366	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
c4d0e811	367	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
c4d0e811	368	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
c4d0e811 SL	369
	370	/* controller 4, Base address 203000 */
	371	#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
c4d0e811	372	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
c4d0e811	373	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
c4d0e811	374
c4d0e811 SL	375	/* Qman/Bman */
c4d0e811 SL	376	#ifndef CONFIG_NOBQFMAN
c4d0e811 SL	377	#define CONFIG_SYS_BMAN_NUM_PORTALS 18
	378	#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
	379	#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
	380	#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
3fa66db4 JL	381	#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
	382	#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
	383	#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
	384	#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	385	#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
	386	CONFIG_SYS_BMAN_CENA_SIZE)
	387	#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
	388	#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
c4d0e811 SL	389	#define CONFIG_SYS_QMAN_NUM_PORTALS 18
	390	#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
	391	#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
	392	#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
3fa66db4 JL	393	#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
	394	#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
	395	#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
	396	#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	397	#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
	398	CONFIG_SYS_QMAN_CENA_SIZE)
	399	#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
	400	#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
c4d0e811 SL	401
	402	#define CONFIG_SYS_DPAA_FMAN
	403	#define CONFIG_SYS_DPAA_PME
	404	#define CONFIG_SYS_PMAN
	405	#define CONFIG_SYS_DPAA_DCE
	406	#define CONFIG_SYS_DPAA_RMAN /* RMan */
c4d0e811 SL	407	#endif /* CONFIG_NOBQFMAN */
	408
	409	#ifdef CONFIG_SYS_DPAA_FMAN
c4d0e811 SL	410	#define RGMII_PHY1_ADDR 0x1
	411	#define RGMII_PHY2_ADDR 0x2
	412	#define FM1_10GEC1_PHY_ADDR 0x3
	413	#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
	414	#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
	415	#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
	416	#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
	417	#endif
	418
c4d0e811 SL	419	/*
	420	* USB
	421	*/
c4d0e811 SL	422
	423	/*
	424	* SDHC
	425	*/
	426	#ifdef CONFIG_MMC
c4d0e811	427	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
c4d0e811 SL	428	#endif
c4d0e811 SL	429
9941cf78 SL	430	/*
	431	* Dynamic MTD Partition support with mtdparts
	432	*/
9941cf78	433
c4d0e811 SL	434	/*
	435	* Miscellaneous configurable options
	436	*/
c4d0e811 SL	437
	438	/*
	439	* For booting Linux, the board info and command line data
	440	* have to be in the first 64 MB of memory, since this is
	441	* the maximum mapped by the Linux kernel during initialization.
	442	*/
	443	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
c4d0e811	444
c4d0e811 SL	445	/*
	446	* Environment Configuration
	447	*/
	448	#define CONFIG_ROOTPATH "/opt/nfsroot"
c4d0e811 SL	449	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
c4d0e811 SL	450
c4d0e811 SL	451	#define __USB_PHY_TYPE utmi
	452
	453	#define CONFIG_EXTRA_ENV_SETTINGS \
	454	"hwconfig=fsl_ddr:" \
	455	"ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
	456	"bank_intlv=auto;" \
	457	"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
	458	"netdev=eth0\0" \
	459	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
98463903	460	"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
c4d0e811 SL	461	"tftpflash=tftpboot $loadaddr $uboot && " \
	462	"protect off $ubootaddr +$filesize && " \
	463	"erase $ubootaddr +$filesize && " \
	464	"cp.b $loadaddr $ubootaddr $filesize && " \
	465	"protect on $ubootaddr +$filesize && " \
	466	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	467	"consoledev=ttyS0\0" \
	468	"ramdiskaddr=2000000\0" \
	469	"ramdiskfile=t2080qds/ramdisk.uboot\0" \
b24a4f62	470	"fdtaddr=1e00000\0" \
c4d0e811	471	"fdtfile=t2080qds/t2080qds.dtb\0" \
3246584d	472	"bdev=sda3\0"
c4d0e811 SL	473
	474	/*
	475	* For emulation this causes u-boot to jump to the start of the
	476	* proof point app code automatically
	477	*/
7ae1b080	478	#define PROOF_POINTS \
c4d0e811 SL	479	"setenv bootargs root=/dev/$bdev rw " \
	480	"console=$consoledev,$baudrate $othbootargs;" \
	481	"cpu 1 release 0x29000000 - - -;" \
	482	"cpu 2 release 0x29000000 - - -;" \
	483	"cpu 3 release 0x29000000 - - -;" \
	484	"cpu 4 release 0x29000000 - - -;" \
	485	"cpu 5 release 0x29000000 - - -;" \
	486	"cpu 6 release 0x29000000 - - -;" \
	487	"cpu 7 release 0x29000000 - - -;" \
	488	"go 0x29000000"
	489
7ae1b080	490	#define HVBOOT \
c4d0e811 SL	491	"setenv bootargs config-addr=0x60000000; " \
	492	"bootm 0x01000000 - 0x00f00000"
	493
7ae1b080	494	#define ALU \
c4d0e811 SL	495	"setenv bootargs root=/dev/$bdev rw " \
	496	"console=$consoledev,$baudrate $othbootargs;" \
	497	"cpu 1 release 0x01000000 - - -;" \
	498	"cpu 2 release 0x01000000 - - -;" \
	499	"cpu 3 release 0x01000000 - - -;" \
	500	"cpu 4 release 0x01000000 - - -;" \
	501	"cpu 5 release 0x01000000 - - -;" \
	502	"cpu 6 release 0x01000000 - - -;" \
	503	"cpu 7 release 0x01000000 - - -;" \
	504	"go 0x01000000"
	505
c4d0e811	506	#include <asm/fsl_secure_boot.h>
ef6c55a2	507
254887a5	508	#endif /* __T208xQDS_H */