[J-u-boot.git] / arch / arm / mach-davinci / Kconfig

if ARCH_DAVINCI

choice
	prompt "DaVinci board select"
	optional

config TARGET_DA850EVM
	bool "DA850 EVM board"
	select MACH_DAVINCI_DA850_EVM
	select SOC_DA850
	select SUPPORT_SPL

config TARGET_OMAPL138_LCDK
	bool "OMAPL138 LCDK"
	select SOC_DA8XX
	select SUPPORT_SPL
	select SPL_BOARD_INIT

config TARGET_LEGOEV3
	bool "LEGO MINDSTORMS EV3"
	select MACH_DAVINCI_DA850_EVM
	select SOC_DA850

endchoice

config SYS_SOC
	default "davinci"

config DA850_LOWLEVEL
	bool "Enable Lowlevel DA850 initialization"
	depends on SOC_DA850

config SYS_DA850_PLL_INIT
	bool

config SYS_DA850_DDR_INIT
	bool

config SOC_DA850
	bool
	select SOC_DA8XX

config SOC_DA8XX
	bool
	select SYS_DA850_DDR_INIT if SUPPORT_SPL || DA850_LOWLEVEL
	select SYS_DA850_PLL_INIT if SUPPORT_SPL || DA850_LOWLEVEL

config MACH_DAVINCI_DA850_EVM
	bool

if SYS_DA850_PLL_INIT
comment "DA850 PLL Initialization Parameters"

config SYS_DV_CLKMODE
	int "PLLCTL Clock Mode"
	default 0
	help
	  Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator

config SYS_DA850_PLL0_POSTDIV
	int "PLLC0 PLL Post-Divider"
	default 1
	help
	  Value written to PLLC0 PLL Post-Divider Control Register

config SYS_DA850_PLL0_PLLDIV1
	hex "PLLC0 Divider 1"
	default 0x8000
	help
	  Value written to PLLC0 Divider 1 register

config SYS_DA850_PLL0_PLLDIV2
	hex "PLLC0 Divider 2"
	default 0x8001
	help
	  Value written to PLLC0 Divider 2 register

config SYS_DA850_PLL0_PLLDIV3
	hex "PLLC0 Divider 3"
	default 0x8002
	help
	  Value written to PLLC0 Divider 3 register

config SYS_DA850_PLL0_PLLDIV4
	hex "PLLC0 Divider 4"
	default 0x8003
	help
	  Value written to PLLC0 Divider 4 register

config SYS_DA850_PLL0_PLLDIV5
	hex "PLLC0 Divider 5"
	default 0x8002
	help
	  Value written to PLLC0 Divider 5 register

config SYS_DA850_PLL0_PLLDIV6
	hex "PLLC0 Divider 6"
	default 0x8000
	help
	  Value written to PLLC0 Divider 6 register

config SYS_DA850_PLL0_PLLDIV7
	hex "PLLC0 Divider 7"
	default 0x8005
	help
	  Value written to PLLC0 Divider 7 register

config SYS_DA850_PLL1_POSTDIV
	hex "PLLC1 PLL Post-Divider"
	default 1
	help
	  Value written to PLLC1 PLL Post-Divider Control Register

config SYS_DA850_PLL1_PLLDIV1
	hex "PLLC1 Divider 2"
	default 0x8000
	help
	  Value written to PLLC1 Divider 1 register

config SYS_DA850_PLL1_PLLDIV2
	hex "PLLC1 Divider 2"
	default 0x8001
	help
	  Value written to PLLC1 Divider 2 register

config SYS_DA850_PLL1_PLLDIV3
	hex "PLLC1 Divider 3"
	default 0x8002
	help
	  Value written to PLLC1 Divider 3 register

endif

source "board/davinci/da8xxevm/Kconfig"
source "board/lego/ev3/Kconfig"

config SPL_LDSCRIPT
	default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds"

endif
Commit	Line	Data
3491ba63 MY	1	if ARCH_DAVINCI
	2
	3	choice
	4	prompt "DaVinci board select"
a26cd049	5	optional
3491ba63	6
3491ba63 MY	7	config TARGET_DA850EVM
3491ba63 MY	8	bool "DA850 EVM board"
6aa4ad8e AF	9	select MACH_DAVINCI_DA850_EVM
6aa4ad8e AF	10	select SOC_DA850
02627356	11	select SUPPORT_SPL
3491ba63	12
6761946f SG	13	config TARGET_OMAPL138_LCDK
6761946f SG	14	bool "OMAPL138 LCDK"
2e879805	15	select SOC_DA8XX
6761946f	16	select SUPPORT_SPL
598d9bcc	17	select SPL_BOARD_INIT
3491ba63	18
2ac07f75 DL	19	config TARGET_LEGOEV3
2ac07f75 DL	20	bool "LEGO MINDSTORMS EV3"
6aa4ad8e AF	21	select MACH_DAVINCI_DA850_EVM
6aa4ad8e AF	22	select SOC_DA850
2ac07f75	23
3491ba63 MY	24	endchoice
3491ba63 MY	25
3491ba63	26	config SYS_SOC
3491ba63 MY	27	default "davinci"
3491ba63 MY	28
6aa4ad8e AF	29	config DA850_LOWLEVEL
	30	bool "Enable Lowlevel DA850 initialization"
	31	depends on SOC_DA850
	32
f519b364 FP	33	config SYS_DA850_PLL_INIT
	34	bool
	35
b31bf37a FP	36	config SYS_DA850_DDR_INIT
	37	bool
	38
6aa4ad8e AF	39	config SOC_DA850
	40	bool
	41	select SOC_DA8XX
6aa4ad8e AF	42
	43	config SOC_DA8XX
	44	bool
891ab74b	45	select SYS_DA850_DDR_INIT if SUPPORT_SPL \|\| DA850_LOWLEVEL
58008cba	46	select SYS_DA850_PLL_INIT if SUPPORT_SPL \|\| DA850_LOWLEVEL
6aa4ad8e AF	47
	48	config MACH_DAVINCI_DA850_EVM
	49	bool
	50
76e22222 AF	51	if SYS_DA850_PLL_INIT
	52	comment "DA850 PLL Initialization Parameters"
	53
	54	config SYS_DV_CLKMODE
	55	int "PLLCTL Clock Mode"
2e879805	56	default 0
76e22222 AF	57	help
	58	Set PLLCTL Clock Mode bit as External Clock or On Chip oscillator
	59
	60	config SYS_DA850_PLL0_POSTDIV
	61	int "PLLC0 PLL Post-Divider"
2e879805	62	default 1
76e22222 AF	63	help
	64	Value written to PLLC0 PLL Post-Divider Control Register
	65
	66	config SYS_DA850_PLL0_PLLDIV1
	67	hex "PLLC0 Divider 1"
2e879805	68	default 0x8000
76e22222 AF	69	help
	70	Value written to PLLC0 Divider 1 register
	71
	72	config SYS_DA850_PLL0_PLLDIV2
	73	hex "PLLC0 Divider 2"
2e879805	74	default 0x8001
76e22222 AF	75	help
	76	Value written to PLLC0 Divider 2 register
	77
	78	config SYS_DA850_PLL0_PLLDIV3
	79	hex "PLLC0 Divider 3"
2e879805	80	default 0x8002
76e22222 AF	81	help
	82	Value written to PLLC0 Divider 3 register
	83
	84	config SYS_DA850_PLL0_PLLDIV4
	85	hex "PLLC0 Divider 4"
2e879805	86	default 0x8003
76e22222 AF	87	help
	88	Value written to PLLC0 Divider 4 register
	89
	90	config SYS_DA850_PLL0_PLLDIV5
	91	hex "PLLC0 Divider 5"
2e879805	92	default 0x8002
76e22222 AF	93	help
	94	Value written to PLLC0 Divider 5 register
	95
	96	config SYS_DA850_PLL0_PLLDIV6
	97	hex "PLLC0 Divider 6"
2e879805	98	default 0x8000
76e22222 AF	99	help
	100	Value written to PLLC0 Divider 6 register
	101
	102	config SYS_DA850_PLL0_PLLDIV7
	103	hex "PLLC0 Divider 7"
2e879805	104	default 0x8005
76e22222 AF	105	help
	106	Value written to PLLC0 Divider 7 register
	107
	108	config SYS_DA850_PLL1_POSTDIV
	109	hex "PLLC1 PLL Post-Divider"
2e879805	110	default 1
76e22222 AF	111	help
	112	Value written to PLLC1 PLL Post-Divider Control Register
	113
	114	config SYS_DA850_PLL1_PLLDIV1
	115	hex "PLLC1 Divider 2"
2e879805	116	default 0x8000
76e22222 AF	117	help
	118	Value written to PLLC1 Divider 1 register
	119
	120	config SYS_DA850_PLL1_PLLDIV2
	121	hex "PLLC1 Divider 2"
2e879805	122	default 0x8001
76e22222 AF	123	help
	124	Value written to PLLC1 Divider 2 register
	125
	126	config SYS_DA850_PLL1_PLLDIV3
	127	hex "PLLC1 Divider 3"
2e879805	128	default 0x8002
76e22222 AF	129	help
	130	Value written to PLLC1 Divider 3 register
	131
	132	endif
	133
3491ba63	134	source "board/davinci/da8xxevm/Kconfig"
2ac07f75	135	source "board/lego/ev3/Kconfig"
3491ba63	136
b529993e	137	config SPL_LDSCRIPT
2c59412a	138	default "board/davinci/da8xxevm/u-boot-spl-da850evm.lds"
b529993e	139
3491ba63	140	endif