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dm: i2c: use CONFIG_IS_ENABLED macro for DM_I2C/DM_I2C_GPIO
[J-u-boot.git] / board / sunxi / board.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
cba69eee
IC		 2/*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <[email protected]>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <[email protected]>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <[email protected]>
9 *
10 * Some board init for the Allwinner A10-evb board.
cba69eee
IC		 11 */
12
13#include <common.h>
237050fc 14#include <dm.h>
c7694dd4 15#include <env.h>
db41d65a 16#include <hang.h>
4d72caa5 17#include <image.h>
9b4a205f 18#include <init.h>
f7ae49fc 19#include <log.h>
e79c7c88 20#include <mmc.h>
6944aff1 21#include <axp_pmic.h>
237050fc
JT		 22#include <generic-phy.h>
23#include <phy-sun4i-usb.h>
cba69eee 24#include <asm/arch/clock.h>
b41d7d05 25#include <asm/arch/cpu.h>
2d7a084b 26#include <asm/arch/display.h>
cba69eee 27#include <asm/arch/dram.h>
e24ea55c
IC		 28#include <asm/arch/gpio.h>
29#include <asm/arch/mmc.h>
8a8b73b6 30#include <asm/arch/prcm.h>
4a8c7c1f 31#include <asm/arch/spl.h>
401d1c4f 32#include <asm/global_data.h>
c05ed00a 33#include <linux/delay.h>
3db71108 34#include <u-boot/crc.h>
d96ebc46
SS		 35#ifndef CONFIG_ARM64
36#include <asm/armv7.h>
37#endif
4f7e01c9 38#include <asm/gpio.h>
b41d7d05 39#include <asm/io.h>
a740ee91 40#include <u-boot/crc.h>
f3998fdc 41#include <env_internal.h>
b08c8c48 42#include <linux/libfdt.h>
9267ff89 43#include <fdt_support.h>
f62bfa56 44#include <nand.h>
b41d7d05 45#include <net.h>
f4c3523c 46#include <spl.h>
0d8382ae 47#include <sy8106a.h>
5d982856 48#include <asm/setup.h>
cba69eee 49
55410089
HG		 50#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
51/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
52int soft_i2c_gpio_sda;
53int soft_i2c_gpio_scl;
4f7e01c9
HG		 54
55static int soft_i2c_board_init(void)
56{
57 int ret;
58
59 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
60 if (soft_i2c_gpio_sda < 0) {
61 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
62 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
63 return soft_i2c_gpio_sda;
64 }
65 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
66 if (ret) {
67 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
68 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
69 return ret;
70 }
71
72 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
73 if (soft_i2c_gpio_scl < 0) {
74 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
75 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
76 return soft_i2c_gpio_scl;
77 }
78 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
79 if (ret) {
80 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
81 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
82 return ret;
83 }
84
85 return 0;
86}
87#else
88static int soft_i2c_board_init(void) { return 0; }
55410089
HG		 89#endif
90
cba69eee
IC		 91DECLARE_GLOBAL_DATA_PTR;
92
acbc7e0a
JS		 93void i2c_init_board(void)
94{
95#ifdef CONFIG_I2C0_ENABLE
96#if defined(CONFIG_MACH_SUN4I) || \
97 defined(CONFIG_MACH_SUN5I) || \
98 defined(CONFIG_MACH_SUN7I) || \
99 defined(CONFIG_MACH_SUN8I_R40)
100 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
101 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
102 clock_twi_onoff(0, 1);
103#elif defined(CONFIG_MACH_SUN6I)
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
105 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
106 clock_twi_onoff(0, 1);
8c51c652
IZ		 107#elif defined(CONFIG_MACH_SUN8I_V3S)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
110 clock_twi_onoff(0, 1);
acbc7e0a
JS		 111#elif defined(CONFIG_MACH_SUN8I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
113 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
114 clock_twi_onoff(0, 1);
da1ae590
SM		 115#elif defined(CONFIG_MACH_SUN50I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
118 clock_twi_onoff(0, 1);
acbc7e0a
JS		 119#endif
120#endif
121
122#ifdef CONFIG_I2C1_ENABLE
123#if defined(CONFIG_MACH_SUN4I) || \
124 defined(CONFIG_MACH_SUN7I) || \
125 defined(CONFIG_MACH_SUN8I_R40)
126 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
127 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
128 clock_twi_onoff(1, 1);
129#elif defined(CONFIG_MACH_SUN5I)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
132 clock_twi_onoff(1, 1);
133#elif defined(CONFIG_MACH_SUN6I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
135 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
136 clock_twi_onoff(1, 1);
137#elif defined(CONFIG_MACH_SUN8I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
140 clock_twi_onoff(1, 1);
da1ae590
SM		 141#elif defined(CONFIG_MACH_SUN50I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
143 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
144 clock_twi_onoff(1, 1);
acbc7e0a
JS		 145#endif
146#endif
147
148#ifdef CONFIG_I2C2_ENABLE
149#if defined(CONFIG_MACH_SUN4I) || \
150 defined(CONFIG_MACH_SUN7I) || \
151 defined(CONFIG_MACH_SUN8I_R40)
152 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
153 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
154 clock_twi_onoff(2, 1);
155#elif defined(CONFIG_MACH_SUN5I)
156 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
157 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
158 clock_twi_onoff(2, 1);
159#elif defined(CONFIG_MACH_SUN6I)
160 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
161 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
162 clock_twi_onoff(2, 1);
163#elif defined(CONFIG_MACH_SUN8I)
164 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
165 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
166 clock_twi_onoff(2, 1);
da1ae590
SM		 167#elif defined(CONFIG_MACH_SUN50I)
168 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
169 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
170 clock_twi_onoff(2, 1);
acbc7e0a
JS		 171#endif
172#endif
173
174#ifdef CONFIG_I2C3_ENABLE
175#if defined(CONFIG_MACH_SUN6I)
176 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
177 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
178 clock_twi_onoff(3, 1);
179#elif defined(CONFIG_MACH_SUN7I) || \
180 defined(CONFIG_MACH_SUN8I_R40)
181 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
182 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
183 clock_twi_onoff(3, 1);
184#endif
185#endif
186
187#ifdef CONFIG_I2C4_ENABLE
188#if defined(CONFIG_MACH_SUN7I) || \
189 defined(CONFIG_MACH_SUN8I_R40)
190 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
191 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
192 clock_twi_onoff(4, 1);
193#endif
194#endif
195
196#ifdef CONFIG_R_I2C_ENABLE
31a4ac4d
VK		 197#ifdef CONFIG_MACH_SUN50I
198 clock_twi_onoff(5, 1);
199 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
200 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
d0b07c15
JS		 201#elif CONFIG_MACH_SUN50I_H616
202 clock_twi_onoff(5, 1);
203 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
204 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
31a4ac4d 205#else
acbc7e0a
JS		 206 clock_twi_onoff(5, 1);
207 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
208 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
209#endif
31a4ac4d 210#endif
acbc7e0a
JS		 211}
212
b39117ca
MR		 213#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
214enum env_location env_get_location(enum env_operation op, int prio)
215{
216 switch (prio) {
217 case 0:
218 return ENVL_FAT;
219
220 case 1:
221 return ENVL_MMC;
222
223 default:
224 return ENVL_UNKNOWN;
225 }
226}
227#endif
228
a7ae1599
AP		 229#ifdef CONFIG_DM_MMC
230static void mmc_pinmux_setup(int sdc);
231#endif
232
cba69eee
IC		 233/* add board specific code here */
234int board_init(void)
235{
f5fd7886 236 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
cba69eee
IC		 237
238 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
239
d96ebc46 240#ifndef CONFIG_ARM64
cba69eee
IC		 241 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
242 debug("id_pfr1: 0x%08x\n", id_pfr1);
243 /* Generic Timer Extension available? */
d96ebc46
SS		 244 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
245 uint32_t freq;
246
cba69eee 247 debug("Setting CNTFRQ\n");
d96ebc46
SS		 248
249 /*
250 * CNTFRQ is a secure register, so we will crash if we try to
251 * write this from the non-secure world (read is OK, though).
252 * In case some bootcode has already set the correct value,
253 * we avoid the risk of writing to it.
254 */
255 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
e4916e85 256 if (freq != COUNTER_FREQUENCY) {
d96ebc46 257 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
e4916e85 258 freq, COUNTER_FREQUENCY);
d96ebc46
SS		 259#ifdef CONFIG_NON_SECURE
260 printf("arch timer frequency is wrong, but cannot adjust it\n");
261#else
262 asm volatile("mcr p15, 0, %0, c14, c0, 0"
e4916e85 263 : : "r"(COUNTER_FREQUENCY));
d96ebc46
SS		 264#endif
265 }
cba69eee 266 }
d96ebc46 267#endif /* !CONFIG_ARM64 */
cba69eee 268
2fcf033d
HG		 269 ret = axp_gpio_init();
270 if (ret)
271 return ret;
272
e9ad1b8d
AP		 273 /* strcmp() would look better, but doesn't get optimised away. */
274 if (CONFIG_SATAPWR[0]) {
275 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
276 if (satapwr_pin >= 0) {
277 gpio_request(satapwr_pin, "satapwr");
278 gpio_direction_output(satapwr_pin, 1);
279
280 /*
281 * Give the attached SATA device time to power-up
282 * to avoid link timeouts
283 */
284 mdelay(500);
285 }
286 }
287
288 if (CONFIG_MACPWR[0]) {
289 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
290 if (macpwr_pin >= 0) {
291 gpio_request(macpwr_pin, "macpwr");
292 gpio_direction_output(macpwr_pin, 1);
293 }
294 }
fc8991c6 295
2147a169 296#if CONFIG_IS_ENABLED(DM_I2C)
a8f01ccf
JS		 297 /*
298 * Temporary workaround for enabling I2C clocks until proper sunxi DM
299 * clk, reset and pinctrl drivers land.
300 */
301 i2c_init_board();
302#endif
303
a7ae1599
AP		 304#ifdef CONFIG_DM_MMC
305 /*
306 * Temporary workaround for enabling MMC clocks until a sunxi DM
307 * pinctrl driver lands.
308 */
309 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
310#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
311 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
312#endif
313#endif /* CONFIG_DM_MMC */
314
4f7e01c9
HG		 315 /* Uses dm gpio code so do this here and not in i2c_init_board() */
316 return soft_i2c_board_init();
cba69eee
IC		 317}
318
cff5c138
AP		 319/*
320 * On older SoCs the SPL is actually at address zero, so using NULL as
321 * an error value does not work.
322 */
323#define INVALID_SPL_HEADER ((void *)~0UL)
324
325static struct boot_file_head * get_spl_header(uint8_t req_version)
326{
327 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
328 uint8_t spl_header_version = spl->spl_signature[3];
329
330 /* Is there really the SPL header (still) there? */
331 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
332 return INVALID_SPL_HEADER;
333
334 if (spl_header_version < req_version) {
335 printf("sunxi SPL version mismatch: expected %u, got %u\n",
336 req_version, spl_header_version);
337 return INVALID_SPL_HEADER;
338 }
339
340 return spl;
341}
342
467b7e52
SH		 343static const char *get_spl_dt_name(void)
344{
345 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
346
347 /* Check if there is a DT name stored in the SPL header. */
348 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
349 return (char *)spl + spl->dt_name_offset;
350
351 return NULL;
352}
467b7e52 353
cba69eee
IC		 354int dram_init(void)
355{
5776610e
AP		 356 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
357
358 if (spl == INVALID_SPL_HEADER)
359 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
360 PHYS_SDRAM_0_SIZE);
361 else
362 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
363
364 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
365 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
cba69eee
IC		 366
367 return 0;
368}
369
4ccae81c 370#if defined(CONFIG_NAND_SUNXI)
ad008299
KG		 371static void nand_pinmux_setup(void)
372{
373 unsigned int pin;
ad008299 374
022a99d8 375 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
ad008299
KG		 376 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
377
022a99d8
HG		 378#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
379 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
380 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
381#endif
382 /* sun4i / sun7i do have a PC23, but it is not used for nand,
383 * only sun7i has a PC24 */
384#ifdef CONFIG_MACH_SUN7I
ad008299 385 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
022a99d8 386#endif
ad008299
KG		 387}
388
389static void nand_clock_setup(void)
390{
391 struct sunxi_ccm_reg *const ccm =
392 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
31c21471 393
ad008299 394 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
ba1c98ba
MR		 395#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
396 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
397 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
31c21471 398#endif
ad008299
KG		 399 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
400}
f62bfa56
HG		 401
402void board_nand_init(void)
403{
404 nand_pinmux_setup();
405 nand_clock_setup();
4ccae81c
BB		 406#ifndef CONFIG_SPL_BUILD
407 sunxi_nand_init();
408#endif
f62bfa56 409}
ad008299
KG		 410#endif
411
4aa2ba3a 412#ifdef CONFIG_MMC
e24ea55c
IC		 413static void mmc_pinmux_setup(int sdc)
414{
415 unsigned int pin;
8deacca9 416 __maybe_unused int pins;
e24ea55c
IC		 417
418 switch (sdc) {
419 case 0:
8deacca9 420 /* SDC0: PF0-PF5 */
e24ea55c 421 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
487b3277 422 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
e24ea55c
IC		 423 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
424 sunxi_gpio_set_drv(pin, 2);
425 }
426 break;
427
428 case 1:
8deacca9
PK		 429 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
430
8094a4a2
CYT		 431#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
432 defined(CONFIG_MACH_SUN8I_R40)
8deacca9
PK		 433 if (pins == SUNXI_GPIO_H) {
434 /* SDC1: PH22-PH-27 */
435 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
439 }
440 } else {
441 /* SDC1: PG0-PG5 */
442 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
443 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
444 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
445 sunxi_gpio_set_drv(pin, 2);
446 }
447 }
448#elif defined(CONFIG_MACH_SUN5I)
449 /* SDC1: PG3-PG8 */
bbff84b3 450 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
487b3277 451 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
e24ea55c
IC		 452 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
453 sunxi_gpio_set_drv(pin, 2);
454 }
8deacca9
PK		 455#elif defined(CONFIG_MACH_SUN6I)
456 /* SDC1: PG0-PG5 */
457 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
458 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
459 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
460 sunxi_gpio_set_drv(pin, 2);
461 }
462#elif defined(CONFIG_MACH_SUN8I)
463 if (pins == SUNXI_GPIO_D) {
464 /* SDC1: PD2-PD7 */
465 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
466 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
467 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
468 sunxi_gpio_set_drv(pin, 2);
469 }
470 } else {
471 /* SDC1: PG0-PG5 */
472 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
473 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
474 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
475 sunxi_gpio_set_drv(pin, 2);
476 }
477 }
478#endif
e24ea55c
IC		 479 break;
480
481 case 2:
8deacca9
PK		 482 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
483
484#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
485 /* SDC2: PC6-PC11 */
e24ea55c 486 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
487b3277 487 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
e24ea55c
IC		 488 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
489 sunxi_gpio_set_drv(pin, 2);
490 }
8deacca9
PK		 491#elif defined(CONFIG_MACH_SUN5I)
492 if (pins == SUNXI_GPIO_E) {
493 /* SDC2: PE4-PE9 */
494 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
495 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
496 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
497 sunxi_gpio_set_drv(pin, 2);
498 }
499 } else {
500 /* SDC2: PC6-PC15 */
501 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
502 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
503 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
504 sunxi_gpio_set_drv(pin, 2);
505 }
506 }
507#elif defined(CONFIG_MACH_SUN6I)
508 if (pins == SUNXI_GPIO_A) {
509 /* SDC2: PA9-PA14 */
510 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
511 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
512 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
513 sunxi_gpio_set_drv(pin, 2);
514 }
515 } else {
516 /* SDC2: PC6-PC15, PC24 */
517 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
518 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
519 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
520 sunxi_gpio_set_drv(pin, 2);
521 }
522
523 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
524 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
525 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
526 }
8094a4a2
CYT		 527#elif defined(CONFIG_MACH_SUN8I_R40)
528 /* SDC2: PC6-PC15, PC24 */
529 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
530 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
531 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
532 sunxi_gpio_set_drv(pin, 2);
533 }
534
535 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
536 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
537 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
d96ebc46 538#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
8deacca9
PK		 539 /* SDC2: PC5-PC6, PC8-PC16 */
540 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
541 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
542 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
543 sunxi_gpio_set_drv(pin, 2);
544 }
545
546 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
547 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
548 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
549 sunxi_gpio_set_drv(pin, 2);
42956f1b
IZ		 550 }
551#elif defined(CONFIG_MACH_SUN50I_H6)
552 /* SDC2: PC4-PC14 */
553 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
554 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
555 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
556 sunxi_gpio_set_drv(pin, 2);
8deacca9 557 }
3ebb4567
PT		 558#elif defined(CONFIG_MACH_SUN9I)
559 /* SDC2: PC6-PC16 */
560 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
561 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
562 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
563 sunxi_gpio_set_drv(pin, 2);
564 }
8deacca9 565#endif
e24ea55c
IC		 566 break;
567
568 case 3:
8deacca9
PK		 569 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
570
8094a4a2
CYT		 571#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
572 defined(CONFIG_MACH_SUN8I_R40)
8deacca9 573 /* SDC3: PI4-PI9 */
e24ea55c 574 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
8deacca9 575 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
e24ea55c
IC		 576 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
577 sunxi_gpio_set_drv(pin, 2);
578 }
8deacca9
PK		 579#elif defined(CONFIG_MACH_SUN6I)
580 if (pins == SUNXI_GPIO_A) {
581 /* SDC3: PA9-PA14 */
582 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
583 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
584 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
585 sunxi_gpio_set_drv(pin, 2);
586 }
587 } else {
588 /* SDC3: PC6-PC15, PC24 */
589 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
590 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
591 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
592 sunxi_gpio_set_drv(pin, 2);
593 }
594
595 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
596 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
597 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
598 }
599#endif
e24ea55c
IC		 600 break;
601
602 default:
603 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
604 break;
605 }
606}
607
b75d8dc5 608int board_mmc_init(struct bd_info *bis)
e24ea55c 609{
e79c7c88 610 __maybe_unused struct mmc *mmc0, *mmc1;
e79c7c88 611
e24ea55c 612 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
e79c7c88
HG		 613 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
614 if (!mmc0)
615 return -1;
616
2ccfac01 617#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
e24ea55c 618 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
e79c7c88
HG		 619 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
620 if (!mmc1)
621 return -1;
622#endif
623
e24ea55c
IC		 624 return 0;
625}
626#endif
627
cba69eee 628#ifdef CONFIG_SPL_BUILD
5776610e
AP		 629
630static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
631{
632 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
633
634 if (spl == INVALID_SPL_HEADER)
635 return;
636
637 /* Promote the header version for U-Boot proper, if needed. */
638 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
639 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
640
641 spl->dram_size = dram_size >> 20;
642}
643
cba69eee
IC		 644void sunxi_board_init(void)
645{
14bc66bd 646 int power_failed = 0;
cba69eee 647
0d8382ae
JW		 648#ifdef CONFIG_SY8106A_POWER
649 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
650#endif
651
95ab8fee 652#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
fbd37d8d
JS		 653 defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
654 defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
6944aff1
HG		 655 power_failed = axp_init();
656
795857df
CYT		 657#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
658 defined CONFIG_AXP818_POWER
6944aff1 659 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
24289208 660#endif
fbd37d8d 661#if !defined(CONFIG_AXP305_POWER)
6944aff1
HG		 662 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
663 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
fbd37d8d 664#endif
95ab8fee 665#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
6944aff1 666 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
5c7f10fd 667#endif
795857df
CYT		 668#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
669 defined CONFIG_AXP818_POWER
6944aff1 670 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
14bc66bd
HN		 671#endif
672
795857df
CYT		 673#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
674 defined CONFIG_AXP818_POWER
6944aff1
HG		 675 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
676#endif
fbd37d8d 677#if !defined(CONFIG_AXP305_POWER)
6944aff1 678 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
fbd37d8d
JS		 679#endif
680#if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
6944aff1
HG		 681 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
682#endif
683#ifdef CONFIG_AXP209_POWER
684 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
685#endif
686
795857df
CYT		 687#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
688 defined(CONFIG_AXP818_POWER)
3517a27d
CYT		 689 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
690 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
795857df 691#if !defined CONFIG_AXP809_POWER
3517a27d
CYT		 692 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
693 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
795857df 694#endif
6944aff1
HG		 695 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
696 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
697 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
698#endif
38491d9c
CYT		 699
700#ifdef CONFIG_AXP818_POWER
701 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
702 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
703 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
795857df
CYT		 704#endif
705
706#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
15278ccb 707 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
38491d9c 708#endif
6944aff1 709#endif
44c214dc
FKP		 710 printf("DRAM:");
711 gd->ram_size = sunxi_dram_init();
712 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
713 if (!gd->ram_size)
714 hang();
715
716 sunxi_spl_store_dram_size(gd->ram_size);
5776610e 717
14bc66bd
HN		 718 /*
719 * Only clock up the CPU to full speed if we are reasonably
720 * assured it's being powered with suitable core voltage
721 */
722 if (!power_failed)
e71b422b 723 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
14bc66bd 724 else
44c214dc 725 printf("Failed to set core voltage! Can't set CPU frequency\n");
cba69eee
IC		 726}
727#endif
b41d7d05 728
f1df758d
PK		 729#ifdef CONFIG_USB_GADGET
730int g_dnl_board_usb_cable_connected(void)
731{
237050fc
JT		 732 struct udevice *dev;
733 struct phy phy;
734 int ret;
735
01311624 736 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
237050fc
JT		 737 if (ret) {
738 pr_err("%s: Cannot find USB device\n", __func__);
739 return ret;
740 }
741
742 ret = generic_phy_get_by_name(dev, "usb", &phy);
743 if (ret) {
744 pr_err("failed to get %s USB PHY\n", dev->name);
745 return ret;
746 }
747
748 ret = generic_phy_init(&phy);
749 if (ret) {
f286e37c 750 pr_debug("failed to init %s USB PHY\n", dev->name);
237050fc
JT		 751 return ret;
752 }
753
754 ret = sun4i_usb_phy_vbus_detect(&phy);
755 if (ret == 1) {
756 pr_err("A charger is plugged into the OTG\n");
757 return -ENODEV;
758 }
759
760 return ret;
f1df758d
PK		 761}
762#endif
763
9f852211
PK		 764#ifdef CONFIG_SERIAL_TAG
765void get_board_serial(struct tag_serialnr *serialnr)
766{
767 char *serial_string;
768 unsigned long long serial;
769
00caae6d 770 serial_string = env_get("serial#");
9f852211
PK		 771
772 if (serial_string) {
773 serial = simple_strtoull(serial_string, NULL, 16);
774
775 serialnr->high = (unsigned int) (serial >> 32);
776 serialnr->low = (unsigned int) (serial & 0xffffffff);
777 } else {
778 serialnr->high = 0;
779 serialnr->low = 0;
780 }
781}
782#endif
783
af654d14
BN		 784/*
785 * Check the SPL header for the "sunxi" variant. If found: parse values
786 * that might have been passed by the loader ("fel" utility), and update
787 * the environment accordingly.
788 */
789static void parse_spl_header(const uint32_t spl_addr)
790{
cff5c138 791 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
320e0570 792
cff5c138 793 if (spl == INVALID_SPL_HEADER)
320e0570 794 return;
cff5c138 795
320e0570
BN		 796 if (!spl->fel_script_address)
797 return;
798
799 if (spl->fel_uEnv_length != 0) {
800 /*
801 * data is expected in uEnv.txt compatible format, so "env
802 * import -t" the string(s) at fel_script_address right away.
803 */
5a74a391 804 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
320e0570
BN		 805 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
806 return;
af654d14 807 }
320e0570 808 /* otherwise assume .scr format (mkimage-type script) */
018f5303 809 env_set_hex("fel_scriptaddr", spl->fel_script_address);
af654d14 810}
af654d14 811
928f4f48
AH		 812static bool get_unique_sid(unsigned int *sid)
813{
814 if (sunxi_get_sid(sid) != 0)
815 return false;
816
817 if (!sid[0])
818 return false;
819
820 /*
821 * The single words 1 - 3 of the SID have quite a few bits
822 * which are the same on many models, so we take a crc32
823 * of all 3 words, to get a more unique value.
824 *
825 * Note we only do this on newer SoCs as we cannot change
826 * the algorithm on older SoCs since those have been using
827 * fixed mac-addresses based on only using word 3 for a
828 * long time and changing a fixed mac-address with an
829 * u-boot update is not good.
830 */
831#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
832 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
833 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
834 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
835#endif
836
837 /* Ensure the NIC specific bytes of the mac are not all 0 */
838 if ((sid[3] & 0xffffff) == 0)
839 sid[3] |= 0x800000;
840
841 return true;
842}
843
f221961e
HG		 844/*
845 * Note this function gets called multiple times.
846 * It must not make any changes to env variables which already exist.
847 */
848static void setup_environment(const void *fdt)
b41d7d05 849{
8c816573 850 char serial_string[17] = { 0 };
cac5b1cc 851 unsigned int sid[4];
8c816573 852 uint8_t mac_addr[6];
f221961e 853 char ethaddr[16];
928f4f48 854 int i;
3f8ea3b0 855
928f4f48
AH		 856 if (!get_unique_sid(sid))
857 return;
97322c3e 858
928f4f48
AH		 859 for (i = 0; i < 4; i++) {
860 sprintf(ethaddr, "ethernet%d", i);
861 if (!fdt_get_alias(fdt, ethaddr))
862 continue;
f221961e 863
928f4f48
AH		 864 if (i == 0)
865 strcpy(ethaddr, "ethaddr");
866 else
867 sprintf(ethaddr, "eth%daddr", i);
f221961e 868
928f4f48
AH		 869 if (env_get(ethaddr))
870 continue;
f221961e 871
928f4f48
AH		 872 /* Non OUI / registered MAC address */
873 mac_addr[0] = (i << 4) | 0x02;
874 mac_addr[1] = (sid[0] >> 0) & 0xff;
875 mac_addr[2] = (sid[3] >> 24) & 0xff;
876 mac_addr[3] = (sid[3] >> 16) & 0xff;
877 mac_addr[4] = (sid[3] >> 8) & 0xff;
878 mac_addr[5] = (sid[3] >> 0) & 0xff;
8c816573 879
928f4f48
AH		 880 eth_env_set_enetaddr(ethaddr, mac_addr);
881 }
b41d7d05 882
928f4f48
AH		 883 if (!env_get("serial#")) {
884 snprintf(serial_string, sizeof(serial_string),
885 "%08x%08x", sid[0], sid[3]);
b41d7d05 886
928f4f48 887 env_set("serial#", serial_string);
b41d7d05 888 }
f221961e
HG		 889}
890
f221961e
HG		 891int misc_init_r(void)
892{
20f3ee31 893 const char *spl_dt_name;
f4c3523c 894 uint boot;
f221961e 895
382bee57
SG		 896 env_set("fel_booted", NULL);
897 env_set("fel_scriptaddr", NULL);
de86fc38 898 env_set("mmc_bootdev", NULL);
f4c3523c
MR		 899
900 boot = sunxi_get_boot_device();
f221961e 901 /* determine if we are running in FEL mode */
f4c3523c 902 if (boot == BOOT_DEVICE_BOARD) {
382bee57 903 env_set("fel_booted", "1");
f221961e 904 parse_spl_header(SPL_ADDR);
de86fc38
MR		 905 /* or if we booted from MMC, and which one */
906 } else if (boot == BOOT_DEVICE_MMC1) {
907 env_set("mmc_bootdev", "0");
908 } else if (boot == BOOT_DEVICE_MMC2) {
909 env_set("mmc_bootdev", "1");
f221961e 910 }
f221961e 911
20f3ee31
SH		 912 /* Set fdtfile to match the FIT configuration chosen in SPL. */
913 spl_dt_name = get_spl_dt_name();
914 if (spl_dt_name) {
915 char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
916 char str[64];
917
918 snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
919 env_set("fdtfile", str);
920 }
921
f221961e 922 setup_environment(gd->fdt_blob);
b41d7d05 923
92600edb
AS		 924 return 0;
925}
926
927int board_late_init(void)
928{
e6ee85a6 929#ifdef CONFIG_USB_ETHER
90dd2f19 930 usb_ether_init();
e6ee85a6 931#endif
90dd2f19 932
b41d7d05
JL		 933 return 0;
934}
2d7a084b 935
9267ff89
AH		 936static void bluetooth_dt_fixup(void *blob)
937{
938 /* Some devices ship with a Bluetooth controller default address.
939 * Set a valid address through the device tree.
940 */
941 uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
942 unsigned int sid[4];
943 int i;
944
945 if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
946 return;
947
948 if (eth_env_get_enetaddr("bdaddr", tmp)) {
949 /* Convert between the binary formats of the corresponding stacks */
950 for (i = 0; i < ETH_ALEN; ++i)
951 bdaddr[i] = tmp[ETH_ALEN - i - 1];
952 } else {
953 if (!get_unique_sid(sid))
954 return;
955
956 bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
957 bdaddr[1] = (sid[3] >> 8) & 0xff;
958 bdaddr[2] = (sid[3] >> 16) & 0xff;
959 bdaddr[3] = (sid[3] >> 24) & 0xff;
960 bdaddr[4] = (sid[0] >> 0) & 0xff;
961 bdaddr[5] = 0x02;
962 }
963
964 do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
965 "local-bd-address", bdaddr, ETH_ALEN, 1);
966}
967
b75d8dc5 968int ft_board_setup(void *blob, struct bd_info *bd)
2d7a084b 969{
d75111a7
HG		 970 int __maybe_unused r;
971
f221961e
HG		 972 /*
973 * Call setup_environment again in case the boot fdt has
974 * ethernet aliases the u-boot copy does not have.
975 */
976 setup_environment(blob);
977
9267ff89
AH		 978 bluetooth_dt_fixup(blob);
979
2d7a084b 980#ifdef CONFIG_VIDEO_DT_SIMPLEFB
d75111a7
HG		 981 r = sunxi_simplefb_setup(blob);
982 if (r)
983 return r;
2d7a084b 984#endif
d75111a7 985 return 0;
2d7a084b 986}
9ea3c35a
AP		 987
988#ifdef CONFIG_SPL_LOAD_FIT
41530cf6
SH		 989
990static void set_spl_dt_name(const char *name)
991{
992 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
993
994 if (spl == INVALID_SPL_HEADER)
995 return;
996
997 /* Promote the header version for U-Boot proper, if needed. */
998 if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
999 spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
1000
1001 strcpy((char *)&spl->string_pool, name);
1002 spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
1003}
1004
9ea3c35a
AP		 1005int board_fit_config_name_match(const char *name)
1006{
467b7e52 1007 const char *best_dt_name = get_spl_dt_name();
41530cf6 1008 int ret;
9ea3c35a
AP		 1009
1010#ifdef CONFIG_DEFAULT_DEVICE_TREE
467b7e52 1011 if (best_dt_name == NULL)
2fcd7489 1012 best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
9ea3c35a
AP		 1013#endif
1014
467b7e52
SH		 1015 if (best_dt_name == NULL) {
1016 /* No DT name was provided, so accept the first config. */
1017 return 0;
1018 }
c6c2c85e 1019#ifdef CONFIG_PINE64_DT_SELECTION
54ac5aa1
SH		 1020 if (strstr(best_dt_name, "-pine64-plus")) {
1021 /* Differentiate the Pine A64 boards by their DRAM size. */
1022 if ((gd->ram_size == 512 * 1024 * 1024))
1023 best_dt_name = "sun50i-a64-pine64";
9ea3c35a 1024 }
c6c2c85e 1025#endif
8a8b73b6
SH		 1026#ifdef CONFIG_PINEPHONE_DT_SELECTION
1027 if (strstr(best_dt_name, "-pinephone")) {
1028 /* Differentiate the PinePhone revisions by GPIO inputs. */
1029 prcm_apb0_enable(PRCM_APB0_GATE_PIO);
1030 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
1031 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
1032 udelay(100);
1033
1034 /* PL6 is pulled low by the modem on v1.2. */
1035 if (gpio_get_value(SUNXI_GPL(6)) == 0)
1036 best_dt_name = "sun50i-a64-pinephone-1.2";
1037 else
1038 best_dt_name = "sun50i-a64-pinephone-1.1";
1039
1040 sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
1041 sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
1042 prcm_apb0_disable(PRCM_APB0_GATE_PIO);
1043 }
1044#endif
1045
41530cf6
SH		 1046 ret = strcmp(name, best_dt_name);
1047
1048 /*
1049 * If one of the FIT configurations matches the most accurate DT name,
1050 * update the SPL header to provide that DT name to U-Boot proper.
1051 */
1052 if (ret == 0)
1053 set_spl_dt_name(best_dt_name);
1054
1055 return ret;
9ea3c35a
AP		 1056}
1057#endif
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