]> Git Repo - J-u-boot.git/blame - drivers/clk/rockchip/clk_rk3399.c
projects / J-u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
common: Drop linux/printk.h from common header
[J-u-boot.git] / drivers / clk / rockchip / clk_rk3399.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0
b0b3c865
KY		 2/*
3 * (C) Copyright 2015 Google, Inc
8fa6979b 4 * (C) 2017 Theobroma Systems Design und Consulting GmbH
b0b3c865
KY		 5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
5ae2fd97 10#include <dt-structs.h>
b0b3c865 11#include <errno.h>
f7ae49fc 12#include <log.h>
336d4615 13#include <malloc.h>
5ae2fd97 14#include <mapmem.h>
b0b3c865 15#include <syscon.h>
364fc731 16#include <bitfield.h>
b0b3c865 17#include <asm/io.h>
15f09a1a 18#include <asm/arch-rockchip/clock.h>
b52a199e 19#include <asm/arch-rockchip/cru.h>
15f09a1a 20#include <asm/arch-rockchip/hardware.h>
401d1c4f 21#include <asm/global_data.h>
0fd3d911 22#include <dm/device-internal.h>
b0b3c865
KY		 23#include <dm/lists.h>
24#include <dt-bindings/clock/rk3399-cru.h>
cd93d625 25#include <linux/bitops.h>
c05ed00a 26#include <linux/delay.h>
1e94b46f 27#include <linux/printk.h>
b0b3c865 28
eb890250
ANY		 29DECLARE_GLOBAL_DATA_PTR;
30
5ae2fd97
KY		 31#if CONFIG_IS_ENABLED(OF_PLATDATA)
32struct rk3399_clk_plat {
33 struct dtd_rockchip_rk3399_cru dtd;
5e79f443
KY		 34};
35
5ae2fd97
KY		 36struct rk3399_pmuclk_plat {
37 struct dtd_rockchip_rk3399_pmucru dtd;
38};
39#endif
40
b0b3c865
KY		 41struct pll_div {
42 u32 refdiv;
43 u32 fbdiv;
44 u32 postdiv1;
45 u32 postdiv2;
46 u32 frac;
47};
48
49#define RATE_TO_DIV(input_rate, output_rate) \
dd7dfa21
JT		 50 ((input_rate) / (output_rate) - 1)
51#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
b0b3c865
KY		 52
53#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
54 .refdiv = _refdiv,\
55 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
56 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
57
58static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
59static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
eb890250 60#if !defined(CONFIG_SPL_BUILD)
b0b3c865 61static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
61dff33b 62#endif
b0b3c865 63
dd7dfa21
JT		 64static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
65static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
b0b3c865
KY		 66
67static const struct pll_div *apll_l_cfgs[] = {
68 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
69 [APLL_L_600_MHZ] = &apll_l_600_cfg,
70};
71
dd7dfa21 72static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
af765a49
CM		 73static const struct pll_div *apll_b_cfgs[] = {
74 [APLL_B_600_MHZ] = &apll_b_600_cfg,
75};
76
b0b3c865
KY		 77enum {
78 /* PLL_CON0 */
79 PLL_FBDIV_MASK = 0xfff,
80 PLL_FBDIV_SHIFT = 0,
81
82 /* PLL_CON1 */
83 PLL_POSTDIV2_SHIFT = 12,
84 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
85 PLL_POSTDIV1_SHIFT = 8,
86 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
87 PLL_REFDIV_MASK = 0x3f,
88 PLL_REFDIV_SHIFT = 0,
89
90 /* PLL_CON2 */
91 PLL_LOCK_STATUS_SHIFT = 31,
92 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
93 PLL_FRACDIV_MASK = 0xffffff,
94 PLL_FRACDIV_SHIFT = 0,
95
96 /* PLL_CON3 */
97 PLL_MODE_SHIFT = 8,
98 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
99 PLL_MODE_SLOW = 0,
100 PLL_MODE_NORM,
101 PLL_MODE_DEEP,
102 PLL_DSMPD_SHIFT = 3,
103 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
104 PLL_INTEGER_MODE = 1,
105
106 /* PMUCRU_CLKSEL_CON0 */
107 PMU_PCLK_DIV_CON_MASK = 0x1f,
108 PMU_PCLK_DIV_CON_SHIFT = 0,
109
110 /* PMUCRU_CLKSEL_CON1 */
111 SPI3_PLL_SEL_SHIFT = 7,
112 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
113 SPI3_PLL_SEL_24M = 0,
114 SPI3_PLL_SEL_PPLL = 1,
115 SPI3_DIV_CON_SHIFT = 0x0,
116 SPI3_DIV_CON_MASK = 0x7f,
117
118 /* PMUCRU_CLKSEL_CON2 */
119 I2C_DIV_CON_MASK = 0x7f,
5e79f443
KY		 120 CLK_I2C8_DIV_CON_SHIFT = 8,
121 CLK_I2C0_DIV_CON_SHIFT = 0,
b0b3c865
KY		 122
123 /* PMUCRU_CLKSEL_CON3 */
5e79f443 124 CLK_I2C4_DIV_CON_SHIFT = 0,
b0b3c865
KY		 125
126 /* CLKSEL_CON0 */
127 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
128 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
129 CLK_CORE_L_PLL_SEL_SHIFT = 6,
130 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
131 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
132 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
133 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
134 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
135 CLK_CORE_L_DIV_MASK = 0x1f,
136 CLK_CORE_L_DIV_SHIFT = 0,
137
138 /* CLKSEL_CON1 */
139 PCLK_DBG_L_DIV_SHIFT = 0x8,
140 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
141 ATCLK_CORE_L_DIV_SHIFT = 0,
142 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
143
af765a49
CM		 144 /* CLKSEL_CON2 */
145 ACLKM_CORE_B_DIV_CON_SHIFT = 8,
146 ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
147 CLK_CORE_B_PLL_SEL_SHIFT = 6,
148 CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
149 CLK_CORE_B_PLL_SEL_ALPLL = 0x0,
150 CLK_CORE_B_PLL_SEL_ABPLL = 0x1,
151 CLK_CORE_B_PLL_SEL_DPLL = 0x10,
152 CLK_CORE_B_PLL_SEL_GPLL = 0x11,
153 CLK_CORE_B_DIV_MASK = 0x1f,
154 CLK_CORE_B_DIV_SHIFT = 0,
155
156 /* CLKSEL_CON3 */
157 PCLK_DBG_B_DIV_SHIFT = 0x8,
158 PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT,
159 ATCLK_CORE_B_DIV_SHIFT = 0,
160 ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
161
b0b3c865
KY		 162 /* CLKSEL_CON14 */
163 PCLK_PERIHP_DIV_CON_SHIFT = 12,
164 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
165 HCLK_PERIHP_DIV_CON_SHIFT = 8,
166 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
167 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
168 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
169 ACLK_PERIHP_PLL_SEL_CPLL = 0,
170 ACLK_PERIHP_PLL_SEL_GPLL = 1,
171 ACLK_PERIHP_DIV_CON_SHIFT = 0,
172 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
173
174 /* CLKSEL_CON21 */
175 ACLK_EMMC_PLL_SEL_SHIFT = 7,
176 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
177 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
178 ACLK_EMMC_DIV_CON_SHIFT = 0,
179 ACLK_EMMC_DIV_CON_MASK = 0x1f,
180
181 /* CLKSEL_CON22 */
182 CLK_EMMC_PLL_SHIFT = 8,
183 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
184 CLK_EMMC_PLL_SEL_GPLL = 0x1,
fd4b2dc0 185 CLK_EMMC_PLL_SEL_24M = 0x5,
b0b3c865
KY		 186 CLK_EMMC_DIV_CON_SHIFT = 0,
187 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
188
189 /* CLKSEL_CON23 */
190 PCLK_PERILP0_DIV_CON_SHIFT = 12,
191 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
192 HCLK_PERILP0_DIV_CON_SHIFT = 8,
193 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
194 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
195 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
196 ACLK_PERILP0_PLL_SEL_CPLL = 0,
197 ACLK_PERILP0_PLL_SEL_GPLL = 1,
198 ACLK_PERILP0_DIV_CON_SHIFT = 0,
199 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
200
201 /* CLKSEL_CON25 */
202 PCLK_PERILP1_DIV_CON_SHIFT = 8,
203 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
204 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
205 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
206 HCLK_PERILP1_PLL_SEL_CPLL = 0,
207 HCLK_PERILP1_PLL_SEL_GPLL = 1,
208 HCLK_PERILP1_DIV_CON_SHIFT = 0,
209 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
210
211 /* CLKSEL_CON26 */
212 CLK_SARADC_DIV_CON_SHIFT = 8,
364fc731
DW		 213 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
214 CLK_SARADC_DIV_CON_WIDTH = 8,
b0b3c865
KY		 215
216 /* CLKSEL_CON27 */
217 CLK_TSADC_SEL_X24M = 0x0,
218 CLK_TSADC_SEL_SHIFT = 15,
219 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
220 CLK_TSADC_DIV_CON_SHIFT = 0,
221 CLK_TSADC_DIV_CON_MASK = 0x3ff,
222
223 /* CLKSEL_CON47 & CLKSEL_CON48 */
224 ACLK_VOP_PLL_SEL_SHIFT = 6,
225 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
226 ACLK_VOP_PLL_SEL_CPLL = 0x1,
227 ACLK_VOP_DIV_CON_SHIFT = 0,
228 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
229
230 /* CLKSEL_CON49 & CLKSEL_CON50 */
231 DCLK_VOP_DCLK_SEL_SHIFT = 11,
232 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
233 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
234 DCLK_VOP_PLL_SEL_SHIFT = 8,
235 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
236 DCLK_VOP_PLL_SEL_VPLL = 0,
237 DCLK_VOP_DIV_CON_MASK = 0xff,
238 DCLK_VOP_DIV_CON_SHIFT = 0,
239
da0be4e1
JM		 240 /* CLKSEL_CON57 */
241 PCLK_ALIVE_DIV_CON_SHIFT = 0,
242 PCLK_ALIVE_DIV_CON_MASK = 0x1f << PCLK_ALIVE_DIV_CON_SHIFT,
243
b0b3c865 244 /* CLKSEL_CON58 */
8fa6979b
PT		 245 CLK_SPI_PLL_SEL_WIDTH = 1,
246 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
247 CLK_SPI_PLL_SEL_CPLL = 0,
248 CLK_SPI_PLL_SEL_GPLL = 1,
249 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
250 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
251
252 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
253 CLK_SPI5_PLL_SEL_SHIFT = 15,
b0b3c865
KY		 254
255 /* CLKSEL_CON59 */
256 CLK_SPI1_PLL_SEL_SHIFT = 15,
257 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
258 CLK_SPI0_PLL_SEL_SHIFT = 7,
259 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
260
261 /* CLKSEL_CON60 */
262 CLK_SPI4_PLL_SEL_SHIFT = 15,
263 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
264 CLK_SPI2_PLL_SEL_SHIFT = 7,
265 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
266
267 /* CLKSEL_CON61 */
268 CLK_I2C_PLL_SEL_MASK = 1,
269 CLK_I2C_PLL_SEL_CPLL = 0,
270 CLK_I2C_PLL_SEL_GPLL = 1,
271 CLK_I2C5_PLL_SEL_SHIFT = 15,
272 CLK_I2C5_DIV_CON_SHIFT = 8,
273 CLK_I2C1_PLL_SEL_SHIFT = 7,
274 CLK_I2C1_DIV_CON_SHIFT = 0,
275
276 /* CLKSEL_CON62 */
277 CLK_I2C6_PLL_SEL_SHIFT = 15,
278 CLK_I2C6_DIV_CON_SHIFT = 8,
279 CLK_I2C2_PLL_SEL_SHIFT = 7,
280 CLK_I2C2_DIV_CON_SHIFT = 0,
281
282 /* CLKSEL_CON63 */
283 CLK_I2C7_PLL_SEL_SHIFT = 15,
284 CLK_I2C7_DIV_CON_SHIFT = 8,
285 CLK_I2C3_PLL_SEL_SHIFT = 7,
286 CLK_I2C3_DIV_CON_SHIFT = 0,
287
288 /* CRU_SOFTRST_CON4 */
289 RESETN_DDR0_REQ_SHIFT = 8,
290 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
291 RESETN_DDRPHY0_REQ_SHIFT = 9,
292 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
293 RESETN_DDR1_REQ_SHIFT = 12,
294 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
295 RESETN_DDRPHY1_REQ_SHIFT = 13,
296 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
297};
298
299#define VCO_MAX_KHZ (3200 * (MHz / KHz))
300#define VCO_MIN_KHZ (800 * (MHz / KHz))
301#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
302#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
303
304/*
305 * the div restructions of pll in integer mode, these are defined in
306 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
307 */
308#define PLL_DIV_MIN 16
309#define PLL_DIV_MAX 3200
310
311/*
312 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
313 * Formulas also embedded within the Fractional PLL Verilog model:
314 * If DSMPD = 1 (DSM is disabled, "integer mode")
315 * FOUTVCO = FREF / REFDIV * FBDIV
316 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
317 * Where:
318 * FOUTVCO = Fractional PLL non-divided output frequency
319 * FOUTPOSTDIV = Fractional PLL divided output frequency
320 * (output of second post divider)
321 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
322 * REFDIV = Fractional PLL input reference clock divider
323 * FBDIV = Integer value programmed into feedback divide
324 *
325 */
326static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
327{
328 /* All 8 PLLs have same VCO and output frequency range restrictions. */
329 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
330 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
331
332 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
333 "postdiv2=%d, vco=%u khz, output=%u khz\n",
334 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
335 div->postdiv2, vco_khz, output_khz);
336 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
337 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
338 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
339
340 /*
341 * When power on or changing PLL setting,
342 * we must force PLL into slow mode to ensure output stable clock.
343 */
344 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
345 PLL_MODE_SLOW << PLL_MODE_SHIFT);
346
347 /* use integer mode */
348 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
349 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
350
351 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
352 div->fbdiv << PLL_FBDIV_SHIFT);
353 rk_clrsetreg(&pll_con[1],
354 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
355 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
356 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
357 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
358 (div->refdiv << PLL_REFDIV_SHIFT));
359
360 /* waiting for pll lock */
361 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
362 udelay(1);
363
364 /* pll enter normal mode */
365 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
366 PLL_MODE_NORM << PLL_MODE_SHIFT);
367}
368
369static int pll_para_config(u32 freq_hz, struct pll_div *div)
370{
371 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
372 u32 postdiv1, postdiv2 = 1;
373 u32 fref_khz;
374 u32 diff_khz, best_diff_khz;
375 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
376 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
377 u32 vco_khz;
378 u32 freq_khz = freq_hz / KHz;
379
380 if (!freq_hz) {
381 printf("%s: the frequency can't be 0 Hz\n", __func__);
382 return -1;
383 }
384
385 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
386 if (postdiv1 > max_postdiv1) {
387 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
388 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
389 }
390
391 vco_khz = freq_khz * postdiv1 * postdiv2;
392
393 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
394 postdiv2 > max_postdiv2) {
395 printf("%s: Cannot find out a supported VCO"
396 " for Frequency (%uHz).\n", __func__, freq_hz);
397 return -1;
398 }
399
400 div->postdiv1 = postdiv1;
401 div->postdiv2 = postdiv2;
402
403 best_diff_khz = vco_khz;
404 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
405 fref_khz = ref_khz / refdiv;
406
407 fbdiv = vco_khz / fref_khz;
dd7dfa21 408 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
b0b3c865
KY		 409 continue;
410 diff_khz = vco_khz - fbdiv * fref_khz;
411 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
412 fbdiv++;
413 diff_khz = fref_khz - diff_khz;
414 }
415
416 if (diff_khz >= best_diff_khz)
417 continue;
418
419 best_diff_khz = diff_khz;
420 div->refdiv = refdiv;
421 div->fbdiv = fbdiv;
422 }
423
dd7dfa21 424 if (best_diff_khz > 4 * (MHz / KHz)) {
b0b3c865
KY		 425 printf("%s: Failed to match output frequency %u, "
426 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
427 best_diff_khz * KHz);
428 return -1;
429 }
430 return 0;
431}
432
b52a199e 433void rk3399_configure_cpu_l(struct rockchip_cru *cru,
af765a49 434 enum apll_l_frequencies apll_l_freq)
b0b3c865
KY		 435{
436 u32 aclkm_div;
437 u32 pclk_dbg_div;
438 u32 atclk_div;
439
af765a49 440 /* Setup cluster L */
b0b3c865
KY		 441 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
442
af765a49
CM		 443 aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
444 assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
b0b3c865
KY		 445 aclkm_div < 0x1f);
446
af765a49
CM		 447 pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
448 assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
b0b3c865
KY		 449 pclk_dbg_div < 0x1f);
450
af765a49
CM		 451 atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
452 assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
b0b3c865
KY		 453 atclk_div < 0x1f);
454
455 rk_clrsetreg(&cru->clksel_con[0],
456 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
457 CLK_CORE_L_DIV_MASK,
458 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
459 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
460 0 << CLK_CORE_L_DIV_SHIFT);
461
462 rk_clrsetreg(&cru->clksel_con[1],
463 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
464 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
465 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
466}
af765a49 467
b52a199e 468void rk3399_configure_cpu_b(struct rockchip_cru *cru,
af765a49
CM		 469 enum apll_b_frequencies apll_b_freq)
470{
471 u32 aclkm_div;
472 u32 pclk_dbg_div;
473 u32 atclk_div;
474
475 /* Setup cluster B */
476 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
477
478 aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
479 assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
480 aclkm_div < 0x1f);
481
482 pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
483 assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
484 pclk_dbg_div < 0x1f);
485
486 atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
487 assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
488 atclk_div < 0x1f);
489
490 rk_clrsetreg(&cru->clksel_con[2],
491 ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
492 CLK_CORE_B_DIV_MASK,
493 aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
494 CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
495 0 << CLK_CORE_B_DIV_SHIFT);
496
497 rk_clrsetreg(&cru->clksel_con[3],
498 PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
499 pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
500 atclk_div << ATCLK_CORE_B_DIV_SHIFT);
501}
502
b0b3c865 503#define I2C_CLK_REG_MASK(bus) \
dd7dfa21
JT		 504 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
505 CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
b0b3c865
KY		 506
507#define I2C_CLK_REG_VALUE(bus, clk_div) \
dd7dfa21
JT		 508 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
509 CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
b0b3c865
KY		 510
511#define I2C_CLK_DIV_VALUE(con, bus) \
dd7dfa21 512 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
b0b3c865 513
5e79f443 514#define I2C_PMUCLK_REG_MASK(bus) \
dd7dfa21 515 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
5e79f443
KY		 516
517#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
dd7dfa21 518 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
5e79f443 519
b52a199e 520static ulong rk3399_i2c_get_clk(struct rockchip_cru *cru, ulong clk_id)
b0b3c865
KY		 521{
522 u32 div, con;
523
524 switch (clk_id) {
525 case SCLK_I2C1:
526 con = readl(&cru->clksel_con[61]);
527 div = I2C_CLK_DIV_VALUE(con, 1);
528 break;
529 case SCLK_I2C2:
530 con = readl(&cru->clksel_con[62]);
531 div = I2C_CLK_DIV_VALUE(con, 2);
532 break;
533 case SCLK_I2C3:
534 con = readl(&cru->clksel_con[63]);
535 div = I2C_CLK_DIV_VALUE(con, 3);
536 break;
537 case SCLK_I2C5:
538 con = readl(&cru->clksel_con[61]);
539 div = I2C_CLK_DIV_VALUE(con, 5);
540 break;
541 case SCLK_I2C6:
542 con = readl(&cru->clksel_con[62]);
543 div = I2C_CLK_DIV_VALUE(con, 6);
544 break;
545 case SCLK_I2C7:
546 con = readl(&cru->clksel_con[63]);
547 div = I2C_CLK_DIV_VALUE(con, 7);
548 break;
549 default:
550 printf("do not support this i2c bus\n");
551 return -EINVAL;
552 }
553
554 return DIV_TO_RATE(GPLL_HZ, div);
555}
556
b52a199e 557static ulong rk3399_i2c_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
b0b3c865
KY		 558{
559 int src_clk_div;
560
561 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
562 src_clk_div = GPLL_HZ / hz;
563 assert(src_clk_div - 1 < 127);
564
565 switch (clk_id) {
566 case SCLK_I2C1:
567 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
568 I2C_CLK_REG_VALUE(1, src_clk_div));
569 break;
570 case SCLK_I2C2:
571 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
572 I2C_CLK_REG_VALUE(2, src_clk_div));
573 break;
574 case SCLK_I2C3:
575 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
576 I2C_CLK_REG_VALUE(3, src_clk_div));
577 break;
578 case SCLK_I2C5:
579 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
580 I2C_CLK_REG_VALUE(5, src_clk_div));
581 break;
582 case SCLK_I2C6:
583 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
584 I2C_CLK_REG_VALUE(6, src_clk_div));
585 break;
586 case SCLK_I2C7:
587 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
588 I2C_CLK_REG_VALUE(7, src_clk_div));
589 break;
590 default:
591 printf("do not support this i2c bus\n");
592 return -EINVAL;
593 }
594
beb90a53 595 return rk3399_i2c_get_clk(cru, clk_id);
b0b3c865
KY		 596}
597
8fa6979b
PT		 598/*
599 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
600 * to select either CPLL or GPLL as the clock-parent. The location within
601 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
602 */
603
604struct spi_clkreg {
dd7dfa21
JT		 605 u8 reg; /* CLKSEL_CON[reg] register in CRU */
606 u8 div_shift;
607 u8 sel_shift;
8fa6979b
PT		 608};
609
610/*
611 * The entries are numbered relative to their offset from SCLK_SPI0.
612 *
613 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
614 * logic is not supported).
615 */
616static const struct spi_clkreg spi_clkregs[] = {
617 [0] = { .reg = 59,
618 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
619 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
620 [1] = { .reg = 59,
621 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
622 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
623 [2] = { .reg = 60,
624 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
625 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
626 [3] = { .reg = 60,
627 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
628 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
629 [4] = { .reg = 58,
630 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
631 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
632};
633
b52a199e 634static ulong rk3399_spi_get_clk(struct rockchip_cru *cru, ulong clk_id)
8fa6979b
PT		 635{
636 const struct spi_clkreg *spiclk = NULL;
637 u32 div, val;
638
639 switch (clk_id) {
640 case SCLK_SPI0 ... SCLK_SPI5:
641 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
642 break;
643
644 default:
9b643e31 645 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT		 646 return -EINVAL;
647 }
648
649 val = readl(&cru->clksel_con[spiclk->reg]);
a8ee98df
PT		 650 div = bitfield_extract(val, spiclk->div_shift,
651 CLK_SPI_PLL_DIV_CON_WIDTH);
8fa6979b
PT		 652
653 return DIV_TO_RATE(GPLL_HZ, div);
654}
655
b52a199e 656static ulong rk3399_spi_set_clk(struct rockchip_cru *cru, ulong clk_id, uint hz)
8fa6979b
PT		 657{
658 const struct spi_clkreg *spiclk = NULL;
659 int src_clk_div;
660
217273cd
KY		 661 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
662 assert(src_clk_div < 128);
8fa6979b
PT		 663
664 switch (clk_id) {
665 case SCLK_SPI1 ... SCLK_SPI5:
666 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
667 break;
668
669 default:
9b643e31 670 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT		 671 return -EINVAL;
672 }
673
674 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
675 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
676 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
677 ((src_clk_div << spiclk->div_shift) |
678 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
679
beb90a53 680 return rk3399_spi_get_clk(cru, clk_id);
8fa6979b
PT		 681}
682
b52a199e 683static ulong rk3399_vop_set_clk(struct rockchip_cru *cru, ulong clk_id, u32 hz)
b0b3c865
KY		 684{
685 struct pll_div vpll_config = {0};
dd7dfa21 686 int aclk_vop = 198 * MHz;
b0b3c865
KY		 687 void *aclkreg_addr, *dclkreg_addr;
688 u32 div;
689
690 switch (clk_id) {
691 case DCLK_VOP0:
692 aclkreg_addr = &cru->clksel_con[47];
693 dclkreg_addr = &cru->clksel_con[49];
694 break;
695 case DCLK_VOP1:
696 aclkreg_addr = &cru->clksel_con[48];
697 dclkreg_addr = &cru->clksel_con[50];
698 break;
699 default:
700 return -EINVAL;
701 }
702 /* vop aclk source clk: cpll */
703 div = CPLL_HZ / aclk_vop;
704 assert(div - 1 < 32);
705
706 rk_clrsetreg(aclkreg_addr,
707 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
708 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
709 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
710
711 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
712 if (pll_para_config(hz, &vpll_config))
713 return -1;
714
715 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
716
717 rk_clrsetreg(dclkreg_addr,
dd7dfa21 718 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
b0b3c865
KY		 719 DCLK_VOP_DIV_CON_MASK,
720 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
721 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
722 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
723
724 return hz;
725}
726
b52a199e 727static ulong rk3399_mmc_get_clk(struct rockchip_cru *cru, uint clk_id)
b0b3c865
KY		 728{
729 u32 div, con;
730
731 switch (clk_id) {
f103c112
MS		 732 case HCLK_SDIO:
733 case SCLK_SDIO:
734 con = readl(&cru->clksel_con[15]);
735 /* dwmmc controller have internal div 2 */
736 div = 2;
737 break;
998c61ae 738 case HCLK_SDMMC:
b0b3c865
KY		 739 case SCLK_SDMMC:
740 con = readl(&cru->clksel_con[16]);
3a94d75d
KY		 741 /* dwmmc controller have internal div 2 */
742 div = 2;
b0b3c865
KY		 743 break;
744 case SCLK_EMMC:
4648108c 745 con = readl(&cru->clksel_con[22]);
3a94d75d 746 div = 1;
b0b3c865
KY		 747 break;
748 default:
749 return -EINVAL;
750 }
b0b3c865 751
3a94d75d 752 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
fd4b2dc0
KY		 753 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
754 == CLK_EMMC_PLL_SEL_24M)
3a94d75d 755 return DIV_TO_RATE(OSC_HZ, div);
fd4b2dc0
KY		 756 else
757 return DIV_TO_RATE(GPLL_HZ, div);
b0b3c865
KY		 758}
759
f103c112
MS		 760static void rk3399_dwmmc_set_clk(struct rockchip_cru *cru,
761 unsigned int con, ulong set_rate)
762{
763 /* Select clk_sdmmc source from GPLL by default */
764 /* mmc clock defaulg div 2 internal, provide double in cru */
765 int src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
766
767 if (src_clk_div > 128) {
768 /* use 24MHz source for 400KHz clock */
769 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
770 assert(src_clk_div - 1 < 128);
771 rk_clrsetreg(&cru->clksel_con[con],
772 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
773 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
774 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
775 } else {
776 rk_clrsetreg(&cru->clksel_con[con],
777 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
778 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
779 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
780 }
781}
782
b52a199e 783static ulong rk3399_mmc_set_clk(struct rockchip_cru *cru,
b0b3c865
KY		 784 ulong clk_id, ulong set_rate)
785{
b0b3c865 786 switch (clk_id) {
f103c112
MS		 787 case HCLK_SDIO:
788 case SCLK_SDIO:
789 rk3399_dwmmc_set_clk(cru, 15, set_rate);
790 break;
998c61ae 791 case HCLK_SDMMC:
b0b3c865 792 case SCLK_SDMMC:
f103c112 793 rk3399_dwmmc_set_clk(cru, 16, set_rate);
b0b3c865 794 break;
f103c112
MS		 795 case SCLK_EMMC: {
796 int aclk_emmc = 198 * MHz;
b0b3c865 797 /* Select aclk_emmc source from GPLL */
f103c112
MS		 798 int src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
799
217273cd 800 assert(src_clk_div - 1 < 32);
b0b3c865
KY		 801
802 rk_clrsetreg(&cru->clksel_con[21],
803 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
804 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
805 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
806
807 /* Select clk_emmc source from GPLL too */
217273cd
KY		 808 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
809 assert(src_clk_div - 1 < 128);
b0b3c865
KY		 810
811 rk_clrsetreg(&cru->clksel_con[22],
812 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
813 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
814 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
815 break;
f103c112 816 }
b0b3c865
KY		 817 default:
818 return -EINVAL;
819 }
820 return rk3399_mmc_get_clk(cru, clk_id);
821}
822
b52a199e 823static ulong rk3399_gmac_set_clk(struct rockchip_cru *cru, ulong rate)
a45f17e8
PT		 824{
825 ulong ret;
826
827 /*
828 * The RGMII CLK can be derived either from an external "clkin"
829 * or can be generated from internally by a divider from SCLK_MAC.
830 */
831 if (readl(&cru->clksel_con[19]) & BIT(4)) {
832 /* An external clock will always generate the right rate... */
833 ret = rate;
834 } else {
835 /*
836 * No platform uses an internal clock to date.
837 * Implement this once it becomes necessary and print an error
838 * if someone tries to use it (while it remains unimplemented).
839 */
840 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
841 ret = 0;
842 }
843
844 return ret;
845}
846
5ae2fd97 847#define PMUSGRF_DDR_RGN_CON16 0xff330040
b52a199e 848static ulong rk3399_ddr_set_clk(struct rockchip_cru *cru,
5ae2fd97
KY		 849 ulong set_rate)
850{
851 struct pll_div dpll_cfg;
852
853 /* IC ECO bug, need to set this register */
854 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
855
856 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
857 switch (set_rate) {
09565686
JT		 858 case 50 * MHz:
859 dpll_cfg = (struct pll_div)
2cb23b80 860 {.refdiv = 2, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 6};
09565686 861 break;
dd7dfa21 862 case 200 * MHz:
5ae2fd97
KY		 863 dpll_cfg = (struct pll_div)
864 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
865 break;
dd7dfa21 866 case 300 * MHz:
5ae2fd97
KY		 867 dpll_cfg = (struct pll_div)
868 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
869 break;
f556d75a
JT		 870 case 400 * MHz:
871 dpll_cfg = (struct pll_div)
872 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
873 break;
dd7dfa21 874 case 666 * MHz:
5ae2fd97
KY		 875 dpll_cfg = (struct pll_div)
876 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
877 break;
dd7dfa21 878 case 800 * MHz:
5ae2fd97
KY		 879 dpll_cfg = (struct pll_div)
880 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
881 break;
dd7dfa21 882 case 933 * MHz:
5ae2fd97
KY		 883 dpll_cfg = (struct pll_div)
884 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
885 break;
886 default:
9b643e31 887 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
5ae2fd97
KY		 888 }
889 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
890
891 return set_rate;
892}
364fc731 893
da0be4e1
JM		 894static ulong rk3399_alive_get_clk(struct rockchip_cru *cru)
895{
896 u32 div, val;
897
898 val = readl(&cru->clksel_con[57]);
899 div = (val & PCLK_ALIVE_DIV_CON_MASK) >>
900 PCLK_ALIVE_DIV_CON_SHIFT;
901
902 return DIV_TO_RATE(GPLL_HZ, div);
903}
904
b52a199e 905static ulong rk3399_saradc_get_clk(struct rockchip_cru *cru)
364fc731
DW		 906{
907 u32 div, val;
908
909 val = readl(&cru->clksel_con[26]);
910 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
911 CLK_SARADC_DIV_CON_WIDTH);
912
913 return DIV_TO_RATE(OSC_HZ, div);
914}
915
b52a199e 916static ulong rk3399_saradc_set_clk(struct rockchip_cru *cru, uint hz)
364fc731
DW		 917{
918 int src_clk_div;
919
920 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
921 assert(src_clk_div < 128);
922
923 rk_clrsetreg(&cru->clksel_con[26],
924 CLK_SARADC_DIV_CON_MASK,
925 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
926
927 return rk3399_saradc_get_clk(cru);
928}
929
b0b3c865
KY		 930static ulong rk3399_clk_get_rate(struct clk *clk)
931{
932 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
933 ulong rate = 0;
934
935 switch (clk->id) {
936 case 0 ... 63:
937 return 0;
f103c112
MS		 938 case HCLK_SDIO:
939 case SCLK_SDIO:
998c61ae 940 case HCLK_SDMMC:
b0b3c865
KY		 941 case SCLK_SDMMC:
942 case SCLK_EMMC:
943 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
944 break;
945 case SCLK_I2C1:
946 case SCLK_I2C2:
947 case SCLK_I2C3:
948 case SCLK_I2C5:
949 case SCLK_I2C6:
950 case SCLK_I2C7:
951 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
952 break;
8fa6979b
PT		 953 case SCLK_SPI0...SCLK_SPI5:
954 rate = rk3399_spi_get_clk(priv->cru, clk->id);
955 break;
956 case SCLK_UART0:
24615436 957 case SCLK_UART1:
8fa6979b 958 case SCLK_UART2:
24615436 959 case SCLK_UART3:
8fa6979b 960 return 24000000;
ffc1fac5
PT		 961 case PCLK_HDMI_CTRL:
962 break;
b0b3c865
KY		 963 case DCLK_VOP0:
964 case DCLK_VOP1:
965 break;
a70feb46
PT		 966 case PCLK_EFUSE1024NS:
967 break;
364fc731
DW		 968 case SCLK_SARADC:
969 rate = rk3399_saradc_get_clk(priv->cru);
970 break;
5328af17
SG		 971 case ACLK_VIO:
972 case ACLK_HDCP:
973 case ACLK_GIC_PRE:
974 case PCLK_DDR:
975 break;
da0be4e1
JM		 976 case PCLK_ALIVE:
977 case PCLK_WDT:
978 rate = rk3399_alive_get_clk(priv->cru);
979 break;
b0b3c865 980 default:
5328af17 981 log_debug("Unknown clock %lu\n", clk->id);
b0b3c865
KY		 982 return -ENOENT;
983 }
984
985 return rate;
986}
987
988static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
989{
990 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
991 ulong ret = 0;
992
993 switch (clk->id) {
994 case 0 ... 63:
995 return 0;
d2f1f1ab
PT		 996
997 case ACLK_PERIHP:
998 case HCLK_PERIHP:
999 case PCLK_PERIHP:
1000 return 0;
1001
1002 case ACLK_PERILP0:
1003 case HCLK_PERILP0:
1004 case PCLK_PERILP0:
1005 return 0;
1006
1007 case ACLK_CCI:
1008 return 0;
1009
1010 case HCLK_PERILP1:
1011 case PCLK_PERILP1:
1012 return 0;
1013
f103c112
MS		 1014 case HCLK_SDIO:
1015 case SCLK_SDIO:
998c61ae 1016 case HCLK_SDMMC:
b0b3c865
KY		 1017 case SCLK_SDMMC:
1018 case SCLK_EMMC:
1019 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
1020 break;
65d83303 1021 case SCLK_MAC:
a45f17e8 1022 ret = rk3399_gmac_set_clk(priv->cru, rate);
65d83303 1023 break;
b0b3c865
KY		 1024 case SCLK_I2C1:
1025 case SCLK_I2C2:
1026 case SCLK_I2C3:
1027 case SCLK_I2C5:
1028 case SCLK_I2C6:
1029 case SCLK_I2C7:
1030 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
1031 break;
8fa6979b
PT		 1032 case SCLK_SPI0...SCLK_SPI5:
1033 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
1034 break;
ffc1fac5
PT		 1035 case PCLK_HDMI_CTRL:
1036 case PCLK_VIO_GRF:
1037 /* the PCLK gates for video are enabled by default */
1038 break;
b0b3c865
KY		 1039 case DCLK_VOP0:
1040 case DCLK_VOP1:
5e79f443 1041 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
b0b3c865 1042 break;
b1bcd616
JT		 1043 case ACLK_VOP1:
1044 case HCLK_VOP1:
96993d7c 1045 case HCLK_SD:
80e19111
JT		 1046 case SCLK_UPHY0_TCPDCORE:
1047 case SCLK_UPHY1_TCPDCORE:
b1bcd616
JT		 1048 /**
1049 * assigned-clocks handling won't require for vopl, so
1050 * return 0 to satisfy clk_set_defaults during device probe.
1051 */
1052 return 0;
5ae2fd97
KY		 1053 case SCLK_DDRCLK:
1054 ret = rk3399_ddr_set_clk(priv->cru, rate);
1055 break;
a70feb46
PT		 1056 case PCLK_EFUSE1024NS:
1057 break;
364fc731
DW		 1058 case SCLK_SARADC:
1059 ret = rk3399_saradc_set_clk(priv->cru, rate);
1060 break;
5328af17
SG		 1061 case ACLK_VIO:
1062 case ACLK_HDCP:
1063 case ACLK_GIC_PRE:
1064 case PCLK_DDR:
1065 return 0;
b0b3c865 1066 default:
5328af17 1067 log_debug("Unknown clock %lu\n", clk->id);
b0b3c865
KY		 1068 return -ENOENT;
1069 }
1070
1071 return ret;
1072}
1073
dd7dfa21
JT		 1074static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1075 struct clk *parent)
a45f17e8
PT		 1076{
1077 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1078 const char *clock_output_name;
1079 int ret;
1080
1081 /*
1082 * If the requested parent is in the same clock-controller and
1083 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1084 */
dd7dfa21 1085 if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
a45f17e8
PT		 1086 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1087 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1088 return 0;
1089 }
1090
1091 /*
1092 * Otherwise, we need to check the clock-output-names of the
1093 * requested parent to see if the requested id is "clkin_gmac".
1094 */
1095 ret = dev_read_string_index(parent->dev, "clock-output-names",
1096 parent->id, &clock_output_name);
1097 if (ret < 0)
1098 return -ENODATA;
1099
1100 /* If this is "clkin_gmac", switch to the external clock input */
1101 if (!strcmp(clock_output_name, "clkin_gmac")) {
1102 debug("%s: switching RGMII to CLKIN\n", __func__);
1103 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1104 return 0;
1105 }
1106
1107 return -EINVAL;
1108}
1109
dd7dfa21
JT		 1110static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1111 struct clk *parent)
a45f17e8
PT		 1112{
1113 switch (clk->id) {
1114 case SCLK_RMII_SRC:
1115 return rk3399_gmac_set_parent(clk, parent);
1116 }
1117
1118 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1119 return -ENOENT;
1120}
1121
30d09a2f
JT		 1122static int rk3399_clk_enable(struct clk *clk)
1123{
1124 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1125
1126 switch (clk->id) {
1127 case SCLK_MAC:
1128 rk_clrreg(&priv->cru->clkgate_con[5], BIT(5));
1129 break;
1130 case SCLK_MAC_RX:
1131 rk_clrreg(&priv->cru->clkgate_con[5], BIT(8));
1132 break;
1133 case SCLK_MAC_TX:
1134 rk_clrreg(&priv->cru->clkgate_con[5], BIT(9));
1135 break;
1136 case SCLK_MACREF:
1137 rk_clrreg(&priv->cru->clkgate_con[5], BIT(7));
1138 break;
1139 case SCLK_MACREF_OUT:
1140 rk_clrreg(&priv->cru->clkgate_con[5], BIT(6));
1141 break;
f7dd12a7
JT		 1142 case SCLK_USB2PHY0_REF:
1143 rk_clrreg(&priv->cru->clkgate_con[6], BIT(5));
1144 break;
1145 case SCLK_USB2PHY1_REF:
1146 rk_clrreg(&priv->cru->clkgate_con[6], BIT(6));
1147 break;
30d09a2f
JT		 1148 case ACLK_GMAC:
1149 rk_clrreg(&priv->cru->clkgate_con[32], BIT(0));
1150 break;
1151 case PCLK_GMAC:
1152 rk_clrreg(&priv->cru->clkgate_con[32], BIT(2));
1153 break;
1154 case SCLK_USB3OTG0_REF:
1155 rk_clrreg(&priv->cru->clkgate_con[12], BIT(1));
1156 break;
1157 case SCLK_USB3OTG1_REF:
1158 rk_clrreg(&priv->cru->clkgate_con[12], BIT(2));
1159 break;
1160 case SCLK_USB3OTG0_SUSPEND:
1161 rk_clrreg(&priv->cru->clkgate_con[12], BIT(3));
1162 break;
1163 case SCLK_USB3OTG1_SUSPEND:
1164 rk_clrreg(&priv->cru->clkgate_con[12], BIT(4));
1165 break;
1166 case ACLK_USB3OTG0:
1167 rk_clrreg(&priv->cru->clkgate_con[30], BIT(1));
1168 break;
1169 case ACLK_USB3OTG1:
1170 rk_clrreg(&priv->cru->clkgate_con[30], BIT(2));
1171 break;
1172 case ACLK_USB3_RKSOC_AXI_PERF:
1173 rk_clrreg(&priv->cru->clkgate_con[30], BIT(3));
1174 break;
1175 case ACLK_USB3:
1176 rk_clrreg(&priv->cru->clkgate_con[12], BIT(0));
1177 break;
1178 case ACLK_USB3_GRF:
1179 rk_clrreg(&priv->cru->clkgate_con[30], BIT(4));
1180 break;
1181 case HCLK_HOST0:
1182 rk_clrreg(&priv->cru->clksel_con[20], BIT(5));
1183 break;
1184 case HCLK_HOST0_ARB:
1185 rk_clrreg(&priv->cru->clksel_con[20], BIT(6));
1186 break;
1187 case HCLK_HOST1:
1188 rk_clrreg(&priv->cru->clksel_con[20], BIT(7));
1189 break;
1190 case HCLK_HOST1_ARB:
1191 rk_clrreg(&priv->cru->clksel_con[20], BIT(8));
1192 break;
e1b413d1
JT		 1193 case SCLK_UPHY0_TCPDPHY_REF:
1194 rk_clrreg(&priv->cru->clkgate_con[13], BIT(4));
1195 break;
1196 case SCLK_UPHY0_TCPDCORE:
1197 rk_clrreg(&priv->cru->clkgate_con[13], BIT(5));
1198 break;
1199 case SCLK_UPHY1_TCPDPHY_REF:
1200 rk_clrreg(&priv->cru->clkgate_con[13], BIT(6));
1201 break;
1202 case SCLK_UPHY1_TCPDCORE:
1203 rk_clrreg(&priv->cru->clkgate_con[13], BIT(7));
1204 break;
912f633d
JT		 1205 case SCLK_PCIEPHY_REF:
1206 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1207 break;
30d09a2f
JT		 1208 default:
1209 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1210 return -ENOENT;
1211 }
1212
1213 return 0;
1214}
1215
1216static int rk3399_clk_disable(struct clk *clk)
1217{
1218 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1219
1220 switch (clk->id) {
1221 case SCLK_MAC:
1222 rk_setreg(&priv->cru->clkgate_con[5], BIT(5));
1223 break;
1224 case SCLK_MAC_RX:
1225 rk_setreg(&priv->cru->clkgate_con[5], BIT(8));
1226 break;
1227 case SCLK_MAC_TX:
1228 rk_setreg(&priv->cru->clkgate_con[5], BIT(9));
1229 break;
1230 case SCLK_MACREF:
1231 rk_setreg(&priv->cru->clkgate_con[5], BIT(7));
1232 break;
1233 case SCLK_MACREF_OUT:
1234 rk_setreg(&priv->cru->clkgate_con[5], BIT(6));
1235 break;
f7dd12a7
JT		 1236 case SCLK_USB2PHY0_REF:
1237 rk_setreg(&priv->cru->clkgate_con[6], BIT(5));
1238 break;
1239 case SCLK_USB2PHY1_REF:
1240 rk_setreg(&priv->cru->clkgate_con[6], BIT(6));
1241 break;
30d09a2f
JT		 1242 case ACLK_GMAC:
1243 rk_setreg(&priv->cru->clkgate_con[32], BIT(0));
1244 break;
1245 case PCLK_GMAC:
1246 rk_setreg(&priv->cru->clkgate_con[32], BIT(2));
1247 break;
1248 case SCLK_USB3OTG0_REF:
1249 rk_setreg(&priv->cru->clkgate_con[12], BIT(1));
1250 break;
1251 case SCLK_USB3OTG1_REF:
1252 rk_setreg(&priv->cru->clkgate_con[12], BIT(2));
1253 break;
1254 case SCLK_USB3OTG0_SUSPEND:
1255 rk_setreg(&priv->cru->clkgate_con[12], BIT(3));
1256 break;
1257 case SCLK_USB3OTG1_SUSPEND:
1258 rk_setreg(&priv->cru->clkgate_con[12], BIT(4));
1259 break;
1260 case ACLK_USB3OTG0:
1261 rk_setreg(&priv->cru->clkgate_con[30], BIT(1));
1262 break;
1263 case ACLK_USB3OTG1:
1264 rk_setreg(&priv->cru->clkgate_con[30], BIT(2));
1265 break;
1266 case ACLK_USB3_RKSOC_AXI_PERF:
1267 rk_setreg(&priv->cru->clkgate_con[30], BIT(3));
1268 break;
1269 case ACLK_USB3:
1270 rk_setreg(&priv->cru->clkgate_con[12], BIT(0));
1271 break;
1272 case ACLK_USB3_GRF:
1273 rk_setreg(&priv->cru->clkgate_con[30], BIT(4));
1274 break;
1275 case HCLK_HOST0:
1276 rk_setreg(&priv->cru->clksel_con[20], BIT(5));
1277 break;
1278 case HCLK_HOST0_ARB:
1279 rk_setreg(&priv->cru->clksel_con[20], BIT(6));
1280 break;
1281 case HCLK_HOST1:
1282 rk_setreg(&priv->cru->clksel_con[20], BIT(7));
1283 break;
1284 case HCLK_HOST1_ARB:
1285 rk_setreg(&priv->cru->clksel_con[20], BIT(8));
1286 break;
e1b413d1
JT		 1287 case SCLK_UPHY0_TCPDPHY_REF:
1288 rk_setreg(&priv->cru->clkgate_con[13], BIT(4));
1289 break;
1290 case SCLK_UPHY0_TCPDCORE:
1291 rk_setreg(&priv->cru->clkgate_con[13], BIT(5));
1292 break;
1293 case SCLK_UPHY1_TCPDPHY_REF:
1294 rk_setreg(&priv->cru->clkgate_con[13], BIT(6));
1295 break;
1296 case SCLK_UPHY1_TCPDCORE:
1297 rk_setreg(&priv->cru->clkgate_con[13], BIT(7));
1298 break;
912f633d
JT		 1299 case SCLK_PCIEPHY_REF:
1300 rk_clrreg(&priv->cru->clksel_con[18], BIT(10));
1301 break;
30d09a2f
JT		 1302 default:
1303 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1304 return -ENOENT;
1305 }
1306
1307 return 0;
1308}
1309
b0b3c865
KY		 1310static struct clk_ops rk3399_clk_ops = {
1311 .get_rate = rk3399_clk_get_rate,
1312 .set_rate = rk3399_clk_set_rate,
414cc151 1313#if CONFIG_IS_ENABLED(OF_REAL)
a45f17e8 1314 .set_parent = rk3399_clk_set_parent,
75b381aa 1315#endif
30d09a2f
JT		 1316 .enable = rk3399_clk_enable,
1317 .disable = rk3399_clk_disable,
b0b3c865
KY		 1318};
1319
b52a199e 1320static void rkclk_init(struct rockchip_cru *cru)
9f636a24
KY		 1321{
1322 u32 aclk_div;
1323 u32 hclk_div;
1324 u32 pclk_div;
1325
af765a49
CM		 1326 rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1327 rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
9f636a24
KY		 1328 /*
1329 * some cru registers changed by bootrom, we'd better reset them to
1330 * reset/default values described in TRM to avoid confusion in kernel.
1331 * Please consider these three lines as a fix of bootrom bug.
1332 */
1333 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1334 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1335 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1336
1337 /* configure gpll cpll */
1338 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1339 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1340
1341 /* configure perihp aclk, hclk, pclk */
1342 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1343 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1344
1345 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1346 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1347 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1348
1349 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1350 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1351 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1352
1353 rk_clrsetreg(&cru->clksel_con[14],
1354 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1355 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1356 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1357 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1358 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1359 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1360
1361 /* configure perilp0 aclk, hclk, pclk */
1362 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1363 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1364
1365 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1366 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1367 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1368
1369 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1370 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1371 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1372
1373 rk_clrsetreg(&cru->clksel_con[23],
1374 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1375 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1376 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1377 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1378 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1379 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1380
1381 /* perilp1 hclk select gpll as source */
1382 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1383 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1384 GPLL_HZ && (hclk_div < 0x1f));
1385
1386 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1387 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1388 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1389
1390 rk_clrsetreg(&cru->clksel_con[25],
1391 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1392 HCLK_PERILP1_PLL_SEL_MASK,
1393 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1394 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1395 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1396}
9f636a24 1397
b0b3c865
KY		 1398static int rk3399_clk_probe(struct udevice *dev)
1399{
1400 struct rk3399_clk_priv *priv = dev_get_priv(dev);
eb890250 1401 bool init_clocks = false;
b0b3c865 1402
5ae2fd97 1403#if CONFIG_IS_ENABLED(OF_PLATDATA)
c69cda25 1404 struct rk3399_clk_plat *plat = dev_get_plat(dev);
b0b3c865 1405
c20ee0ed 1406 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
5ae2fd97 1407#endif
eb890250
ANY		 1408
1409#if defined(CONFIG_SPL_BUILD)
1410 init_clocks = true;
1411#elif CONFIG_IS_ENABLED(HANDOFF)
1412 if (!(gd->flags & GD_FLG_RELOC)) {
1413 if (!(gd->spl_handoff))
1414 init_clocks = true;
1415 }
5ae2fd97 1416#endif
eb890250
ANY		 1417
1418 if (init_clocks)
1419 rkclk_init(priv->cru);
1420
b0b3c865
KY		 1421 return 0;
1422}
1423
d1998a9f 1424static int rk3399_clk_of_to_plat(struct udevice *dev)
b0b3c865 1425{
dcfc42b1
SG		 1426 if (CONFIG_IS_ENABLED(OF_REAL)) {
1427 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1428
1429 priv->cru = dev_read_addr_ptr(dev);
1430 }
b0b3c865 1431
b0b3c865
KY		 1432 return 0;
1433}
1434
1435static int rk3399_clk_bind(struct udevice *dev)
1436{
1437 int ret;
f24e36da
KY		 1438 struct udevice *sys_child;
1439 struct sysreset_reg *priv;
b0b3c865
KY		 1440
1441 /* The reset driver does not have a device node, so bind it here */
f24e36da
KY		 1442 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1443 &sys_child);
1444 if (ret) {
1445 debug("Warning: No sysreset driver: ret=%d\n", ret);
1446 } else {
1447 priv = malloc(sizeof(struct sysreset_reg));
b52a199e 1448 priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
f24e36da 1449 glb_srst_fst_value);
b52a199e 1450 priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
f24e36da 1451 glb_srst_snd_value);
0fd3d911 1452 dev_set_priv(sys_child, priv);
f24e36da 1453 }
b0b3c865 1454
a5ada25e 1455#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
b52a199e 1456 ret = offsetof(struct rockchip_cru, softrst_con[0]);
538f67c3
EZ		 1457 ret = rockchip_reset_bind(dev, ret, 21);
1458 if (ret)
30850b69 1459 debug("Warning: software reset driver bind failed\n");
538f67c3
EZ		 1460#endif
1461
b0b3c865
KY		 1462 return 0;
1463}
1464
1465static const struct udevice_id rk3399_clk_ids[] = {
1466 { .compatible = "rockchip,rk3399-cru" },
1467 { }
1468};
1469
1470U_BOOT_DRIVER(clk_rk3399) = {
5ae2fd97 1471 .name = "rockchip_rk3399_cru",
b0b3c865
KY		 1472 .id = UCLASS_CLK,
1473 .of_match = rk3399_clk_ids,
41575d8e 1474 .priv_auto = sizeof(struct rk3399_clk_priv),
d1998a9f 1475 .of_to_plat = rk3399_clk_of_to_plat,
b0b3c865
KY		 1476 .ops = &rk3399_clk_ops,
1477 .bind = rk3399_clk_bind,
1478 .probe = rk3399_clk_probe,
5ae2fd97 1479#if CONFIG_IS_ENABLED(OF_PLATDATA)
caa4daa2 1480 .plat_auto = sizeof(struct rk3399_clk_plat),
5ae2fd97 1481#endif
b0b3c865 1482};
5e79f443
KY		 1483
1484static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1485{
1486 u32 div, con;
1487
1488 switch (clk_id) {
1489 case SCLK_I2C0_PMU:
1490 con = readl(&pmucru->pmucru_clksel[2]);
1491 div = I2C_CLK_DIV_VALUE(con, 0);
1492 break;
1493 case SCLK_I2C4_PMU:
1494 con = readl(&pmucru->pmucru_clksel[3]);
1495 div = I2C_CLK_DIV_VALUE(con, 4);
1496 break;
1497 case SCLK_I2C8_PMU:
1498 con = readl(&pmucru->pmucru_clksel[2]);
1499 div = I2C_CLK_DIV_VALUE(con, 8);
1500 break;
1501 default:
1502 printf("do not support this i2c bus\n");
1503 return -EINVAL;
1504 }
1505
1506 return DIV_TO_RATE(PPLL_HZ, div);
1507}
1508
1509static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1510 uint hz)
1511{
1512 int src_clk_div;
1513
1514 src_clk_div = PPLL_HZ / hz;
1515 assert(src_clk_div - 1 < 127);
1516
1517 switch (clk_id) {
1518 case SCLK_I2C0_PMU:
1519 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1520 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1521 break;
1522 case SCLK_I2C4_PMU:
1523 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1524 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1525 break;
1526 case SCLK_I2C8_PMU:
1527 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1528 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1529 break;
1530 default:
1531 printf("do not support this i2c bus\n");
1532 return -EINVAL;
1533 }
1534
1535 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1536}
1537
1538static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1539{
1540 u32 div, con;
1541
1542 /* PWM closk rate is same as pclk_pmu */
1543 con = readl(&pmucru->pmucru_clksel[0]);
1544 div = con & PMU_PCLK_DIV_CON_MASK;
1545
1546 return DIV_TO_RATE(PPLL_HZ, div);
1547}
1548
1549static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1550{
1551 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1552 ulong rate = 0;
1553
1554 switch (clk->id) {
434d5a00
PT		 1555 case PLL_PPLL:
1556 return PPLL_HZ;
5e79f443 1557 case PCLK_RKPWM_PMU:
da0be4e1 1558 case PCLK_WDT_M0_PMU:
5e79f443
KY		 1559 rate = rk3399_pwm_get_clk(priv->pmucru);
1560 break;
1561 case SCLK_I2C0_PMU:
1562 case SCLK_I2C4_PMU:
1563 case SCLK_I2C8_PMU:
1564 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1565 break;
1566 default:
1567 return -ENOENT;
1568 }
1569
1570 return rate;
1571}
1572
1573static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1574{
1575 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1576 ulong ret = 0;
1577
1578 switch (clk->id) {
434d5a00
PT		 1579 case PLL_PPLL:
1580 /*
1581 * This has already been set up and we don't want/need
1582 * to change it here. Accept the request though, as the
1583 * device-tree has this in an 'assigned-clocks' list.
1584 */
1585 return PPLL_HZ;
5e79f443
KY		 1586 case SCLK_I2C0_PMU:
1587 case SCLK_I2C4_PMU:
1588 case SCLK_I2C8_PMU:
1589 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1590 break;
1591 default:
1592 return -ENOENT;
1593 }
1594
1595 return ret;
1596}
1597
1598static struct clk_ops rk3399_pmuclk_ops = {
1599 .get_rate = rk3399_pmuclk_get_rate,
1600 .set_rate = rk3399_pmuclk_set_rate,
1601};
1602
5ae2fd97 1603#ifndef CONFIG_SPL_BUILD
5e79f443
KY		 1604static void pmuclk_init(struct rk3399_pmucru *pmucru)
1605{
1606 u32 pclk_div;
1607
1608 /* configure pmu pll(ppll) */
1609 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1610
1611 /* configure pmu pclk */
1612 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
5e79f443
KY		 1613 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1614 PMU_PCLK_DIV_CON_MASK,
1615 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1616}
5ae2fd97 1617#endif
5e79f443
KY		 1618
1619static int rk3399_pmuclk_probe(struct udevice *dev)
1620{
61dff33b 1621#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
5e79f443 1622 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
61dff33b 1623#endif
5e79f443 1624
5ae2fd97 1625#if CONFIG_IS_ENABLED(OF_PLATDATA)
c69cda25 1626 struct rk3399_pmuclk_plat *plat = dev_get_plat(dev);
5ae2fd97 1627
c20ee0ed 1628 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
5ae2fd97 1629#endif
5e79f443 1630
5ae2fd97
KY		 1631#ifndef CONFIG_SPL_BUILD
1632 pmuclk_init(priv->pmucru);
1633#endif
5e79f443
KY		 1634 return 0;
1635}
1636
d1998a9f 1637static int rk3399_pmuclk_of_to_plat(struct udevice *dev)
5e79f443 1638{
dcfc42b1
SG		 1639 if (CONFIG_IS_ENABLED(OF_REAL)) {
1640 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1641
1642 priv->pmucru = dev_read_addr_ptr(dev);
1643 }
5e79f443 1644
5e79f443
KY		 1645 return 0;
1646}
1647
538f67c3
EZ		 1648static int rk3399_pmuclk_bind(struct udevice *dev)
1649{
957a3e54 1650#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
538f67c3
EZ		 1651 int ret;
1652
1653 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1654 ret = rockchip_reset_bind(dev, ret, 2);
1655 if (ret)
30850b69 1656 debug("Warning: software reset driver bind failed\n");
538f67c3
EZ		 1657#endif
1658 return 0;
1659}
1660
5e79f443
KY		 1661static const struct udevice_id rk3399_pmuclk_ids[] = {
1662 { .compatible = "rockchip,rk3399-pmucru" },
1663 { }
1664};
1665
c8a6bc96 1666U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
5ae2fd97 1667 .name = "rockchip_rk3399_pmucru",
5e79f443
KY		 1668 .id = UCLASS_CLK,
1669 .of_match = rk3399_pmuclk_ids,
41575d8e 1670 .priv_auto = sizeof(struct rk3399_pmuclk_priv),
d1998a9f 1671 .of_to_plat = rk3399_pmuclk_of_to_plat,
5e79f443
KY		 1672 .ops = &rk3399_pmuclk_ops,
1673 .probe = rk3399_pmuclk_probe,
538f67c3 1674 .bind = rk3399_pmuclk_bind,
5ae2fd97 1675#if CONFIG_IS_ENABLED(OF_PLATDATA)
caa4daa2 1676 .plat_auto = sizeof(struct rk3399_pmuclk_plat),
5ae2fd97 1677#endif
5e79f443 1678};
Empty description
This page took 0.499376 seconds and 4 git commands to generate.