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clk: rockchip: rk3399: Set 50MHz ddr clock
[J-u-boot.git] / drivers / clk / rockchip / clk_rk3399.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0
b0b3c865
KY		 2/*
3 * (C) Copyright 2015 Google, Inc
8fa6979b 4 * (C) 2017 Theobroma Systems Design und Consulting GmbH
b0b3c865
KY		 5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
5ae2fd97 10#include <dt-structs.h>
b0b3c865 11#include <errno.h>
5ae2fd97 12#include <mapmem.h>
b0b3c865 13#include <syscon.h>
364fc731 14#include <bitfield.h>
b0b3c865 15#include <asm/io.h>
15f09a1a
KY		 16#include <asm/arch-rockchip/clock.h>
17#include <asm/arch-rockchip/cru_rk3399.h>
18#include <asm/arch-rockchip/hardware.h>
b0b3c865
KY		 19#include <dm/lists.h>
20#include <dt-bindings/clock/rk3399-cru.h>
21
5ae2fd97
KY		 22#if CONFIG_IS_ENABLED(OF_PLATDATA)
23struct rk3399_clk_plat {
24 struct dtd_rockchip_rk3399_cru dtd;
5e79f443
KY		 25};
26
5ae2fd97
KY		 27struct rk3399_pmuclk_plat {
28 struct dtd_rockchip_rk3399_pmucru dtd;
29};
30#endif
31
b0b3c865
KY		 32struct pll_div {
33 u32 refdiv;
34 u32 fbdiv;
35 u32 postdiv1;
36 u32 postdiv2;
37 u32 frac;
38};
39
40#define RATE_TO_DIV(input_rate, output_rate) \
dd7dfa21
JT		 41 ((input_rate) / (output_rate) - 1)
42#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
b0b3c865
KY		 43
44#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
45 .refdiv = _refdiv,\
46 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
48
61dff33b 49#if defined(CONFIG_SPL_BUILD)
b0b3c865
KY		 50static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
51static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
61dff33b 52#else
b0b3c865 53static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
61dff33b 54#endif
b0b3c865 55
dd7dfa21
JT		 56static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);
57static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
b0b3c865
KY		 58
59static const struct pll_div *apll_l_cfgs[] = {
60 [APLL_L_1600_MHZ] = &apll_l_1600_cfg,
61 [APLL_L_600_MHZ] = &apll_l_600_cfg,
62};
63
dd7dfa21 64static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);
af765a49
CM		 65static const struct pll_div *apll_b_cfgs[] = {
66 [APLL_B_600_MHZ] = &apll_b_600_cfg,
67};
68
b0b3c865
KY		 69enum {
70 /* PLL_CON0 */
71 PLL_FBDIV_MASK = 0xfff,
72 PLL_FBDIV_SHIFT = 0,
73
74 /* PLL_CON1 */
75 PLL_POSTDIV2_SHIFT = 12,
76 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
77 PLL_POSTDIV1_SHIFT = 8,
78 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
79 PLL_REFDIV_MASK = 0x3f,
80 PLL_REFDIV_SHIFT = 0,
81
82 /* PLL_CON2 */
83 PLL_LOCK_STATUS_SHIFT = 31,
84 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
85 PLL_FRACDIV_MASK = 0xffffff,
86 PLL_FRACDIV_SHIFT = 0,
87
88 /* PLL_CON3 */
89 PLL_MODE_SHIFT = 8,
90 PLL_MODE_MASK = 3 << PLL_MODE_SHIFT,
91 PLL_MODE_SLOW = 0,
92 PLL_MODE_NORM,
93 PLL_MODE_DEEP,
94 PLL_DSMPD_SHIFT = 3,
95 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
96 PLL_INTEGER_MODE = 1,
97
98 /* PMUCRU_CLKSEL_CON0 */
99 PMU_PCLK_DIV_CON_MASK = 0x1f,
100 PMU_PCLK_DIV_CON_SHIFT = 0,
101
102 /* PMUCRU_CLKSEL_CON1 */
103 SPI3_PLL_SEL_SHIFT = 7,
104 SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT,
105 SPI3_PLL_SEL_24M = 0,
106 SPI3_PLL_SEL_PPLL = 1,
107 SPI3_DIV_CON_SHIFT = 0x0,
108 SPI3_DIV_CON_MASK = 0x7f,
109
110 /* PMUCRU_CLKSEL_CON2 */
111 I2C_DIV_CON_MASK = 0x7f,
5e79f443
KY		 112 CLK_I2C8_DIV_CON_SHIFT = 8,
113 CLK_I2C0_DIV_CON_SHIFT = 0,
b0b3c865
KY		 114
115 /* PMUCRU_CLKSEL_CON3 */
5e79f443 116 CLK_I2C4_DIV_CON_SHIFT = 0,
b0b3c865
KY		 117
118 /* CLKSEL_CON0 */
119 ACLKM_CORE_L_DIV_CON_SHIFT = 8,
120 ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT,
121 CLK_CORE_L_PLL_SEL_SHIFT = 6,
122 CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT,
123 CLK_CORE_L_PLL_SEL_ALPLL = 0x0,
124 CLK_CORE_L_PLL_SEL_ABPLL = 0x1,
125 CLK_CORE_L_PLL_SEL_DPLL = 0x10,
126 CLK_CORE_L_PLL_SEL_GPLL = 0x11,
127 CLK_CORE_L_DIV_MASK = 0x1f,
128 CLK_CORE_L_DIV_SHIFT = 0,
129
130 /* CLKSEL_CON1 */
131 PCLK_DBG_L_DIV_SHIFT = 0x8,
132 PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT,
133 ATCLK_CORE_L_DIV_SHIFT = 0,
134 ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT,
135
af765a49
CM		 136 /* CLKSEL_CON2 */
137 ACLKM_CORE_B_DIV_CON_SHIFT = 8,
138 ACLKM_CORE_B_DIV_CON_MASK = 0x1f << ACLKM_CORE_B_DIV_CON_SHIFT,
139 CLK_CORE_B_PLL_SEL_SHIFT = 6,
140 CLK_CORE_B_PLL_SEL_MASK = 3 << CLK_CORE_B_PLL_SEL_SHIFT,
141 CLK_CORE_B_PLL_SEL_ALPLL = 0x0,
142 CLK_CORE_B_PLL_SEL_ABPLL = 0x1,
143 CLK_CORE_B_PLL_SEL_DPLL = 0x10,
144 CLK_CORE_B_PLL_SEL_GPLL = 0x11,
145 CLK_CORE_B_DIV_MASK = 0x1f,
146 CLK_CORE_B_DIV_SHIFT = 0,
147
148 /* CLKSEL_CON3 */
149 PCLK_DBG_B_DIV_SHIFT = 0x8,
150 PCLK_DBG_B_DIV_MASK = 0x1f << PCLK_DBG_B_DIV_SHIFT,
151 ATCLK_CORE_B_DIV_SHIFT = 0,
152 ATCLK_CORE_B_DIV_MASK = 0x1f << ATCLK_CORE_B_DIV_SHIFT,
153
b0b3c865
KY		 154 /* CLKSEL_CON14 */
155 PCLK_PERIHP_DIV_CON_SHIFT = 12,
156 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
157 HCLK_PERIHP_DIV_CON_SHIFT = 8,
158 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
159 ACLK_PERIHP_PLL_SEL_SHIFT = 7,
160 ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT,
161 ACLK_PERIHP_PLL_SEL_CPLL = 0,
162 ACLK_PERIHP_PLL_SEL_GPLL = 1,
163 ACLK_PERIHP_DIV_CON_SHIFT = 0,
164 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
165
166 /* CLKSEL_CON21 */
167 ACLK_EMMC_PLL_SEL_SHIFT = 7,
168 ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT,
169 ACLK_EMMC_PLL_SEL_GPLL = 0x1,
170 ACLK_EMMC_DIV_CON_SHIFT = 0,
171 ACLK_EMMC_DIV_CON_MASK = 0x1f,
172
173 /* CLKSEL_CON22 */
174 CLK_EMMC_PLL_SHIFT = 8,
175 CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT,
176 CLK_EMMC_PLL_SEL_GPLL = 0x1,
fd4b2dc0 177 CLK_EMMC_PLL_SEL_24M = 0x5,
b0b3c865
KY		 178 CLK_EMMC_DIV_CON_SHIFT = 0,
179 CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT,
180
181 /* CLKSEL_CON23 */
182 PCLK_PERILP0_DIV_CON_SHIFT = 12,
183 PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT,
184 HCLK_PERILP0_DIV_CON_SHIFT = 8,
185 HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT,
186 ACLK_PERILP0_PLL_SEL_SHIFT = 7,
187 ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT,
188 ACLK_PERILP0_PLL_SEL_CPLL = 0,
189 ACLK_PERILP0_PLL_SEL_GPLL = 1,
190 ACLK_PERILP0_DIV_CON_SHIFT = 0,
191 ACLK_PERILP0_DIV_CON_MASK = 0x1f,
192
193 /* CLKSEL_CON25 */
194 PCLK_PERILP1_DIV_CON_SHIFT = 8,
195 PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT,
196 HCLK_PERILP1_PLL_SEL_SHIFT = 7,
197 HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT,
198 HCLK_PERILP1_PLL_SEL_CPLL = 0,
199 HCLK_PERILP1_PLL_SEL_GPLL = 1,
200 HCLK_PERILP1_DIV_CON_SHIFT = 0,
201 HCLK_PERILP1_DIV_CON_MASK = 0x1f,
202
203 /* CLKSEL_CON26 */
204 CLK_SARADC_DIV_CON_SHIFT = 8,
364fc731
DW		 205 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
206 CLK_SARADC_DIV_CON_WIDTH = 8,
b0b3c865
KY		 207
208 /* CLKSEL_CON27 */
209 CLK_TSADC_SEL_X24M = 0x0,
210 CLK_TSADC_SEL_SHIFT = 15,
211 CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT,
212 CLK_TSADC_DIV_CON_SHIFT = 0,
213 CLK_TSADC_DIV_CON_MASK = 0x3ff,
214
215 /* CLKSEL_CON47 & CLKSEL_CON48 */
216 ACLK_VOP_PLL_SEL_SHIFT = 6,
217 ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT,
218 ACLK_VOP_PLL_SEL_CPLL = 0x1,
219 ACLK_VOP_DIV_CON_SHIFT = 0,
220 ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
221
222 /* CLKSEL_CON49 & CLKSEL_CON50 */
223 DCLK_VOP_DCLK_SEL_SHIFT = 11,
224 DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT,
225 DCLK_VOP_DCLK_SEL_DIVOUT = 0,
226 DCLK_VOP_PLL_SEL_SHIFT = 8,
227 DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT,
228 DCLK_VOP_PLL_SEL_VPLL = 0,
229 DCLK_VOP_DIV_CON_MASK = 0xff,
230 DCLK_VOP_DIV_CON_SHIFT = 0,
231
232 /* CLKSEL_CON58 */
8fa6979b
PT		 233 CLK_SPI_PLL_SEL_WIDTH = 1,
234 CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
235 CLK_SPI_PLL_SEL_CPLL = 0,
236 CLK_SPI_PLL_SEL_GPLL = 1,
237 CLK_SPI_PLL_DIV_CON_WIDTH = 7,
238 CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
239
240 CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
241 CLK_SPI5_PLL_SEL_SHIFT = 15,
b0b3c865
KY		 242
243 /* CLKSEL_CON59 */
244 CLK_SPI1_PLL_SEL_SHIFT = 15,
245 CLK_SPI1_PLL_DIV_CON_SHIFT = 8,
246 CLK_SPI0_PLL_SEL_SHIFT = 7,
247 CLK_SPI0_PLL_DIV_CON_SHIFT = 0,
248
249 /* CLKSEL_CON60 */
250 CLK_SPI4_PLL_SEL_SHIFT = 15,
251 CLK_SPI4_PLL_DIV_CON_SHIFT = 8,
252 CLK_SPI2_PLL_SEL_SHIFT = 7,
253 CLK_SPI2_PLL_DIV_CON_SHIFT = 0,
254
255 /* CLKSEL_CON61 */
256 CLK_I2C_PLL_SEL_MASK = 1,
257 CLK_I2C_PLL_SEL_CPLL = 0,
258 CLK_I2C_PLL_SEL_GPLL = 1,
259 CLK_I2C5_PLL_SEL_SHIFT = 15,
260 CLK_I2C5_DIV_CON_SHIFT = 8,
261 CLK_I2C1_PLL_SEL_SHIFT = 7,
262 CLK_I2C1_DIV_CON_SHIFT = 0,
263
264 /* CLKSEL_CON62 */
265 CLK_I2C6_PLL_SEL_SHIFT = 15,
266 CLK_I2C6_DIV_CON_SHIFT = 8,
267 CLK_I2C2_PLL_SEL_SHIFT = 7,
268 CLK_I2C2_DIV_CON_SHIFT = 0,
269
270 /* CLKSEL_CON63 */
271 CLK_I2C7_PLL_SEL_SHIFT = 15,
272 CLK_I2C7_DIV_CON_SHIFT = 8,
273 CLK_I2C3_PLL_SEL_SHIFT = 7,
274 CLK_I2C3_DIV_CON_SHIFT = 0,
275
276 /* CRU_SOFTRST_CON4 */
277 RESETN_DDR0_REQ_SHIFT = 8,
278 RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT,
279 RESETN_DDRPHY0_REQ_SHIFT = 9,
280 RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT,
281 RESETN_DDR1_REQ_SHIFT = 12,
282 RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT,
283 RESETN_DDRPHY1_REQ_SHIFT = 13,
284 RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT,
285};
286
287#define VCO_MAX_KHZ (3200 * (MHz / KHz))
288#define VCO_MIN_KHZ (800 * (MHz / KHz))
289#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
290#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
291
292/*
293 * the div restructions of pll in integer mode, these are defined in
294 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
295 */
296#define PLL_DIV_MIN 16
297#define PLL_DIV_MAX 3200
298
299/*
300 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
301 * Formulas also embedded within the Fractional PLL Verilog model:
302 * If DSMPD = 1 (DSM is disabled, "integer mode")
303 * FOUTVCO = FREF / REFDIV * FBDIV
304 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
305 * Where:
306 * FOUTVCO = Fractional PLL non-divided output frequency
307 * FOUTPOSTDIV = Fractional PLL divided output frequency
308 * (output of second post divider)
309 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
310 * REFDIV = Fractional PLL input reference clock divider
311 * FBDIV = Integer value programmed into feedback divide
312 *
313 */
314static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div)
315{
316 /* All 8 PLLs have same VCO and output frequency range restrictions. */
317 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
318 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
319
320 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, "
321 "postdiv2=%d, vco=%u khz, output=%u khz\n",
322 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
323 div->postdiv2, vco_khz, output_khz);
324 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
325 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
326 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
327
328 /*
329 * When power on or changing PLL setting,
330 * we must force PLL into slow mode to ensure output stable clock.
331 */
332 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
333 PLL_MODE_SLOW << PLL_MODE_SHIFT);
334
335 /* use integer mode */
336 rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK,
337 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
338
339 rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK,
340 div->fbdiv << PLL_FBDIV_SHIFT);
341 rk_clrsetreg(&pll_con[1],
342 PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK |
343 PLL_REFDIV_MASK | PLL_REFDIV_SHIFT,
344 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
345 (div->postdiv1 << PLL_POSTDIV1_SHIFT) |
346 (div->refdiv << PLL_REFDIV_SHIFT));
347
348 /* waiting for pll lock */
349 while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT)))
350 udelay(1);
351
352 /* pll enter normal mode */
353 rk_clrsetreg(&pll_con[3], PLL_MODE_MASK,
354 PLL_MODE_NORM << PLL_MODE_SHIFT);
355}
356
357static int pll_para_config(u32 freq_hz, struct pll_div *div)
358{
359 u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0;
360 u32 postdiv1, postdiv2 = 1;
361 u32 fref_khz;
362 u32 diff_khz, best_diff_khz;
363 const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
364 const u32 max_postdiv1 = 7, max_postdiv2 = 7;
365 u32 vco_khz;
366 u32 freq_khz = freq_hz / KHz;
367
368 if (!freq_hz) {
369 printf("%s: the frequency can't be 0 Hz\n", __func__);
370 return -1;
371 }
372
373 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
374 if (postdiv1 > max_postdiv1) {
375 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
376 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
377 }
378
379 vco_khz = freq_khz * postdiv1 * postdiv2;
380
381 if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ ||
382 postdiv2 > max_postdiv2) {
383 printf("%s: Cannot find out a supported VCO"
384 " for Frequency (%uHz).\n", __func__, freq_hz);
385 return -1;
386 }
387
388 div->postdiv1 = postdiv1;
389 div->postdiv2 = postdiv2;
390
391 best_diff_khz = vco_khz;
392 for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
393 fref_khz = ref_khz / refdiv;
394
395 fbdiv = vco_khz / fref_khz;
dd7dfa21 396 if (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)
b0b3c865
KY		 397 continue;
398 diff_khz = vco_khz - fbdiv * fref_khz;
399 if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
400 fbdiv++;
401 diff_khz = fref_khz - diff_khz;
402 }
403
404 if (diff_khz >= best_diff_khz)
405 continue;
406
407 best_diff_khz = diff_khz;
408 div->refdiv = refdiv;
409 div->fbdiv = fbdiv;
410 }
411
dd7dfa21 412 if (best_diff_khz > 4 * (MHz / KHz)) {
b0b3c865
KY		 413 printf("%s: Failed to match output frequency %u, "
414 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
415 best_diff_khz * KHz);
416 return -1;
417 }
418 return 0;
419}
420
af765a49
CM		 421void rk3399_configure_cpu_l(struct rk3399_cru *cru,
422 enum apll_l_frequencies apll_l_freq)
b0b3c865
KY		 423{
424 u32 aclkm_div;
425 u32 pclk_dbg_div;
426 u32 atclk_div;
427
af765a49 428 /* Setup cluster L */
b0b3c865
KY		 429 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]);
430
af765a49
CM		 431 aclkm_div = LPLL_HZ / ACLKM_CORE_L_HZ - 1;
432 assert((aclkm_div + 1) * ACLKM_CORE_L_HZ == LPLL_HZ &&
b0b3c865
KY		 433 aclkm_div < 0x1f);
434
af765a49
CM		 435 pclk_dbg_div = LPLL_HZ / PCLK_DBG_L_HZ - 1;
436 assert((pclk_dbg_div + 1) * PCLK_DBG_L_HZ == LPLL_HZ &&
b0b3c865
KY		 437 pclk_dbg_div < 0x1f);
438
af765a49
CM		 439 atclk_div = LPLL_HZ / ATCLK_CORE_L_HZ - 1;
440 assert((atclk_div + 1) * ATCLK_CORE_L_HZ == LPLL_HZ &&
b0b3c865
KY		 441 atclk_div < 0x1f);
442
443 rk_clrsetreg(&cru->clksel_con[0],
444 ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK |
445 CLK_CORE_L_DIV_MASK,
446 aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT |
447 CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT |
448 0 << CLK_CORE_L_DIV_SHIFT);
449
450 rk_clrsetreg(&cru->clksel_con[1],
451 PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK,
452 pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT |
453 atclk_div << ATCLK_CORE_L_DIV_SHIFT);
454}
af765a49
CM		 455
456void rk3399_configure_cpu_b(struct rk3399_cru *cru,
457 enum apll_b_frequencies apll_b_freq)
458{
459 u32 aclkm_div;
460 u32 pclk_dbg_div;
461 u32 atclk_div;
462
463 /* Setup cluster B */
464 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]);
465
466 aclkm_div = BPLL_HZ / ACLKM_CORE_B_HZ - 1;
467 assert((aclkm_div + 1) * ACLKM_CORE_B_HZ == BPLL_HZ &&
468 aclkm_div < 0x1f);
469
470 pclk_dbg_div = BPLL_HZ / PCLK_DBG_B_HZ - 1;
471 assert((pclk_dbg_div + 1) * PCLK_DBG_B_HZ == BPLL_HZ &&
472 pclk_dbg_div < 0x1f);
473
474 atclk_div = BPLL_HZ / ATCLK_CORE_B_HZ - 1;
475 assert((atclk_div + 1) * ATCLK_CORE_B_HZ == BPLL_HZ &&
476 atclk_div < 0x1f);
477
478 rk_clrsetreg(&cru->clksel_con[2],
479 ACLKM_CORE_B_DIV_CON_MASK | CLK_CORE_B_PLL_SEL_MASK |
480 CLK_CORE_B_DIV_MASK,
481 aclkm_div << ACLKM_CORE_B_DIV_CON_SHIFT |
482 CLK_CORE_B_PLL_SEL_ABPLL << CLK_CORE_B_PLL_SEL_SHIFT |
483 0 << CLK_CORE_B_DIV_SHIFT);
484
485 rk_clrsetreg(&cru->clksel_con[3],
486 PCLK_DBG_B_DIV_MASK | ATCLK_CORE_B_DIV_MASK,
487 pclk_dbg_div << PCLK_DBG_B_DIV_SHIFT |
488 atclk_div << ATCLK_CORE_B_DIV_SHIFT);
489}
490
b0b3c865 491#define I2C_CLK_REG_MASK(bus) \
dd7dfa21
JT		 492 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \
493 CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)
b0b3c865
KY		 494
495#define I2C_CLK_REG_VALUE(bus, clk_div) \
dd7dfa21
JT		 496 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \
497 CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)
b0b3c865
KY		 498
499#define I2C_CLK_DIV_VALUE(con, bus) \
dd7dfa21 500 ((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)
b0b3c865 501
5e79f443 502#define I2C_PMUCLK_REG_MASK(bus) \
dd7dfa21 503 (I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)
5e79f443
KY		 504
505#define I2C_PMUCLK_REG_VALUE(bus, clk_div) \
dd7dfa21 506 ((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)
5e79f443 507
b0b3c865
KY		 508static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)
509{
510 u32 div, con;
511
512 switch (clk_id) {
513 case SCLK_I2C1:
514 con = readl(&cru->clksel_con[61]);
515 div = I2C_CLK_DIV_VALUE(con, 1);
516 break;
517 case SCLK_I2C2:
518 con = readl(&cru->clksel_con[62]);
519 div = I2C_CLK_DIV_VALUE(con, 2);
520 break;
521 case SCLK_I2C3:
522 con = readl(&cru->clksel_con[63]);
523 div = I2C_CLK_DIV_VALUE(con, 3);
524 break;
525 case SCLK_I2C5:
526 con = readl(&cru->clksel_con[61]);
527 div = I2C_CLK_DIV_VALUE(con, 5);
528 break;
529 case SCLK_I2C6:
530 con = readl(&cru->clksel_con[62]);
531 div = I2C_CLK_DIV_VALUE(con, 6);
532 break;
533 case SCLK_I2C7:
534 con = readl(&cru->clksel_con[63]);
535 div = I2C_CLK_DIV_VALUE(con, 7);
536 break;
537 default:
538 printf("do not support this i2c bus\n");
539 return -EINVAL;
540 }
541
542 return DIV_TO_RATE(GPLL_HZ, div);
543}
544
545static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
546{
547 int src_clk_div;
548
549 /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
550 src_clk_div = GPLL_HZ / hz;
551 assert(src_clk_div - 1 < 127);
552
553 switch (clk_id) {
554 case SCLK_I2C1:
555 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1),
556 I2C_CLK_REG_VALUE(1, src_clk_div));
557 break;
558 case SCLK_I2C2:
559 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2),
560 I2C_CLK_REG_VALUE(2, src_clk_div));
561 break;
562 case SCLK_I2C3:
563 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3),
564 I2C_CLK_REG_VALUE(3, src_clk_div));
565 break;
566 case SCLK_I2C5:
567 rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5),
568 I2C_CLK_REG_VALUE(5, src_clk_div));
569 break;
570 case SCLK_I2C6:
571 rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6),
572 I2C_CLK_REG_VALUE(6, src_clk_div));
573 break;
574 case SCLK_I2C7:
575 rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7),
576 I2C_CLK_REG_VALUE(7, src_clk_div));
577 break;
578 default:
579 printf("do not support this i2c bus\n");
580 return -EINVAL;
581 }
582
beb90a53 583 return rk3399_i2c_get_clk(cru, clk_id);
b0b3c865
KY		 584}
585
8fa6979b
PT		 586/*
587 * RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
588 * to select either CPLL or GPLL as the clock-parent. The location within
589 * the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
590 */
591
592struct spi_clkreg {
dd7dfa21
JT		 593 u8 reg; /* CLKSEL_CON[reg] register in CRU */
594 u8 div_shift;
595 u8 sel_shift;
8fa6979b
PT		 596};
597
598/*
599 * The entries are numbered relative to their offset from SCLK_SPI0.
600 *
601 * Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
602 * logic is not supported).
603 */
604static const struct spi_clkreg spi_clkregs[] = {
605 [0] = { .reg = 59,
606 .div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
607 .sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
608 [1] = { .reg = 59,
609 .div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
610 .sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
611 [2] = { .reg = 60,
612 .div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
613 .sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
614 [3] = { .reg = 60,
615 .div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
616 .sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
617 [4] = { .reg = 58,
618 .div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
619 .sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
620};
621
8fa6979b
PT		 622static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
623{
624 const struct spi_clkreg *spiclk = NULL;
625 u32 div, val;
626
627 switch (clk_id) {
628 case SCLK_SPI0 ... SCLK_SPI5:
629 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
630 break;
631
632 default:
9b643e31 633 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT		 634 return -EINVAL;
635 }
636
637 val = readl(&cru->clksel_con[spiclk->reg]);
a8ee98df
PT		 638 div = bitfield_extract(val, spiclk->div_shift,
639 CLK_SPI_PLL_DIV_CON_WIDTH);
8fa6979b
PT		 640
641 return DIV_TO_RATE(GPLL_HZ, div);
642}
643
644static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
645{
646 const struct spi_clkreg *spiclk = NULL;
647 int src_clk_div;
648
217273cd
KY		 649 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
650 assert(src_clk_div < 128);
8fa6979b
PT		 651
652 switch (clk_id) {
653 case SCLK_SPI1 ... SCLK_SPI5:
654 spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
655 break;
656
657 default:
9b643e31 658 pr_err("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
8fa6979b
PT		 659 return -EINVAL;
660 }
661
662 rk_clrsetreg(&cru->clksel_con[spiclk->reg],
663 ((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
664 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
665 ((src_clk_div << spiclk->div_shift) |
666 (CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
667
beb90a53 668 return rk3399_spi_get_clk(cru, clk_id);
8fa6979b
PT		 669}
670
b0b3c865
KY		 671static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
672{
673 struct pll_div vpll_config = {0};
dd7dfa21 674 int aclk_vop = 198 * MHz;
b0b3c865
KY		 675 void *aclkreg_addr, *dclkreg_addr;
676 u32 div;
677
678 switch (clk_id) {
679 case DCLK_VOP0:
680 aclkreg_addr = &cru->clksel_con[47];
681 dclkreg_addr = &cru->clksel_con[49];
682 break;
683 case DCLK_VOP1:
684 aclkreg_addr = &cru->clksel_con[48];
685 dclkreg_addr = &cru->clksel_con[50];
686 break;
687 default:
688 return -EINVAL;
689 }
690 /* vop aclk source clk: cpll */
691 div = CPLL_HZ / aclk_vop;
692 assert(div - 1 < 32);
693
694 rk_clrsetreg(aclkreg_addr,
695 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
696 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
697 (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
698
699 /* vop dclk source from vpll, and equals to vpll(means div == 1) */
700 if (pll_para_config(hz, &vpll_config))
701 return -1;
702
703 rkclk_set_pll(&cru->vpll_con[0], &vpll_config);
704
705 rk_clrsetreg(dclkreg_addr,
dd7dfa21 706 DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
b0b3c865
KY		 707 DCLK_VOP_DIV_CON_MASK,
708 DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |
709 DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |
710 (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
711
712 return hz;
713}
714
715static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
716{
717 u32 div, con;
718
719 switch (clk_id) {
998c61ae 720 case HCLK_SDMMC:
b0b3c865
KY		 721 case SCLK_SDMMC:
722 con = readl(&cru->clksel_con[16]);
3a94d75d
KY		 723 /* dwmmc controller have internal div 2 */
724 div = 2;
b0b3c865
KY		 725 break;
726 case SCLK_EMMC:
727 con = readl(&cru->clksel_con[21]);
3a94d75d 728 div = 1;
b0b3c865
KY		 729 break;
730 default:
731 return -EINVAL;
732 }
b0b3c865 733
3a94d75d 734 div *= (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
fd4b2dc0
KY		 735 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
736 == CLK_EMMC_PLL_SEL_24M)
3a94d75d 737 return DIV_TO_RATE(OSC_HZ, div);
fd4b2dc0
KY		 738 else
739 return DIV_TO_RATE(GPLL_HZ, div);
b0b3c865
KY		 740}
741
742static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
743 ulong clk_id, ulong set_rate)
744{
745 int src_clk_div;
dd7dfa21 746 int aclk_emmc = 198 * MHz;
b0b3c865
KY		 747
748 switch (clk_id) {
998c61ae 749 case HCLK_SDMMC:
b0b3c865 750 case SCLK_SDMMC:
fd4b2dc0 751 /* Select clk_sdmmc source from GPLL by default */
3a94d75d
KY		 752 /* mmc clock defaulg div 2 internal, provide double in cru */
753 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
b0b3c865 754
217273cd 755 if (src_clk_div > 128) {
fd4b2dc0 756 /* use 24MHz source for 400KHz clock */
3a94d75d 757 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
217273cd 758 assert(src_clk_div - 1 < 128);
fd4b2dc0
KY		 759 rk_clrsetreg(&cru->clksel_con[16],
760 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
761 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
762 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
763 } else {
764 rk_clrsetreg(&cru->clksel_con[16],
765 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
766 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
767 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
768 }
b0b3c865
KY		 769 break;
770 case SCLK_EMMC:
771 /* Select aclk_emmc source from GPLL */
dd7dfa21 772 src_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);
217273cd 773 assert(src_clk_div - 1 < 32);
b0b3c865
KY		 774
775 rk_clrsetreg(&cru->clksel_con[21],
776 ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK,
777 ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT |
778 (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT);
779
780 /* Select clk_emmc source from GPLL too */
217273cd
KY		 781 src_clk_div = DIV_ROUND_UP(GPLL_HZ, set_rate);
782 assert(src_clk_div - 1 < 128);
b0b3c865
KY		 783
784 rk_clrsetreg(&cru->clksel_con[22],
785 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
786 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
787 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
788 break;
789 default:
790 return -EINVAL;
791 }
792 return rk3399_mmc_get_clk(cru, clk_id);
793}
794
a45f17e8
PT		 795static ulong rk3399_gmac_set_clk(struct rk3399_cru *cru, ulong rate)
796{
797 ulong ret;
798
799 /*
800 * The RGMII CLK can be derived either from an external "clkin"
801 * or can be generated from internally by a divider from SCLK_MAC.
802 */
803 if (readl(&cru->clksel_con[19]) & BIT(4)) {
804 /* An external clock will always generate the right rate... */
805 ret = rate;
806 } else {
807 /*
808 * No platform uses an internal clock to date.
809 * Implement this once it becomes necessary and print an error
810 * if someone tries to use it (while it remains unimplemented).
811 */
812 pr_err("%s: internal clock is UNIMPLEMENTED\n", __func__);
813 ret = 0;
814 }
815
816 return ret;
817}
818
5ae2fd97
KY		 819#define PMUSGRF_DDR_RGN_CON16 0xff330040
820static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
821 ulong set_rate)
822{
823 struct pll_div dpll_cfg;
824
825 /* IC ECO bug, need to set this register */
826 writel(0xc000c000, PMUSGRF_DDR_RGN_CON16);
827
828 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
829 switch (set_rate) {
09565686
JT		 830 case 50 * MHz:
831 dpll_cfg = (struct pll_div)
832 {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
833 break;
dd7dfa21 834 case 200 * MHz:
5ae2fd97
KY		 835 dpll_cfg = (struct pll_div)
836 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
837 break;
dd7dfa21 838 case 300 * MHz:
5ae2fd97
KY		 839 dpll_cfg = (struct pll_div)
840 {.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
841 break;
dd7dfa21 842 case 666 * MHz:
5ae2fd97
KY		 843 dpll_cfg = (struct pll_div)
844 {.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
845 break;
dd7dfa21 846 case 800 * MHz:
5ae2fd97
KY		 847 dpll_cfg = (struct pll_div)
848 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
849 break;
dd7dfa21 850 case 933 * MHz:
5ae2fd97
KY		 851 dpll_cfg = (struct pll_div)
852 {.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};
853 break;
854 default:
9b643e31 855 pr_err("Unsupported SDRAM frequency!,%ld\n", set_rate);
5ae2fd97
KY		 856 }
857 rkclk_set_pll(&cru->dpll_con[0], &dpll_cfg);
858
859 return set_rate;
860}
364fc731
DW		 861
862static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru)
863{
864 u32 div, val;
865
866 val = readl(&cru->clksel_con[26]);
867 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
868 CLK_SARADC_DIV_CON_WIDTH);
869
870 return DIV_TO_RATE(OSC_HZ, div);
871}
872
873static ulong rk3399_saradc_set_clk(struct rk3399_cru *cru, uint hz)
874{
875 int src_clk_div;
876
877 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
878 assert(src_clk_div < 128);
879
880 rk_clrsetreg(&cru->clksel_con[26],
881 CLK_SARADC_DIV_CON_MASK,
882 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
883
884 return rk3399_saradc_get_clk(cru);
885}
886
b0b3c865
KY		 887static ulong rk3399_clk_get_rate(struct clk *clk)
888{
889 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
890 ulong rate = 0;
891
892 switch (clk->id) {
893 case 0 ... 63:
894 return 0;
998c61ae 895 case HCLK_SDMMC:
b0b3c865
KY		 896 case SCLK_SDMMC:
897 case SCLK_EMMC:
898 rate = rk3399_mmc_get_clk(priv->cru, clk->id);
899 break;
900 case SCLK_I2C1:
901 case SCLK_I2C2:
902 case SCLK_I2C3:
903 case SCLK_I2C5:
904 case SCLK_I2C6:
905 case SCLK_I2C7:
906 rate = rk3399_i2c_get_clk(priv->cru, clk->id);
907 break;
8fa6979b
PT		 908 case SCLK_SPI0...SCLK_SPI5:
909 rate = rk3399_spi_get_clk(priv->cru, clk->id);
910 break;
911 case SCLK_UART0:
24615436 912 case SCLK_UART1:
8fa6979b 913 case SCLK_UART2:
24615436 914 case SCLK_UART3:
8fa6979b 915 return 24000000;
ffc1fac5
PT		 916 case PCLK_HDMI_CTRL:
917 break;
b0b3c865
KY		 918 case DCLK_VOP0:
919 case DCLK_VOP1:
920 break;
a70feb46
PT		 921 case PCLK_EFUSE1024NS:
922 break;
364fc731
DW		 923 case SCLK_SARADC:
924 rate = rk3399_saradc_get_clk(priv->cru);
925 break;
5328af17
SG		 926 case ACLK_VIO:
927 case ACLK_HDCP:
928 case ACLK_GIC_PRE:
929 case PCLK_DDR:
930 break;
b0b3c865 931 default:
5328af17 932 log_debug("Unknown clock %lu\n", clk->id);
b0b3c865
KY		 933 return -ENOENT;
934 }
935
936 return rate;
937}
938
939static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
940{
941 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
942 ulong ret = 0;
943
944 switch (clk->id) {
945 case 0 ... 63:
946 return 0;
d2f1f1ab
PT		 947
948 case ACLK_PERIHP:
949 case HCLK_PERIHP:
950 case PCLK_PERIHP:
951 return 0;
952
953 case ACLK_PERILP0:
954 case HCLK_PERILP0:
955 case PCLK_PERILP0:
956 return 0;
957
958 case ACLK_CCI:
959 return 0;
960
961 case HCLK_PERILP1:
962 case PCLK_PERILP1:
963 return 0;
964
998c61ae 965 case HCLK_SDMMC:
b0b3c865
KY		 966 case SCLK_SDMMC:
967 case SCLK_EMMC:
968 ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
969 break;
65d83303 970 case SCLK_MAC:
a45f17e8 971 ret = rk3399_gmac_set_clk(priv->cru, rate);
65d83303 972 break;
b0b3c865
KY		 973 case SCLK_I2C1:
974 case SCLK_I2C2:
975 case SCLK_I2C3:
976 case SCLK_I2C5:
977 case SCLK_I2C6:
978 case SCLK_I2C7:
979 ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
980 break;
8fa6979b
PT		 981 case SCLK_SPI0...SCLK_SPI5:
982 ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
983 break;
ffc1fac5
PT		 984 case PCLK_HDMI_CTRL:
985 case PCLK_VIO_GRF:
986 /* the PCLK gates for video are enabled by default */
987 break;
b0b3c865
KY		 988 case DCLK_VOP0:
989 case DCLK_VOP1:
5e79f443 990 ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
b0b3c865 991 break;
5ae2fd97
KY		 992 case SCLK_DDRCLK:
993 ret = rk3399_ddr_set_clk(priv->cru, rate);
994 break;
a70feb46
PT		 995 case PCLK_EFUSE1024NS:
996 break;
364fc731
DW		 997 case SCLK_SARADC:
998 ret = rk3399_saradc_set_clk(priv->cru, rate);
999 break;
5328af17
SG		 1000 case ACLK_VIO:
1001 case ACLK_HDCP:
1002 case ACLK_GIC_PRE:
1003 case PCLK_DDR:
1004 return 0;
b0b3c865 1005 default:
5328af17 1006 log_debug("Unknown clock %lu\n", clk->id);
b0b3c865
KY		 1007 return -ENOENT;
1008 }
1009
1010 return ret;
1011}
1012
dd7dfa21
JT		 1013static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,
1014 struct clk *parent)
a45f17e8
PT		 1015{
1016 struct rk3399_clk_priv *priv = dev_get_priv(clk->dev);
1017 const char *clock_output_name;
1018 int ret;
1019
1020 /*
1021 * If the requested parent is in the same clock-controller and
1022 * the id is SCLK_MAC ("clk_gmac"), switch to the internal clock.
1023 */
dd7dfa21 1024 if (parent->dev == clk->dev && parent->id == SCLK_MAC) {
a45f17e8
PT		 1025 debug("%s: switching RGMII to SCLK_MAC\n", __func__);
1026 rk_clrreg(&priv->cru->clksel_con[19], BIT(4));
1027 return 0;
1028 }
1029
1030 /*
1031 * Otherwise, we need to check the clock-output-names of the
1032 * requested parent to see if the requested id is "clkin_gmac".
1033 */
1034 ret = dev_read_string_index(parent->dev, "clock-output-names",
1035 parent->id, &clock_output_name);
1036 if (ret < 0)
1037 return -ENODATA;
1038
1039 /* If this is "clkin_gmac", switch to the external clock input */
1040 if (!strcmp(clock_output_name, "clkin_gmac")) {
1041 debug("%s: switching RGMII to CLKIN\n", __func__);
1042 rk_setreg(&priv->cru->clksel_con[19], BIT(4));
1043 return 0;
1044 }
1045
1046 return -EINVAL;
1047}
1048
dd7dfa21
JT		 1049static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,
1050 struct clk *parent)
a45f17e8
PT		 1051{
1052 switch (clk->id) {
1053 case SCLK_RMII_SRC:
1054 return rk3399_gmac_set_parent(clk, parent);
1055 }
1056
1057 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1058 return -ENOENT;
1059}
1060
2f01a2b2
PT		 1061static int rk3399_clk_enable(struct clk *clk)
1062{
1063 switch (clk->id) {
1064 case HCLK_HOST0:
1065 case HCLK_HOST0_ARB:
1066 case HCLK_HOST1:
1067 case HCLK_HOST1_ARB:
1068 return 0;
a9bdd676
PT		 1069
1070 case SCLK_MAC:
1071 case SCLK_MAC_RX:
1072 case SCLK_MAC_TX:
1073 case SCLK_MACREF:
1074 case SCLK_MACREF_OUT:
1075 case ACLK_GMAC:
1076 case PCLK_GMAC:
1077 /* Required to successfully probe the Designware GMAC driver */
1078 return 0;
555ceca0
MK		 1079
1080 case SCLK_USB3OTG0_REF:
1081 case SCLK_USB3OTG1_REF:
1082 case SCLK_USB3OTG0_SUSPEND:
1083 case SCLK_USB3OTG1_SUSPEND:
1084 case ACLK_USB3OTG0:
1085 case ACLK_USB3OTG1:
1086 case ACLK_USB3_RKSOC_AXI_PERF:
1087 case ACLK_USB3:
1088 case ACLK_USB3_GRF:
1089 /* Required to successfully probe the Designware USB3 driver */
1090 return 0;
2f01a2b2
PT		 1091 }
1092
1093 debug("%s: unsupported clk %ld\n", __func__, clk->id);
1094 return -ENOENT;
1095}
1096
b0b3c865
KY		 1097static struct clk_ops rk3399_clk_ops = {
1098 .get_rate = rk3399_clk_get_rate,
1099 .set_rate = rk3399_clk_set_rate,
75b381aa 1100#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
a45f17e8 1101 .set_parent = rk3399_clk_set_parent,
75b381aa 1102#endif
2f01a2b2 1103 .enable = rk3399_clk_enable,
b0b3c865
KY		 1104};
1105
9f636a24
KY		 1106#ifdef CONFIG_SPL_BUILD
1107static void rkclk_init(struct rk3399_cru *cru)
1108{
1109 u32 aclk_div;
1110 u32 hclk_div;
1111 u32 pclk_div;
1112
af765a49
CM		 1113 rk3399_configure_cpu_l(cru, APLL_L_600_MHZ);
1114 rk3399_configure_cpu_b(cru, APLL_B_600_MHZ);
9f636a24
KY		 1115 /*
1116 * some cru registers changed by bootrom, we'd better reset them to
1117 * reset/default values described in TRM to avoid confusion in kernel.
1118 * Please consider these three lines as a fix of bootrom bug.
1119 */
1120 rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
1121 rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
1122 rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
1123
1124 /* configure gpll cpll */
1125 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
1126 rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
1127
1128 /* configure perihp aclk, hclk, pclk */
1129 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
1130 assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1131
1132 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
1133 assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
1134 PERIHP_ACLK_HZ && (hclk_div < 0x4));
1135
1136 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
1137 assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
1138 PERIHP_ACLK_HZ && (pclk_div < 0x7));
1139
1140 rk_clrsetreg(&cru->clksel_con[14],
1141 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
1142 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
1143 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
1144 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
1145 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
1146 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
1147
1148 /* configure perilp0 aclk, hclk, pclk */
1149 aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
1150 assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
1151
1152 hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
1153 assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
1154 PERILP0_ACLK_HZ && (hclk_div < 0x4));
1155
1156 pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
1157 assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
1158 PERILP0_ACLK_HZ && (pclk_div < 0x7));
1159
1160 rk_clrsetreg(&cru->clksel_con[23],
1161 PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
1162 ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
1163 pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
1164 hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
1165 ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
1166 aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
1167
1168 /* perilp1 hclk select gpll as source */
1169 hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
1170 assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
1171 GPLL_HZ && (hclk_div < 0x1f));
1172
1173 pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
1174 assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
1175 PERILP1_HCLK_HZ && (hclk_div < 0x7));
1176
1177 rk_clrsetreg(&cru->clksel_con[25],
1178 PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
1179 HCLK_PERILP1_PLL_SEL_MASK,
1180 pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
1181 hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
1182 HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
1183}
1184#endif
1185
b0b3c865
KY		 1186static int rk3399_clk_probe(struct udevice *dev)
1187{
5ae2fd97 1188#ifdef CONFIG_SPL_BUILD
b0b3c865
KY		 1189 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1190
5ae2fd97
KY		 1191#if CONFIG_IS_ENABLED(OF_PLATDATA)
1192 struct rk3399_clk_plat *plat = dev_get_platdata(dev);
b0b3c865 1193
c20ee0ed 1194 priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
5ae2fd97
KY		 1195#endif
1196 rkclk_init(priv->cru);
1197#endif
b0b3c865
KY		 1198 return 0;
1199}
1200
1201static int rk3399_clk_ofdata_to_platdata(struct udevice *dev)
1202{
5ae2fd97 1203#if !CONFIG_IS_ENABLED(OF_PLATDATA)
b0b3c865
KY		 1204 struct rk3399_clk_priv *priv = dev_get_priv(dev);
1205
75c78598 1206 priv->cru = dev_read_addr_ptr(dev);
5ae2fd97 1207#endif
b0b3c865
KY		 1208 return 0;
1209}
1210
1211static int rk3399_clk_bind(struct udevice *dev)
1212{
1213 int ret;
f24e36da
KY		 1214 struct udevice *sys_child;
1215 struct sysreset_reg *priv;
b0b3c865
KY		 1216
1217 /* The reset driver does not have a device node, so bind it here */
f24e36da
KY		 1218 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
1219 &sys_child);
1220 if (ret) {
1221 debug("Warning: No sysreset driver: ret=%d\n", ret);
1222 } else {
1223 priv = malloc(sizeof(struct sysreset_reg));
1224 priv->glb_srst_fst_value = offsetof(struct rk3399_cru,
1225 glb_srst_fst_value);
1226 priv->glb_srst_snd_value = offsetof(struct rk3399_cru,
1227 glb_srst_snd_value);
1228 sys_child->priv = priv;
1229 }
b0b3c865 1230
538f67c3
EZ		 1231#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1232 ret = offsetof(struct rk3399_cru, softrst_con[0]);
1233 ret = rockchip_reset_bind(dev, ret, 21);
1234 if (ret)
1235 debug("Warning: software reset driver bind faile\n");
1236#endif
1237
b0b3c865
KY		 1238 return 0;
1239}
1240
1241static const struct udevice_id rk3399_clk_ids[] = {
1242 { .compatible = "rockchip,rk3399-cru" },
1243 { }
1244};
1245
1246U_BOOT_DRIVER(clk_rk3399) = {
5ae2fd97 1247 .name = "rockchip_rk3399_cru",
b0b3c865
KY		 1248 .id = UCLASS_CLK,
1249 .of_match = rk3399_clk_ids,
1250 .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv),
1251 .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata,
1252 .ops = &rk3399_clk_ops,
1253 .bind = rk3399_clk_bind,
1254 .probe = rk3399_clk_probe,
5ae2fd97
KY		 1255#if CONFIG_IS_ENABLED(OF_PLATDATA)
1256 .platdata_auto_alloc_size = sizeof(struct rk3399_clk_plat),
1257#endif
b0b3c865 1258};
5e79f443
KY		 1259
1260static ulong rk3399_i2c_get_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id)
1261{
1262 u32 div, con;
1263
1264 switch (clk_id) {
1265 case SCLK_I2C0_PMU:
1266 con = readl(&pmucru->pmucru_clksel[2]);
1267 div = I2C_CLK_DIV_VALUE(con, 0);
1268 break;
1269 case SCLK_I2C4_PMU:
1270 con = readl(&pmucru->pmucru_clksel[3]);
1271 div = I2C_CLK_DIV_VALUE(con, 4);
1272 break;
1273 case SCLK_I2C8_PMU:
1274 con = readl(&pmucru->pmucru_clksel[2]);
1275 div = I2C_CLK_DIV_VALUE(con, 8);
1276 break;
1277 default:
1278 printf("do not support this i2c bus\n");
1279 return -EINVAL;
1280 }
1281
1282 return DIV_TO_RATE(PPLL_HZ, div);
1283}
1284
1285static ulong rk3399_i2c_set_pmuclk(struct rk3399_pmucru *pmucru, ulong clk_id,
1286 uint hz)
1287{
1288 int src_clk_div;
1289
1290 src_clk_div = PPLL_HZ / hz;
1291 assert(src_clk_div - 1 < 127);
1292
1293 switch (clk_id) {
1294 case SCLK_I2C0_PMU:
1295 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(0),
1296 I2C_PMUCLK_REG_VALUE(0, src_clk_div));
1297 break;
1298 case SCLK_I2C4_PMU:
1299 rk_clrsetreg(&pmucru->pmucru_clksel[3], I2C_PMUCLK_REG_MASK(4),
1300 I2C_PMUCLK_REG_VALUE(4, src_clk_div));
1301 break;
1302 case SCLK_I2C8_PMU:
1303 rk_clrsetreg(&pmucru->pmucru_clksel[2], I2C_PMUCLK_REG_MASK(8),
1304 I2C_PMUCLK_REG_VALUE(8, src_clk_div));
1305 break;
1306 default:
1307 printf("do not support this i2c bus\n");
1308 return -EINVAL;
1309 }
1310
1311 return DIV_TO_RATE(PPLL_HZ, src_clk_div);
1312}
1313
1314static ulong rk3399_pwm_get_clk(struct rk3399_pmucru *pmucru)
1315{
1316 u32 div, con;
1317
1318 /* PWM closk rate is same as pclk_pmu */
1319 con = readl(&pmucru->pmucru_clksel[0]);
1320 div = con & PMU_PCLK_DIV_CON_MASK;
1321
1322 return DIV_TO_RATE(PPLL_HZ, div);
1323}
1324
1325static ulong rk3399_pmuclk_get_rate(struct clk *clk)
1326{
1327 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1328 ulong rate = 0;
1329
1330 switch (clk->id) {
434d5a00
PT		 1331 case PLL_PPLL:
1332 return PPLL_HZ;
5e79f443
KY		 1333 case PCLK_RKPWM_PMU:
1334 rate = rk3399_pwm_get_clk(priv->pmucru);
1335 break;
1336 case SCLK_I2C0_PMU:
1337 case SCLK_I2C4_PMU:
1338 case SCLK_I2C8_PMU:
1339 rate = rk3399_i2c_get_pmuclk(priv->pmucru, clk->id);
1340 break;
1341 default:
1342 return -ENOENT;
1343 }
1344
1345 return rate;
1346}
1347
1348static ulong rk3399_pmuclk_set_rate(struct clk *clk, ulong rate)
1349{
1350 struct rk3399_pmuclk_priv *priv = dev_get_priv(clk->dev);
1351 ulong ret = 0;
1352
1353 switch (clk->id) {
434d5a00
PT		 1354 case PLL_PPLL:
1355 /*
1356 * This has already been set up and we don't want/need
1357 * to change it here. Accept the request though, as the
1358 * device-tree has this in an 'assigned-clocks' list.
1359 */
1360 return PPLL_HZ;
5e79f443
KY		 1361 case SCLK_I2C0_PMU:
1362 case SCLK_I2C4_PMU:
1363 case SCLK_I2C8_PMU:
1364 ret = rk3399_i2c_set_pmuclk(priv->pmucru, clk->id, rate);
1365 break;
1366 default:
1367 return -ENOENT;
1368 }
1369
1370 return ret;
1371}
1372
1373static struct clk_ops rk3399_pmuclk_ops = {
1374 .get_rate = rk3399_pmuclk_get_rate,
1375 .set_rate = rk3399_pmuclk_set_rate,
1376};
1377
5ae2fd97 1378#ifndef CONFIG_SPL_BUILD
5e79f443
KY		 1379static void pmuclk_init(struct rk3399_pmucru *pmucru)
1380{
1381 u32 pclk_div;
1382
1383 /* configure pmu pll(ppll) */
1384 rkclk_set_pll(&pmucru->ppll_con[0], &ppll_init_cfg);
1385
1386 /* configure pmu pclk */
1387 pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1;
5e79f443
KY		 1388 rk_clrsetreg(&pmucru->pmucru_clksel[0],
1389 PMU_PCLK_DIV_CON_MASK,
1390 pclk_div << PMU_PCLK_DIV_CON_SHIFT);
1391}
5ae2fd97 1392#endif
5e79f443
KY		 1393
1394static int rk3399_pmuclk_probe(struct udevice *dev)
1395{
61dff33b 1396#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD)
5e79f443 1397 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
61dff33b 1398#endif
5e79f443 1399
5ae2fd97
KY		 1400#if CONFIG_IS_ENABLED(OF_PLATDATA)
1401 struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev);
1402
c20ee0ed 1403 priv->pmucru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
5ae2fd97 1404#endif
5e79f443 1405
5ae2fd97
KY		 1406#ifndef CONFIG_SPL_BUILD
1407 pmuclk_init(priv->pmucru);
1408#endif
5e79f443
KY		 1409 return 0;
1410}
1411
1412static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
1413{
5ae2fd97 1414#if !CONFIG_IS_ENABLED(OF_PLATDATA)
5e79f443
KY		 1415 struct rk3399_pmuclk_priv *priv = dev_get_priv(dev);
1416
75c78598 1417 priv->pmucru = dev_read_addr_ptr(dev);
5ae2fd97 1418#endif
5e79f443
KY		 1419 return 0;
1420}
1421
538f67c3
EZ		 1422static int rk3399_pmuclk_bind(struct udevice *dev)
1423{
1424#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)
1425 int ret;
1426
1427 ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]);
1428 ret = rockchip_reset_bind(dev, ret, 2);
1429 if (ret)
1430 debug("Warning: software reset driver bind faile\n");
1431#endif
1432 return 0;
1433}
1434
5e79f443
KY		 1435static const struct udevice_id rk3399_pmuclk_ids[] = {
1436 { .compatible = "rockchip,rk3399-pmucru" },
1437 { }
1438};
1439
c8a6bc96 1440U_BOOT_DRIVER(rockchip_rk3399_pmuclk) = {
5ae2fd97 1441 .name = "rockchip_rk3399_pmucru",
5e79f443
KY		 1442 .id = UCLASS_CLK,
1443 .of_match = rk3399_pmuclk_ids,
1444 .priv_auto_alloc_size = sizeof(struct rk3399_pmuclk_priv),
1445 .ofdata_to_platdata = rk3399_pmuclk_ofdata_to_platdata,
1446 .ops = &rk3399_pmuclk_ops,
1447 .probe = rk3399_pmuclk_probe,
538f67c3 1448 .bind = rk3399_pmuclk_bind,
5ae2fd97
KY		 1449#if CONFIG_IS_ENABLED(OF_PLATDATA)
1450 .platdata_auto_alloc_size = sizeof(struct rk3399_pmuclk_plat),
1451#endif
5e79f443 1452};
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