[J-u-boot.git] / drivers / mmc / omap_hsmmc.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 * Sukumar Ghorai <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation's version 2 of
 * the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
#include <twl6035.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>

/* common definitions for all OMAPs */
#define SYSCTL_SRC	(1 << 25)
#define SYSCTL_SRD	(1 << 26)

/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS	1000

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
			unsigned int siz);
static struct mmc hsmmc_dev[2];

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap_sys_ctrl_regs *const ctrl =
		(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;


	value = readl(&ctrl->control_pbiaslite);
	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
	writel(value, &ctrl->control_pbiaslite);
	/* set VMMC to 3V */
	twl6030_power_mmc_init();
	value = readl(&ctrl->control_pbiaslite);
	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
	writel(value, &ctrl->control_pbiaslite);
}
#endif

#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
static void omap5_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap_sys_ctrl_regs *const ctrl =
		(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;

	value = readl(&ctrl->control_pbias);
	value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
	value |= SDCARD_BIAS_HIZ_MODE;
	writel(value, &ctrl->control_pbias);

	twl6035_mmc1_poweron_ldo();

	value = readl(&ctrl->control_pbias);
	value &= ~SDCARD_BIAS_HIZ_MODE;
	value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
	writel(value, &ctrl->control_pbias);

	value = readl(&ctrl->control_pbias);
	if (value & (1 << 23)) {
		value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
		value |= SDCARD_BIAS_HIZ_MODE;
		writel(value, &ctrl->control_pbias);
	}
}
#endif

unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_OMAP34XX)
	t2_t *t2_base = (t2_t *)T2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
	u32 pbias_lite;

	pbias_lite = readl(&t2_base->pbias_lite);
	pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
	writel(pbias_lite, &t2_base->pbias_lite);
#endif
#if defined(CONFIG_TWL4030_POWER)
	twl4030_power_mmc_init();
	mdelay(100);	/* ramp-up delay from Linux code */
#endif
#if defined(CONFIG_OMAP34XX)
	writel(pbias_lite | PBIASLITEPWRDNZ1 |
		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
		&t2_base->pbias_lite);

	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
		&t2_base->devconf0);

	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
		&t2_base->devconf1);

	/* Change from default of 52MHz to 26MHz if necessary */
	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
			&t2_base->ctl_prog_io1);

	writel(readl(&prcm_base->fclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->fclken1_core);

	writel(readl(&prcm_base->iclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->iclken1_core);
#endif

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	/* PBIAS config needed for MMC1 only */
	if (mmc->block_dev.dev == 0)
		omap4_vmmc_pbias_config(mmc);
#endif
#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
	if (mmc->block_dev.dev == 0)
		omap5_pbias_config(mmc);
#endif

	return 0;
}

void mmc_init_stream(struct hsmmc *mmc_base)
{
	ulong start;

	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);

	writel(MMC_CMD0, &mmc_base->cmd);
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc!\n", __func__);
			return;
		}
	}
	writel(CC_MASK, &mmc_base->stat)
		;
	writel(MMC_CMD0, &mmc_base->cmd)
		;
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}


static int mmc_init_setup(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int reg_val;
	unsigned int dsor;
	ulong start;

	mmc_board_init(mmc);

	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
		&mmc_base->sysconfig);
	start = get_timer(0);
	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for softresetall!\n",
				__func__);
			return TIMEOUT;
		}
	}
	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
		&mmc_base->capa);

	reg_val = readl(&mmc_base->con) & RESERVED_MASK;

	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);

	dsor = 240;
	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);

	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);

	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
		&mmc_base->ie);

	mmc_init_stream(mmc_base);

	return 0;
}

/*
 * MMC controller internal finite state machine reset
 *
 * Used to reset command or data internal state machines, using respectively
 * SRC or SRD bit of SYSCTL register
 */
static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
{
	ulong start;

	mmc_reg_out(&mmc_base->sysctl, bit, bit);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & bit) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for sysctl %x to clear\n",
				__func__, bit);
			return;
		}
	}
}

static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			struct mmc_data *data)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int flags, mmc_stat;
	ulong start;

	start = get_timer(0);
	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting on cmd inhibit to clear\n",
					__func__);
			return TIMEOUT;
		}
	}
	writel(0xFFFFFFFF, &mmc_base->stat);
	start = get_timer(0);
	while (readl(&mmc_base->stat)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for STAT (%x) to clear\n",
				__func__, readl(&mmc_base->stat));
			return TIMEOUT;
		}
	}
	/*
	 * CMDREG
	 * CMDIDX[13:8]	: Command index
	 * DATAPRNT[5]	: Data Present Select
	 * ENCMDIDX[4]	: Command Index Check Enable
	 * ENCMDCRC[3]	: Command CRC Check Enable
	 * RSPTYP[1:0]
	 *	00 = No Response
	 *	01 = Length 136
	 *	10 = Length 48
	 *	11 = Length 48 Check busy after response
	 */
	/* Delay added before checking the status of frq change
	 * retry not supported by mmc.c(core file)
	 */
	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
		udelay(50000); /* wait 50 ms */

	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = 0;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		flags = RSP_TYPE_LGHT48B;
	else
		flags = RSP_TYPE_LGHT48;

	/* enable default flags */
	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= CCCE_CHECK;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= CICE_CHECK;

	if (data) {
		if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
			 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
			flags |= (MSBS_MULTIBLK | BCE_ENABLE);
			data->blocksize = 512;
			writel(data->blocksize | (data->blocks << 16),
							&mmc_base->blk);
		} else
			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);

		if (data->flags & MMC_DATA_READ)
			flags |= (DP_DATA | DDIR_READ);
		else
			flags |= (DP_DATA | DDIR_WRITE);
	}

	writel(cmd->cmdarg, &mmc_base->arg);
	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);

	start = get_timer(0);
	do {
		mmc_stat = readl(&mmc_base->stat);
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s : timeout: No status update\n", __func__);
			return TIMEOUT;
		}
	} while (!mmc_stat);

	if ((mmc_stat & IE_CTO) != 0) {
		mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
		return TIMEOUT;
	} else if ((mmc_stat & ERRI_MASK) != 0)
		return -1;

	if (mmc_stat & CC_MASK) {
		writel(CC_MASK, &mmc_base->stat);
		if (cmd->resp_type & MMC_RSP_PRESENT) {
			if (cmd->resp_type & MMC_RSP_136) {
				/* response type 2 */
				cmd->response[3] = readl(&mmc_base->rsp10);
				cmd->response[2] = readl(&mmc_base->rsp32);
				cmd->response[1] = readl(&mmc_base->rsp54);
				cmd->response[0] = readl(&mmc_base->rsp76);
			} else
				/* response types 1, 1b, 3, 4, 5, 6 */
				cmd->response[0] = readl(&mmc_base->rsp10);
		}
	}

	if (data && (data->flags & MMC_DATA_READ)) {
		mmc_read_data(mmc_base,	data->dest,
				data->blocksize * data->blocks);
	} else if (data && (data->flags & MMC_DATA_WRITE)) {
		mmc_write_data(mmc_base, data->src,
				data->blocksize * data->blocks);
	}
	return 0;
}

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
	unsigned int *output_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BRR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);
			for (k = 0; k < count; k++) {
				*output_buf = readl(&mmc_base->data);
				output_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BWR_MASK)
			writel(readl(&mmc_base->stat) | BWR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
				unsigned int size)
{
	unsigned int *input_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
			mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BWR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BWR_MASK,
					&mmc_base->stat);
			for (k = 0; k < count; k++) {
				writel(*input_buf, &mmc_base->data);
				input_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BRR_MASK)
			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static void mmc_set_ios(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int dsor = 0;
	ulong start;

	/* configue bus width */
	switch (mmc->bus_width) {
	case 8:
		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
			&mmc_base->con);
		break;

	case 4:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
			&mmc_base->hctl);
		break;

	case 1:
	default:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
			&mmc_base->hctl);
		break;
	}

	/* configure clock with 96Mhz system clock.
	 */
	if (mmc->clock != 0) {
		dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
		if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
			dsor++;
	}

	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));

	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}

int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
{
	struct mmc *mmc;

	mmc = &hsmmc_dev[dev_index];

	sprintf(mmc->name, "OMAP SD/MMC");
	mmc->send_cmd = mmc_send_cmd;
	mmc->set_ios = mmc_set_ios;
	mmc->init = mmc_init_setup;
	mmc->getcd = NULL;

	switch (dev_index) {
	case 0:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		break;
#ifdef OMAP_HSMMC2_BASE
	case 1:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
		break;
#endif
#ifdef OMAP_HSMMC3_BASE
	case 2:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
		break;
#endif
	default:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		return 1;
	}
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
				MMC_MODE_HC) & ~host_caps_mask;

	mmc->f_min = 400000;

	if (f_max != 0)
		mmc->f_max = f_max;
	else {
		if (mmc->host_caps & MMC_MODE_HS) {
			if (mmc->host_caps & MMC_MODE_HS_52MHz)
				mmc->f_max = 52000000;
			else
				mmc->f_max = 26000000;
		} else
			mmc->f_max = 20000000;
	}

	mmc->b_max = 0;

#if defined(CONFIG_OMAP34XX)
	/*
	 * Silicon revs 2.1 and older do not support multiblock transfers.
	 */
	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
		mmc->b_max = 1;
#endif

	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
de941241 SG	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	* Sukumar Ghorai <[email protected]>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation's version 2 of
	12	* the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include <common.h>
	27	#include <mmc.h>
	28	#include <part.h>
	29	#include <i2c.h>
	30	#include <twl4030.h>
14fa2dd0	31	#include <twl6030.h>
dd23e59d	32	#include <twl6035.h>
de941241 SG	33	#include <asm/io.h>
de941241 SG	34	#include <asm/arch/mmc_host_def.h>
96e0e7b3	35	#include <asm/arch/sys_proto.h>
de941241	36
25c719e2 GI	37	/* common definitions for all OMAPs */
	38	#define SYSCTL_SRC (1 << 25)
	39	#define SYSCTL_SRD (1 << 26)
	40
eb9a28f6 NM	41	/* If we fail after 1 second wait, something is really bad */
	42	#define MAX_RETRY_MS 1000
	43
933efe64 S	44	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size);
	45	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
	46	unsigned int siz);
de941241	47	static struct mmc hsmmc_dev[2];
14fa2dd0 B	48
	49	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	50	static void omap4_vmmc_pbias_config(struct mmc *mmc)
	51	{
	52	u32 value = 0;
002a2c0c S	53	struct omap_sys_ctrl_regs *const ctrl =
002a2c0c S	54	(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
14fa2dd0 B	55
	56
	57	value = readl(&ctrl->control_pbiaslite);
	58	value &= ~(MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ);
	59	writel(value, &ctrl->control_pbiaslite);
	60	/* set VMMC to 3V */
	61	twl6030_power_mmc_init();
	62	value = readl(&ctrl->control_pbiaslite);
	63	value \|= MMC1_PBIASLITE_VMODE \| MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ;
	64	writel(value, &ctrl->control_pbiaslite);
	65	}
	66	#endif
	67
dd23e59d B	68	#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
	69	static void omap5_pbias_config(struct mmc *mmc)
	70	{
	71	u32 value = 0;
	72	struct omap_sys_ctrl_regs *const ctrl =
	73	(struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
	74
	75	value = readl(&ctrl->control_pbias);
	76	value &= ~(SDCARD_PWRDNZ \| SDCARD_BIAS_PWRDNZ);
	77	value \|= SDCARD_BIAS_HIZ_MODE;
	78	writel(value, &ctrl->control_pbias);
	79
	80	twl6035_mmc1_poweron_ldo();
	81
	82	value = readl(&ctrl->control_pbias);
	83	value &= ~SDCARD_BIAS_HIZ_MODE;
	84	value \|= SDCARD_PBIASLITE_VMODE \| SDCARD_PWRDNZ \| SDCARD_BIAS_PWRDNZ;
	85	writel(value, &ctrl->control_pbias);
	86
	87	value = readl(&ctrl->control_pbias);
	88	if (value & (1 << 23)) {
	89	value &= ~(SDCARD_PWRDNZ \| SDCARD_BIAS_PWRDNZ);
	90	value \|= SDCARD_BIAS_HIZ_MODE;
	91	writel(value, &ctrl->control_pbias);
	92	}
	93	}
	94	#endif
	95
14fa2dd0	96	unsigned char mmc_board_init(struct mmc *mmc)
de941241	97	{
de941241 SG	98	#if defined(CONFIG_OMAP34XX)
	99	t2_t t2_base = (t2_t )T2_BASE;
	100	struct prcm prcm_base = (struct prcm )PRCM_BASE;
b1e725f2	101	u32 pbias_lite;
de941241	102
b1e725f2 GI	103	pbias_lite = readl(&t2_base->pbias_lite);
	104	pbias_lite &= ~(PBIASLITEPWRDNZ1 \| PBIASLITEPWRDNZ0);
	105	writel(pbias_lite, &t2_base->pbias_lite);
	106	#endif
	107	#if defined(CONFIG_TWL4030_POWER)
	108	twl4030_power_mmc_init();
	109	mdelay(100); /* ramp-up delay from Linux code */
	110	#endif
	111	#if defined(CONFIG_OMAP34XX)
	112	writel(pbias_lite \| PBIASLITEPWRDNZ1 \|
de941241 SG	113	PBIASSPEEDCTRL0 \| PBIASLITEPWRDNZ0,
	114	&t2_base->pbias_lite);
	115
	116	writel(readl(&t2_base->devconf0) \| MMCSDIO1ADPCLKISEL,
	117	&t2_base->devconf0);
	118
	119	writel(readl(&t2_base->devconf1) \| MMCSDIO2ADPCLKISEL,
	120	&t2_base->devconf1);
	121
bbbc1ae9 JS	122	/* Change from default of 52MHz to 26MHz if necessary */
	123	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
	124	writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
	125	&t2_base->ctl_prog_io1);
	126
de941241 SG	127	writel(readl(&prcm_base->fclken1_core) \|
	128	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	129	&prcm_base->fclken1_core);
	130
	131	writel(readl(&prcm_base->iclken1_core) \|
	132	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	133	&prcm_base->iclken1_core);
	134	#endif
	135
14fa2dd0 B	136	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	137	/* PBIAS config needed for MMC1 only */
	138	if (mmc->block_dev.dev == 0)
	139	omap4_vmmc_pbias_config(mmc);
	140	#endif
dd23e59d B	141	#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
	142	if (mmc->block_dev.dev == 0)
	143	omap5_pbias_config(mmc);
	144	#endif
de941241 SG	145
	146	return 0;
	147	}
	148
933efe64	149	void mmc_init_stream(struct hsmmc *mmc_base)
de941241	150	{
eb9a28f6	151	ulong start;
de941241 SG	152
	153	writel(readl(&mmc_base->con) \| INIT_INITSTREAM, &mmc_base->con);
	154
	155	writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6 NM	156	start = get_timer(0);
	157	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	158	if (get_timer(0) - start > MAX_RETRY_MS) {
	159	printf("%s: timedout waiting for cc!\n", __func__);
	160	return;
	161	}
	162	}
de941241 SG	163	writel(CC_MASK, &mmc_base->stat)
	164	;
	165	writel(MMC_CMD0, &mmc_base->cmd)
	166	;
eb9a28f6 NM	167	start = get_timer(0);
	168	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	169	if (get_timer(0) - start > MAX_RETRY_MS) {
	170	printf("%s: timedout waiting for cc2!\n", __func__);
	171	return;
	172	}
	173	}
de941241 SG	174	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
	175	}
	176
	177
	178	static int mmc_init_setup(struct mmc *mmc)
	179	{
933efe64	180	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241 SG	181	unsigned int reg_val;
de941241 SG	182	unsigned int dsor;
eb9a28f6	183	ulong start;
de941241	184
14fa2dd0	185	mmc_board_init(mmc);
de941241 SG	186
	187	writel(readl(&mmc_base->sysconfig) \| MMC_SOFTRESET,
	188	&mmc_base->sysconfig);
eb9a28f6 NM	189	start = get_timer(0);
	190	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
	191	if (get_timer(0) - start > MAX_RETRY_MS) {
	192	printf("%s: timedout waiting for cc2!\n", __func__);
	193	return TIMEOUT;
	194	}
	195	}
de941241	196	writel(readl(&mmc_base->sysctl) \| SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6 NM	197	start = get_timer(0);
	198	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
	199	if (get_timer(0) - start > MAX_RETRY_MS) {
	200	printf("%s: timedout waiting for softresetall!\n",
	201	__func__);
	202	return TIMEOUT;
	203	}
	204	}
de941241 SG	205	writel(DTW_1_BITMODE \| SDBP_PWROFF \| SDVS_3V0, &mmc_base->hctl);
	206	writel(readl(&mmc_base->capa) \| VS30_3V0SUP \| VS18_1V8SUP,
	207	&mmc_base->capa);
	208
	209	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
	210
	211	writel(CTPL_MMC_SD \| reg_val \| WPP_ACTIVEHIGH \| CDP_ACTIVEHIGH \|
	212	MIT_CTO \| DW8_1_4BITMODE \| MODE_FUNC \| STR_BLOCK \|
	213	HR_NOHOSTRESP \| INIT_NOINIT \| NOOPENDRAIN, &mmc_base->con);
	214
	215	dsor = 240;
	216	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	217	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	218	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	219	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
eb9a28f6 NM	220	start = get_timer(0);
	221	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	222	if (get_timer(0) - start > MAX_RETRY_MS) {
	223	printf("%s: timedout waiting for ics!\n", __func__);
	224	return TIMEOUT;
	225	}
	226	}
de941241 SG	227	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	228
	229	writel(readl(&mmc_base->hctl) \| SDBP_PWRON, &mmc_base->hctl);
	230
	231	writel(IE_BADA \| IE_CERR \| IE_DEB \| IE_DCRC \| IE_DTO \| IE_CIE \|
	232	IE_CEB \| IE_CCRC \| IE_CTO \| IE_BRR \| IE_BWR \| IE_TC \| IE_CC,
	233	&mmc_base->ie);
	234
	235	mmc_init_stream(mmc_base);
	236
	237	return 0;
	238	}
	239
25c719e2 GI	240	/*
	241	* MMC controller internal finite state machine reset
	242	*
	243	* Used to reset command or data internal state machines, using respectively
	244	* SRC or SRD bit of SYSCTL register
	245	*/
	246	static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
	247	{
	248	ulong start;
	249
	250	mmc_reg_out(&mmc_base->sysctl, bit, bit);
	251
	252	start = get_timer(0);
	253	while ((readl(&mmc_base->sysctl) & bit) != 0) {
	254	if (get_timer(0) - start > MAX_RETRY_MS) {
	255	printf("%s: timedout waiting for sysctl %x to clear\n",
	256	__func__, bit);
	257	return;
	258	}
	259	}
	260	}
de941241 SG	261
	262	static int mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	263	struct mmc_data *data)
	264	{
933efe64	265	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	266	unsigned int flags, mmc_stat;
eb9a28f6	267	ulong start;
de941241	268
eb9a28f6	269	start = get_timer(0);
a7778f8f	270	while ((readl(&mmc_base->pstate) & (DATI_MASK \| CMDI_MASK)) != 0) {
eb9a28f6	271	if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f TR	272	printf("%s: timedout waiting on cmd inhibit to clear\n",
a7778f8f TR	273	__func__);
eb9a28f6 NM	274	return TIMEOUT;
	275	}
	276	}
de941241	277	writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6 NM	278	start = get_timer(0);
	279	while (readl(&mmc_base->stat)) {
	280	if (get_timer(0) - start > MAX_RETRY_MS) {
15ceb1de GI	281	printf("%s: timedout waiting for STAT (%x) to clear\n",
15ceb1de GI	282	__func__, readl(&mmc_base->stat));
eb9a28f6 NM	283	return TIMEOUT;
	284	}
	285	}
de941241 SG	286	/*
	287	* CMDREG
	288	* CMDIDX[13:8] : Command index
	289	* DATAPRNT[5] : Data Present Select
	290	* ENCMDIDX[4] : Command Index Check Enable
	291	* ENCMDCRC[3] : Command CRC Check Enable
	292	* RSPTYP[1:0]
	293	* 00 = No Response
	294	* 01 = Length 136
	295	* 10 = Length 48
	296	* 11 = Length 48 Check busy after response
	297	*/
	298	/* Delay added before checking the status of frq change
	299	* retry not supported by mmc.c(core file)
	300	*/
	301	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
	302	udelay(50000); /* wait 50 ms */
	303
	304	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	305	flags = 0;
	306	else if (cmd->resp_type & MMC_RSP_136)
	307	flags = RSP_TYPE_LGHT136 \| CICE_NOCHECK;
	308	else if (cmd->resp_type & MMC_RSP_BUSY)
	309	flags = RSP_TYPE_LGHT48B;
	310	else
	311	flags = RSP_TYPE_LGHT48;
	312
	313	/* enable default flags */
	314	flags = flags \| (CMD_TYPE_NORMAL \| CICE_NOCHECK \| CCCE_NOCHECK \|
	315	MSBS_SGLEBLK \| ACEN_DISABLE \| BCE_DISABLE \| DE_DISABLE);
	316
	317	if (cmd->resp_type & MMC_RSP_CRC)
	318	flags \|= CCCE_CHECK;
	319	if (cmd->resp_type & MMC_RSP_OPCODE)
	320	flags \|= CICE_CHECK;
	321
	322	if (data) {
	323	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) \|\|
	324	(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
	325	flags \|= (MSBS_MULTIBLK \| BCE_ENABLE);
	326	data->blocksize = 512;
	327	writel(data->blocksize \| (data->blocks << 16),
	328	&mmc_base->blk);
	329	} else
	330	writel(data->blocksize \| NBLK_STPCNT, &mmc_base->blk);
	331
	332	if (data->flags & MMC_DATA_READ)
	333	flags \|= (DP_DATA \| DDIR_READ);
	334	else
	335	flags \|= (DP_DATA \| DDIR_WRITE);
	336	}
	337
	338	writel(cmd->cmdarg, &mmc_base->arg);
	339	writel((cmd->cmdidx << 24) \| flags, &mmc_base->cmd);
	340
eb9a28f6	341	start = get_timer(0);
de941241 SG	342	do {
de941241 SG	343	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	344	if (get_timer(0) - start > MAX_RETRY_MS) {
	345	printf("%s : timeout: No status update\n", __func__);
	346	return TIMEOUT;
	347	}
	348	} while (!mmc_stat);
de941241	349
25c719e2 GI	350	if ((mmc_stat & IE_CTO) != 0) {
25c719e2 GI	351	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
de941241	352	return TIMEOUT;
25c719e2	353	} else if ((mmc_stat & ERRI_MASK) != 0)
de941241 SG	354	return -1;
	355
	356	if (mmc_stat & CC_MASK) {
	357	writel(CC_MASK, &mmc_base->stat);
	358	if (cmd->resp_type & MMC_RSP_PRESENT) {
	359	if (cmd->resp_type & MMC_RSP_136) {
	360	/* response type 2 */
	361	cmd->response[3] = readl(&mmc_base->rsp10);
	362	cmd->response[2] = readl(&mmc_base->rsp32);
	363	cmd->response[1] = readl(&mmc_base->rsp54);
	364	cmd->response[0] = readl(&mmc_base->rsp76);
	365	} else
	366	/* response types 1, 1b, 3, 4, 5, 6 */
	367	cmd->response[0] = readl(&mmc_base->rsp10);
	368	}
	369	}
	370
	371	if (data && (data->flags & MMC_DATA_READ)) {
	372	mmc_read_data(mmc_base, data->dest,
	373	data->blocksize * data->blocks);
	374	} else if (data && (data->flags & MMC_DATA_WRITE)) {
	375	mmc_write_data(mmc_base, data->src,
	376	data->blocksize * data->blocks);
	377	}
	378	return 0;
	379	}
	380
933efe64	381	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size)
de941241 SG	382	{
	383	unsigned int output_buf = (unsigned int )buf;
	384	unsigned int mmc_stat;
	385	unsigned int count;
	386
	387	/*
	388	* Start Polled Read
	389	*/
	390	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	391	count /= 4;
	392
	393	while (size) {
eb9a28f6	394	ulong start = get_timer(0);
de941241 SG	395	do {
de941241 SG	396	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	397	if (get_timer(0) - start > MAX_RETRY_MS) {
	398	printf("%s: timedout waiting for status!\n",
	399	__func__);
	400	return TIMEOUT;
	401	}
de941241 SG	402	} while (mmc_stat == 0);
de941241 SG	403
25c719e2 GI	404	if ((mmc_stat & (IE_DTO \| IE_DCRC \| IE_DEB)) != 0)
	405	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
	406
de941241 SG	407	if ((mmc_stat & ERRI_MASK) != 0)
	408	return 1;
	409
	410	if (mmc_stat & BRR_MASK) {
	411	unsigned int k;
	412
	413	writel(readl(&mmc_base->stat) \| BRR_MASK,
	414	&mmc_base->stat);
	415	for (k = 0; k < count; k++) {
	416	*output_buf = readl(&mmc_base->data);
	417	output_buf++;
	418	}
	419	size -= (count*4);
	420	}
	421
	422	if (mmc_stat & BWR_MASK)
	423	writel(readl(&mmc_base->stat) \| BWR_MASK,
	424	&mmc_base->stat);
	425
	426	if (mmc_stat & TC_MASK) {
	427	writel(readl(&mmc_base->stat) \| TC_MASK,
	428	&mmc_base->stat);
	429	break;
	430	}
	431	}
	432	return 0;
	433	}
	434
933efe64 S	435	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
933efe64 S	436	unsigned int size)
de941241 SG	437	{
	438	unsigned int input_buf = (unsigned int )buf;
	439	unsigned int mmc_stat;
	440	unsigned int count;
	441
	442	/*
	443	* Start Polled Read
	444	*/
	445	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	446	count /= 4;
	447
	448	while (size) {
eb9a28f6	449	ulong start = get_timer(0);
de941241 SG	450	do {
de941241 SG	451	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	452	if (get_timer(0) - start > MAX_RETRY_MS) {
	453	printf("%s: timedout waiting for status!\n",
	454	__func__);
	455	return TIMEOUT;
	456	}
de941241 SG	457	} while (mmc_stat == 0);
de941241 SG	458
25c719e2 GI	459	if ((mmc_stat & (IE_DTO \| IE_DCRC \| IE_DEB)) != 0)
	460	mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
	461
de941241 SG	462	if ((mmc_stat & ERRI_MASK) != 0)
	463	return 1;
	464
	465	if (mmc_stat & BWR_MASK) {
	466	unsigned int k;
	467
	468	writel(readl(&mmc_base->stat) \| BWR_MASK,
	469	&mmc_base->stat);
	470	for (k = 0; k < count; k++) {
	471	writel(*input_buf, &mmc_base->data);
	472	input_buf++;
	473	}
	474	size -= (count*4);
	475	}
	476
	477	if (mmc_stat & BRR_MASK)
	478	writel(readl(&mmc_base->stat) \| BRR_MASK,
	479	&mmc_base->stat);
	480
	481	if (mmc_stat & TC_MASK) {
	482	writel(readl(&mmc_base->stat) \| TC_MASK,
	483	&mmc_base->stat);
	484	break;
	485	}
	486	}
	487	return 0;
	488	}
	489
	490	static void mmc_set_ios(struct mmc *mmc)
	491	{
933efe64	492	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	493	unsigned int dsor = 0;
eb9a28f6	494	ulong start;
de941241 SG	495
	496	/* configue bus width */
	497	switch (mmc->bus_width) {
	498	case 8:
	499	writel(readl(&mmc_base->con) \| DTW_8_BITMODE,
	500	&mmc_base->con);
	501	break;
	502
	503	case 4:
	504	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	505	&mmc_base->con);
	506	writel(readl(&mmc_base->hctl) \| DTW_4_BITMODE,
	507	&mmc_base->hctl);
	508	break;
	509
	510	case 1:
	511	default:
	512	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	513	&mmc_base->con);
	514	writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
	515	&mmc_base->hctl);
	516	break;
	517	}
	518
	519	/* configure clock with 96Mhz system clock.
	520	*/
	521	if (mmc->clock != 0) {
	522	dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
	523	if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
	524	dsor++;
	525	}
	526
	527	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	528	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	529
	530	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	531	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
	532
eb9a28f6 NM	533	start = get_timer(0);
	534	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	535	if (get_timer(0) - start > MAX_RETRY_MS) {
	536	printf("%s: timedout waiting for ics!\n", __func__);
	537	return;
	538	}
	539	}
de941241 SG	540	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	541	}
	542
bbbc1ae9	543	int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
de941241 SG	544	{
	545	struct mmc *mmc;
	546
	547	mmc = &hsmmc_dev[dev_index];
	548
	549	sprintf(mmc->name, "OMAP SD/MMC");
	550	mmc->send_cmd = mmc_send_cmd;
	551	mmc->set_ios = mmc_set_ios;
	552	mmc->init = mmc_init_setup;
48972d90	553	mmc->getcd = NULL;
de941241 SG	554
	555	switch (dev_index) {
	556	case 0:
933efe64	557	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241	558	break;
1037d585	559	#ifdef OMAP_HSMMC2_BASE
de941241	560	case 1:
933efe64	561	mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
de941241	562	break;
1037d585 TR	563	#endif
1037d585 TR	564	#ifdef OMAP_HSMMC3_BASE
de941241	565	case 2:
933efe64	566	mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
de941241	567	break;
1037d585	568	#endif
de941241	569	default:
933efe64	570	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 SG	571	return 1;
	572	}
	573	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
bbbc1ae9 JS	574	mmc->host_caps = (MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS \|
bbbc1ae9 JS	575	MMC_MODE_HC) & ~host_caps_mask;
de941241 SG	576
de941241 SG	577	mmc->f_min = 400000;
bbbc1ae9 JS	578
	579	if (f_max != 0)
	580	mmc->f_max = f_max;
	581	else {
	582	if (mmc->host_caps & MMC_MODE_HS) {
	583	if (mmc->host_caps & MMC_MODE_HS_52MHz)
	584	mmc->f_max = 52000000;
	585	else
	586	mmc->f_max = 26000000;
	587	} else
	588	mmc->f_max = 20000000;
	589	}
de941241	590
8feafcc4 JR	591	mmc->b_max = 0;
8feafcc4 JR	592
4ca9244d JR	593	#if defined(CONFIG_OMAP34XX)
	594	/*
	595	* Silicon revs 2.1 and older do not support multiblock transfers.
	596	*/
	597	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
	598	mmc->b_max = 1;
	599	#endif
	600
de941241 SG	601	mmc_register(mmc);
	602
	603	return 0;
	604	}