[J-u-boot.git] / drivers / mmc / omap_hsmmc.c

/*
 * (C) Copyright 2008
 * Texas Instruments, <www.ti.com>
 * Sukumar Ghorai <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation's version 2 of
 * the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <mmc.h>
#include <part.h>
#include <i2c.h>
#include <twl4030.h>
#include <twl6030.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>

/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS	1000

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
			unsigned int siz);
static struct mmc hsmmc_dev[2];

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
	u32 value = 0;
	struct omap4_sys_ctrl_regs *const ctrl =
		(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;


	value = readl(&ctrl->control_pbiaslite);
	value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
	writel(value, &ctrl->control_pbiaslite);
	/* set VMMC to 3V */
	twl6030_power_mmc_init();
	value = readl(&ctrl->control_pbiaslite);
	value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
	writel(value, &ctrl->control_pbiaslite);
}
#endif

unsigned char mmc_board_init(struct mmc *mmc)
{
#if defined(CONFIG_TWL4030_POWER)
	twl4030_power_mmc_init();
#endif

#if defined(CONFIG_OMAP34XX)
	t2_t *t2_base = (t2_t *)T2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
		PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
		&t2_base->pbias_lite);

	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
		&t2_base->devconf0);

	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
		&t2_base->devconf1);

	/* Change from default of 52MHz to 26MHz if necessary */
	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
		writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
			&t2_base->ctl_prog_io1);

	writel(readl(&prcm_base->fclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->fclken1_core);

	writel(readl(&prcm_base->iclken1_core) |
		EN_MMC1 | EN_MMC2 | EN_MMC3,
		&prcm_base->iclken1_core);
#endif

#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	/* PBIAS config needed for MMC1 only */
	if (mmc->block_dev.dev == 0)
		omap4_vmmc_pbias_config(mmc);
#endif

	return 0;
}

void mmc_init_stream(struct hsmmc *mmc_base)
{
	ulong start;

	writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con);

	writel(MMC_CMD0, &mmc_base->cmd);
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc!\n", __func__);
			return;
		}
	}
	writel(CC_MASK, &mmc_base->stat)
		;
	writel(MMC_CMD0, &mmc_base->cmd)
		;
	start = get_timer(0);
	while (!(readl(&mmc_base->stat) & CC_MASK)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
}


static int mmc_init_setup(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int reg_val;
	unsigned int dsor;
	ulong start;

	mmc_board_init(mmc);

	writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
		&mmc_base->sysconfig);
	start = get_timer(0);
	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for cc2!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for softresetall!\n",
				__func__);
			return TIMEOUT;
		}
	}
	writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl);
	writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP,
		&mmc_base->capa);

	reg_val = readl(&mmc_base->con) & RESERVED_MASK;

	writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH |
		MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK |
		HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con);

	dsor = 240;
	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
		(ICE_STOP | DTO_15THDTO | CEN_DISABLE));
	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
		(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return TIMEOUT;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);

	writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl);

	writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE |
		IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC,
		&mmc_base->ie);

	mmc_init_stream(mmc_base);

	return 0;
}


static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
			struct mmc_data *data)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int flags, mmc_stat;
	ulong start;

	start = get_timer(0);
	while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting on cmd inhibit to clear\n",
					__func__);
			return TIMEOUT;
		}
	}
	writel(0xFFFFFFFF, &mmc_base->stat);
	start = get_timer(0);
	while (readl(&mmc_base->stat)) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for stat!\n", __func__);
			return TIMEOUT;
		}
	}
	/*
	 * CMDREG
	 * CMDIDX[13:8]	: Command index
	 * DATAPRNT[5]	: Data Present Select
	 * ENCMDIDX[4]	: Command Index Check Enable
	 * ENCMDCRC[3]	: Command CRC Check Enable
	 * RSPTYP[1:0]
	 *	00 = No Response
	 *	01 = Length 136
	 *	10 = Length 48
	 *	11 = Length 48 Check busy after response
	 */
	/* Delay added before checking the status of frq change
	 * retry not supported by mmc.c(core file)
	 */
	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
		udelay(50000); /* wait 50 ms */

	if (!(cmd->resp_type & MMC_RSP_PRESENT))
		flags = 0;
	else if (cmd->resp_type & MMC_RSP_136)
		flags = RSP_TYPE_LGHT136 | CICE_NOCHECK;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		flags = RSP_TYPE_LGHT48B;
	else
		flags = RSP_TYPE_LGHT48;

	/* enable default flags */
	flags =	flags | (CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK |
			MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE);

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= CCCE_CHECK;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		flags |= CICE_CHECK;

	if (data) {
		if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) ||
			 (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
			flags |= (MSBS_MULTIBLK | BCE_ENABLE);
			data->blocksize = 512;
			writel(data->blocksize | (data->blocks << 16),
							&mmc_base->blk);
		} else
			writel(data->blocksize | NBLK_STPCNT, &mmc_base->blk);

		if (data->flags & MMC_DATA_READ)
			flags |= (DP_DATA | DDIR_READ);
		else
			flags |= (DP_DATA | DDIR_WRITE);
	}

	writel(cmd->cmdarg, &mmc_base->arg);
	writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);

	start = get_timer(0);
	do {
		mmc_stat = readl(&mmc_base->stat);
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s : timeout: No status update\n", __func__);
			return TIMEOUT;
		}
	} while (!mmc_stat);

	if ((mmc_stat & IE_CTO) != 0)
		return TIMEOUT;
	else if ((mmc_stat & ERRI_MASK) != 0)
		return -1;

	if (mmc_stat & CC_MASK) {
		writel(CC_MASK, &mmc_base->stat);
		if (cmd->resp_type & MMC_RSP_PRESENT) {
			if (cmd->resp_type & MMC_RSP_136) {
				/* response type 2 */
				cmd->response[3] = readl(&mmc_base->rsp10);
				cmd->response[2] = readl(&mmc_base->rsp32);
				cmd->response[1] = readl(&mmc_base->rsp54);
				cmd->response[0] = readl(&mmc_base->rsp76);
			} else
				/* response types 1, 1b, 3, 4, 5, 6 */
				cmd->response[0] = readl(&mmc_base->rsp10);
		}
	}

	if (data && (data->flags & MMC_DATA_READ)) {
		mmc_read_data(mmc_base,	data->dest,
				data->blocksize * data->blocks);
	} else if (data && (data->flags & MMC_DATA_WRITE)) {
		mmc_write_data(mmc_base, data->src,
				data->blocksize * data->blocks);
	}
	return 0;
}

static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
	unsigned int *output_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BRR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);
			for (k = 0; k < count; k++) {
				*output_buf = readl(&mmc_base->data);
				output_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BWR_MASK)
			writel(readl(&mmc_base->stat) | BWR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
				unsigned int size)
{
	unsigned int *input_buf = (unsigned int *)buf;
	unsigned int mmc_stat;
	unsigned int count;

	/*
	 * Start Polled Read
	 */
	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	count /= 4;

	while (size) {
		ulong start = get_timer(0);
		do {
			mmc_stat = readl(&mmc_base->stat);
			if (get_timer(0) - start > MAX_RETRY_MS) {
				printf("%s: timedout waiting for status!\n",
						__func__);
				return TIMEOUT;
			}
		} while (mmc_stat == 0);

		if ((mmc_stat & ERRI_MASK) != 0)
			return 1;

		if (mmc_stat & BWR_MASK) {
			unsigned int k;

			writel(readl(&mmc_base->stat) | BWR_MASK,
					&mmc_base->stat);
			for (k = 0; k < count; k++) {
				writel(*input_buf, &mmc_base->data);
				input_buf++;
			}
			size -= (count*4);
		}

		if (mmc_stat & BRR_MASK)
			writel(readl(&mmc_base->stat) | BRR_MASK,
				&mmc_base->stat);

		if (mmc_stat & TC_MASK) {
			writel(readl(&mmc_base->stat) | TC_MASK,
				&mmc_base->stat);
			break;
		}
	}
	return 0;
}

static void mmc_set_ios(struct mmc *mmc)
{
	struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
	unsigned int dsor = 0;
	ulong start;

	/* configue bus width */
	switch (mmc->bus_width) {
	case 8:
		writel(readl(&mmc_base->con) | DTW_8_BITMODE,
			&mmc_base->con);
		break;

	case 4:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) | DTW_4_BITMODE,
			&mmc_base->hctl);
		break;

	case 1:
	default:
		writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
			&mmc_base->con);
		writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
			&mmc_base->hctl);
		break;
	}

	/* configure clock with 96Mhz system clock.
	 */
	if (mmc->clock != 0) {
		dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
		if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
			dsor++;
	}

	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK),
				(ICE_STOP | DTO_15THDTO | CEN_DISABLE));

	mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK,
				(dsor << CLKD_OFFSET) | ICE_OSCILLATE);

	start = get_timer(0);
	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
		if (get_timer(0) - start > MAX_RETRY_MS) {
			printf("%s: timedout waiting for ics!\n", __func__);
			return;
		}
	}
	writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}

int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
{
	struct mmc *mmc;

	mmc = &hsmmc_dev[dev_index];

	sprintf(mmc->name, "OMAP SD/MMC");
	mmc->send_cmd = mmc_send_cmd;
	mmc->set_ios = mmc_set_ios;
	mmc->init = mmc_init_setup;
	mmc->getcd = NULL;

	switch (dev_index) {
	case 0:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		break;
#ifdef OMAP_HSMMC2_BASE
	case 1:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
		break;
#endif
#ifdef OMAP_HSMMC3_BASE
	case 2:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
		break;
#endif
	default:
		mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
		return 1;
	}
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
	mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
				MMC_MODE_HC) & ~host_caps_mask;

	mmc->f_min = 400000;

	if (f_max != 0)
		mmc->f_max = f_max;
	else {
		if (mmc->host_caps & MMC_MODE_HS) {
			if (mmc->host_caps & MMC_MODE_HS_52MHz)
				mmc->f_max = 52000000;
			else
				mmc->f_max = 26000000;
		} else
			mmc->f_max = 20000000;
	}

	mmc->b_max = 0;

#if defined(CONFIG_OMAP34XX)
	/*
	 * Silicon revs 2.1 and older do not support multiblock transfers.
	 */
	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
		mmc->b_max = 1;
#endif

	mmc_register(mmc);

	return 0;
}
Commit	Line	Data
de941241 SG	1	/*
	2	* (C) Copyright 2008
	3	* Texas Instruments, <www.ti.com>
	4	* Sukumar Ghorai <[email protected]>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation's version 2 of
	12	* the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <config.h>
	26	#include <common.h>
	27	#include <mmc.h>
	28	#include <part.h>
	29	#include <i2c.h>
	30	#include <twl4030.h>
14fa2dd0	31	#include <twl6030.h>
de941241 SG	32	#include <asm/io.h>
de941241 SG	33	#include <asm/arch/mmc_host_def.h>
96e0e7b3	34	#include <asm/arch/sys_proto.h>
de941241	35
eb9a28f6 NM	36	/* If we fail after 1 second wait, something is really bad */
	37	#define MAX_RETRY_MS 1000
	38
933efe64 S	39	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size);
	40	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
	41	unsigned int siz);
de941241	42	static struct mmc hsmmc_dev[2];
14fa2dd0 B	43
	44	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	45	static void omap4_vmmc_pbias_config(struct mmc *mmc)
	46	{
	47	u32 value = 0;
	48	struct omap4_sys_ctrl_regs *const ctrl =
	49	(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
	50
	51
	52	value = readl(&ctrl->control_pbiaslite);
	53	value &= ~(MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ);
	54	writel(value, &ctrl->control_pbiaslite);
	55	/* set VMMC to 3V */
	56	twl6030_power_mmc_init();
	57	value = readl(&ctrl->control_pbiaslite);
	58	value \|= MMC1_PBIASLITE_VMODE \| MMC1_PBIASLITE_PWRDNZ \| MMC1_PWRDNZ;
	59	writel(value, &ctrl->control_pbiaslite);
	60	}
	61	#endif
	62
	63	unsigned char mmc_board_init(struct mmc *mmc)
de941241 SG	64	{
	65	#if defined(CONFIG_TWL4030_POWER)
	66	twl4030_power_mmc_init();
	67	#endif
	68
	69	#if defined(CONFIG_OMAP34XX)
	70	t2_t t2_base = (t2_t )T2_BASE;
	71	struct prcm prcm_base = (struct prcm )PRCM_BASE;
	72
	73	writel(readl(&t2_base->pbias_lite) \| PBIASLITEPWRDNZ1 \|
	74	PBIASSPEEDCTRL0 \| PBIASLITEPWRDNZ0,
	75	&t2_base->pbias_lite);
	76
	77	writel(readl(&t2_base->devconf0) \| MMCSDIO1ADPCLKISEL,
	78	&t2_base->devconf0);
	79
	80	writel(readl(&t2_base->devconf1) \| MMCSDIO2ADPCLKISEL,
	81	&t2_base->devconf1);
	82
bbbc1ae9 JS	83	/* Change from default of 52MHz to 26MHz if necessary */
	84	if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
	85	writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
	86	&t2_base->ctl_prog_io1);
	87
de941241 SG	88	writel(readl(&prcm_base->fclken1_core) \|
	89	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	90	&prcm_base->fclken1_core);
	91
	92	writel(readl(&prcm_base->iclken1_core) \|
	93	EN_MMC1 \| EN_MMC2 \| EN_MMC3,
	94	&prcm_base->iclken1_core);
	95	#endif
	96
14fa2dd0 B	97	#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
	98	/* PBIAS config needed for MMC1 only */
	99	if (mmc->block_dev.dev == 0)
	100	omap4_vmmc_pbias_config(mmc);
	101	#endif
de941241 SG	102
	103	return 0;
	104	}
	105
933efe64	106	void mmc_init_stream(struct hsmmc *mmc_base)
de941241	107	{
eb9a28f6	108	ulong start;
de941241 SG	109
	110	writel(readl(&mmc_base->con) \| INIT_INITSTREAM, &mmc_base->con);
	111
	112	writel(MMC_CMD0, &mmc_base->cmd);
eb9a28f6 NM	113	start = get_timer(0);
	114	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	115	if (get_timer(0) - start > MAX_RETRY_MS) {
	116	printf("%s: timedout waiting for cc!\n", __func__);
	117	return;
	118	}
	119	}
de941241 SG	120	writel(CC_MASK, &mmc_base->stat)
	121	;
	122	writel(MMC_CMD0, &mmc_base->cmd)
	123	;
eb9a28f6 NM	124	start = get_timer(0);
	125	while (!(readl(&mmc_base->stat) & CC_MASK)) {
	126	if (get_timer(0) - start > MAX_RETRY_MS) {
	127	printf("%s: timedout waiting for cc2!\n", __func__);
	128	return;
	129	}
	130	}
de941241 SG	131	writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con);
	132	}
	133
	134
	135	static int mmc_init_setup(struct mmc *mmc)
	136	{
933efe64	137	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241 SG	138	unsigned int reg_val;
de941241 SG	139	unsigned int dsor;
eb9a28f6	140	ulong start;
de941241	141
14fa2dd0	142	mmc_board_init(mmc);
de941241 SG	143
	144	writel(readl(&mmc_base->sysconfig) \| MMC_SOFTRESET,
	145	&mmc_base->sysconfig);
eb9a28f6 NM	146	start = get_timer(0);
	147	while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
	148	if (get_timer(0) - start > MAX_RETRY_MS) {
	149	printf("%s: timedout waiting for cc2!\n", __func__);
	150	return TIMEOUT;
	151	}
	152	}
de941241	153	writel(readl(&mmc_base->sysctl) \| SOFTRESETALL, &mmc_base->sysctl);
eb9a28f6 NM	154	start = get_timer(0);
	155	while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
	156	if (get_timer(0) - start > MAX_RETRY_MS) {
	157	printf("%s: timedout waiting for softresetall!\n",
	158	__func__);
	159	return TIMEOUT;
	160	}
	161	}
de941241 SG	162	writel(DTW_1_BITMODE \| SDBP_PWROFF \| SDVS_3V0, &mmc_base->hctl);
	163	writel(readl(&mmc_base->capa) \| VS30_3V0SUP \| VS18_1V8SUP,
	164	&mmc_base->capa);
	165
	166	reg_val = readl(&mmc_base->con) & RESERVED_MASK;
	167
	168	writel(CTPL_MMC_SD \| reg_val \| WPP_ACTIVEHIGH \| CDP_ACTIVEHIGH \|
	169	MIT_CTO \| DW8_1_4BITMODE \| MODE_FUNC \| STR_BLOCK \|
	170	HR_NOHOSTRESP \| INIT_NOINIT \| NOOPENDRAIN, &mmc_base->con);
	171
	172	dsor = 240;
	173	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	174	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	175	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	176	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
eb9a28f6 NM	177	start = get_timer(0);
	178	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	179	if (get_timer(0) - start > MAX_RETRY_MS) {
	180	printf("%s: timedout waiting for ics!\n", __func__);
	181	return TIMEOUT;
	182	}
	183	}
de941241 SG	184	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	185
	186	writel(readl(&mmc_base->hctl) \| SDBP_PWRON, &mmc_base->hctl);
	187
	188	writel(IE_BADA \| IE_CERR \| IE_DEB \| IE_DCRC \| IE_DTO \| IE_CIE \|
	189	IE_CEB \| IE_CCRC \| IE_CTO \| IE_BRR \| IE_BWR \| IE_TC \| IE_CC,
	190	&mmc_base->ie);
	191
	192	mmc_init_stream(mmc_base);
	193
	194	return 0;
	195	}
	196
	197
	198	static int mmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	199	struct mmc_data *data)
	200	{
933efe64	201	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	202	unsigned int flags, mmc_stat;
eb9a28f6	203	ulong start;
de941241	204
eb9a28f6	205	start = get_timer(0);
a7778f8f	206	while ((readl(&mmc_base->pstate) & (DATI_MASK \| CMDI_MASK)) != 0) {
eb9a28f6	207	if (get_timer(0) - start > MAX_RETRY_MS) {
a7778f8f TR	208	printf("%s: timedout waiting on cmd inhibit to clear\n",
a7778f8f TR	209	__func__);
eb9a28f6 NM	210	return TIMEOUT;
	211	}
	212	}
de941241	213	writel(0xFFFFFFFF, &mmc_base->stat);
eb9a28f6 NM	214	start = get_timer(0);
	215	while (readl(&mmc_base->stat)) {
	216	if (get_timer(0) - start > MAX_RETRY_MS) {
	217	printf("%s: timedout waiting for stat!\n", __func__);
	218	return TIMEOUT;
	219	}
	220	}
de941241 SG	221	/*
	222	* CMDREG
	223	* CMDIDX[13:8] : Command index
	224	* DATAPRNT[5] : Data Present Select
	225	* ENCMDIDX[4] : Command Index Check Enable
	226	* ENCMDCRC[3] : Command CRC Check Enable
	227	* RSPTYP[1:0]
	228	* 00 = No Response
	229	* 01 = Length 136
	230	* 10 = Length 48
	231	* 11 = Length 48 Check busy after response
	232	*/
	233	/* Delay added before checking the status of frq change
	234	* retry not supported by mmc.c(core file)
	235	*/
	236	if (cmd->cmdidx == SD_CMD_APP_SEND_SCR)
	237	udelay(50000); /* wait 50 ms */
	238
	239	if (!(cmd->resp_type & MMC_RSP_PRESENT))
	240	flags = 0;
	241	else if (cmd->resp_type & MMC_RSP_136)
	242	flags = RSP_TYPE_LGHT136 \| CICE_NOCHECK;
	243	else if (cmd->resp_type & MMC_RSP_BUSY)
	244	flags = RSP_TYPE_LGHT48B;
	245	else
	246	flags = RSP_TYPE_LGHT48;
	247
	248	/* enable default flags */
	249	flags = flags \| (CMD_TYPE_NORMAL \| CICE_NOCHECK \| CCCE_NOCHECK \|
	250	MSBS_SGLEBLK \| ACEN_DISABLE \| BCE_DISABLE \| DE_DISABLE);
	251
	252	if (cmd->resp_type & MMC_RSP_CRC)
	253	flags \|= CCCE_CHECK;
	254	if (cmd->resp_type & MMC_RSP_OPCODE)
	255	flags \|= CICE_CHECK;
	256
	257	if (data) {
	258	if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) \|\|
	259	(cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)) {
	260	flags \|= (MSBS_MULTIBLK \| BCE_ENABLE);
	261	data->blocksize = 512;
	262	writel(data->blocksize \| (data->blocks << 16),
	263	&mmc_base->blk);
	264	} else
	265	writel(data->blocksize \| NBLK_STPCNT, &mmc_base->blk);
	266
	267	if (data->flags & MMC_DATA_READ)
	268	flags \|= (DP_DATA \| DDIR_READ);
	269	else
	270	flags \|= (DP_DATA \| DDIR_WRITE);
	271	}
	272
	273	writel(cmd->cmdarg, &mmc_base->arg);
	274	writel((cmd->cmdidx << 24) \| flags, &mmc_base->cmd);
	275
eb9a28f6	276	start = get_timer(0);
de941241 SG	277	do {
de941241 SG	278	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	279	if (get_timer(0) - start > MAX_RETRY_MS) {
	280	printf("%s : timeout: No status update\n", __func__);
	281	return TIMEOUT;
	282	}
	283	} while (!mmc_stat);
de941241 SG	284
	285	if ((mmc_stat & IE_CTO) != 0)
	286	return TIMEOUT;
	287	else if ((mmc_stat & ERRI_MASK) != 0)
	288	return -1;
	289
	290	if (mmc_stat & CC_MASK) {
	291	writel(CC_MASK, &mmc_base->stat);
	292	if (cmd->resp_type & MMC_RSP_PRESENT) {
	293	if (cmd->resp_type & MMC_RSP_136) {
	294	/* response type 2 */
	295	cmd->response[3] = readl(&mmc_base->rsp10);
	296	cmd->response[2] = readl(&mmc_base->rsp32);
	297	cmd->response[1] = readl(&mmc_base->rsp54);
	298	cmd->response[0] = readl(&mmc_base->rsp76);
	299	} else
	300	/* response types 1, 1b, 3, 4, 5, 6 */
	301	cmd->response[0] = readl(&mmc_base->rsp10);
	302	}
	303	}
	304
	305	if (data && (data->flags & MMC_DATA_READ)) {
	306	mmc_read_data(mmc_base, data->dest,
	307	data->blocksize * data->blocks);
	308	} else if (data && (data->flags & MMC_DATA_WRITE)) {
	309	mmc_write_data(mmc_base, data->src,
	310	data->blocksize * data->blocks);
	311	}
	312	return 0;
	313	}
	314
933efe64	315	static int mmc_read_data(struct hsmmc mmc_base, char buf, unsigned int size)
de941241 SG	316	{
	317	unsigned int output_buf = (unsigned int )buf;
	318	unsigned int mmc_stat;
	319	unsigned int count;
	320
	321	/*
	322	* Start Polled Read
	323	*/
	324	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	325	count /= 4;
	326
	327	while (size) {
eb9a28f6	328	ulong start = get_timer(0);
de941241 SG	329	do {
de941241 SG	330	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	331	if (get_timer(0) - start > MAX_RETRY_MS) {
	332	printf("%s: timedout waiting for status!\n",
	333	__func__);
	334	return TIMEOUT;
	335	}
de941241 SG	336	} while (mmc_stat == 0);
	337
	338	if ((mmc_stat & ERRI_MASK) != 0)
	339	return 1;
	340
	341	if (mmc_stat & BRR_MASK) {
	342	unsigned int k;
	343
	344	writel(readl(&mmc_base->stat) \| BRR_MASK,
	345	&mmc_base->stat);
	346	for (k = 0; k < count; k++) {
	347	*output_buf = readl(&mmc_base->data);
	348	output_buf++;
	349	}
	350	size -= (count*4);
	351	}
	352
	353	if (mmc_stat & BWR_MASK)
	354	writel(readl(&mmc_base->stat) \| BWR_MASK,
	355	&mmc_base->stat);
	356
	357	if (mmc_stat & TC_MASK) {
	358	writel(readl(&mmc_base->stat) \| TC_MASK,
	359	&mmc_base->stat);
	360	break;
	361	}
	362	}
	363	return 0;
	364	}
	365
933efe64 S	366	static int mmc_write_data(struct hsmmc mmc_base, const char buf,
933efe64 S	367	unsigned int size)
de941241 SG	368	{
	369	unsigned int input_buf = (unsigned int )buf;
	370	unsigned int mmc_stat;
	371	unsigned int count;
	372
	373	/*
	374	* Start Polled Read
	375	*/
	376	count = (size > MMCSD_SECTOR_SIZE) ? MMCSD_SECTOR_SIZE : size;
	377	count /= 4;
	378
	379	while (size) {
eb9a28f6	380	ulong start = get_timer(0);
de941241 SG	381	do {
de941241 SG	382	mmc_stat = readl(&mmc_base->stat);
eb9a28f6 NM	383	if (get_timer(0) - start > MAX_RETRY_MS) {
	384	printf("%s: timedout waiting for status!\n",
	385	__func__);
	386	return TIMEOUT;
	387	}
de941241 SG	388	} while (mmc_stat == 0);
	389
	390	if ((mmc_stat & ERRI_MASK) != 0)
	391	return 1;
	392
	393	if (mmc_stat & BWR_MASK) {
	394	unsigned int k;
	395
	396	writel(readl(&mmc_base->stat) \| BWR_MASK,
	397	&mmc_base->stat);
	398	for (k = 0; k < count; k++) {
	399	writel(*input_buf, &mmc_base->data);
	400	input_buf++;
	401	}
	402	size -= (count*4);
	403	}
	404
	405	if (mmc_stat & BRR_MASK)
	406	writel(readl(&mmc_base->stat) \| BRR_MASK,
	407	&mmc_base->stat);
	408
	409	if (mmc_stat & TC_MASK) {
	410	writel(readl(&mmc_base->stat) \| TC_MASK,
	411	&mmc_base->stat);
	412	break;
	413	}
	414	}
	415	return 0;
	416	}
	417
	418	static void mmc_set_ios(struct mmc *mmc)
	419	{
933efe64	420	struct hsmmc mmc_base = (struct hsmmc )mmc->priv;
de941241	421	unsigned int dsor = 0;
eb9a28f6	422	ulong start;
de941241 SG	423
	424	/* configue bus width */
	425	switch (mmc->bus_width) {
	426	case 8:
	427	writel(readl(&mmc_base->con) \| DTW_8_BITMODE,
	428	&mmc_base->con);
	429	break;
	430
	431	case 4:
	432	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	433	&mmc_base->con);
	434	writel(readl(&mmc_base->hctl) \| DTW_4_BITMODE,
	435	&mmc_base->hctl);
	436	break;
	437
	438	case 1:
	439	default:
	440	writel(readl(&mmc_base->con) & ~DTW_8_BITMODE,
	441	&mmc_base->con);
	442	writel(readl(&mmc_base->hctl) & ~DTW_4_BITMODE,
	443	&mmc_base->hctl);
	444	break;
	445	}
	446
	447	/* configure clock with 96Mhz system clock.
	448	*/
	449	if (mmc->clock != 0) {
	450	dsor = (MMC_CLOCK_REFERENCE * 1000000 / mmc->clock);
	451	if ((MMC_CLOCK_REFERENCE * 1000000) / dsor > mmc->clock)
	452	dsor++;
	453	}
	454
	455	mmc_reg_out(&mmc_base->sysctl, (ICE_MASK \| DTO_MASK \| CEN_MASK),
	456	(ICE_STOP \| DTO_15THDTO \| CEN_DISABLE));
	457
	458	mmc_reg_out(&mmc_base->sysctl, ICE_MASK \| CLKD_MASK,
	459	(dsor << CLKD_OFFSET) \| ICE_OSCILLATE);
	460
eb9a28f6 NM	461	start = get_timer(0);
	462	while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
	463	if (get_timer(0) - start > MAX_RETRY_MS) {
	464	printf("%s: timedout waiting for ics!\n", __func__);
	465	return;
	466	}
	467	}
de941241 SG	468	writel(readl(&mmc_base->sysctl) \| CEN_ENABLE, &mmc_base->sysctl);
	469	}
	470
bbbc1ae9	471	int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
de941241 SG	472	{
	473	struct mmc *mmc;
	474
	475	mmc = &hsmmc_dev[dev_index];
	476
	477	sprintf(mmc->name, "OMAP SD/MMC");
	478	mmc->send_cmd = mmc_send_cmd;
	479	mmc->set_ios = mmc_set_ios;
	480	mmc->init = mmc_init_setup;
48972d90	481	mmc->getcd = NULL;
de941241 SG	482
	483	switch (dev_index) {
	484	case 0:
933efe64	485	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241	486	break;
1037d585	487	#ifdef OMAP_HSMMC2_BASE
de941241	488	case 1:
933efe64	489	mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
de941241	490	break;
1037d585 TR	491	#endif
1037d585 TR	492	#ifdef OMAP_HSMMC3_BASE
de941241	493	case 2:
933efe64	494	mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
de941241	495	break;
1037d585	496	#endif
de941241	497	default:
933efe64	498	mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
de941241 SG	499	return 1;
	500	}
	501	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
bbbc1ae9 JS	502	mmc->host_caps = (MMC_MODE_4BIT \| MMC_MODE_HS_52MHz \| MMC_MODE_HS \|
bbbc1ae9 JS	503	MMC_MODE_HC) & ~host_caps_mask;
de941241 SG	504
de941241 SG	505	mmc->f_min = 400000;
bbbc1ae9 JS	506
	507	if (f_max != 0)
	508	mmc->f_max = f_max;
	509	else {
	510	if (mmc->host_caps & MMC_MODE_HS) {
	511	if (mmc->host_caps & MMC_MODE_HS_52MHz)
	512	mmc->f_max = 52000000;
	513	else
	514	mmc->f_max = 26000000;
	515	} else
	516	mmc->f_max = 20000000;
	517	}
de941241	518
8feafcc4 JR	519	mmc->b_max = 0;
8feafcc4 JR	520
4ca9244d JR	521	#if defined(CONFIG_OMAP34XX)
	522	/*
	523	* Silicon revs 2.1 and older do not support multiblock transfers.
	524	*/
	525	if ((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() <= CPU_3XX_ES21))
	526	mmc->b_max = 1;
	527	#endif
	528
de941241 SG	529	mmc_register(mmc);
	530
	531	return 0;
	532	}