[J-u-boot.git] / include / configs / edminiv2.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2010 Albert ARIBAUD <[email protected]>
 *
 * Based on original Kirkwood support which is
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Prafulla Wadaskar <[email protected]>
 */

#ifndef _CONFIG_EDMINIV2_H
#define _CONFIG_EDMINIV2_H

/*
 * SPL
 */

#define CONFIG_SPL_TEXT_BASE		0xffff0000
#define CONFIG_SPL_MAX_SIZE		0x0000fff0
#define CONFIG_SPL_STACK		0x00020000
#define CONFIG_SPL_BSS_START_ADDR	0x00020000
#define CONFIG_SPL_BSS_MAX_SIZE		0x0001ffff
#define CONFIG_SYS_SPL_MALLOC_START	0x00040000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x0001ffff
#define CONFIG_SYS_UBOOT_BASE		0xfff90000
#define CONFIG_SYS_UBOOT_START		0x00800000

/*
 * High Level Configuration Options (easy to change)
 */

#define CONFIG_MARVELL		1
#define CONFIG_FEROCEON		1	/* CPU Core subversion */
#define CONFIG_88F5182		1	/* SOC Name */

#include <asm/arch/orion5x.h>
/*
 * CLKs configurations
 */

/*
 * Board-specific values for Orion5x MPP low level init:
 * - MPPs 12 to 15 are SATA LEDs (mode 5)
 * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
 *   MPP16 to MPP19, mode 0 for others
 */

#define ORION5X_MPP0_7		0x00000003
#define ORION5X_MPP8_15		0x55550000
#define ORION5X_MPP16_23	0x00005555

/*
 * Board-specific values for Orion5x GPIO low level init:
 * - GPIO3 is input (RTC interrupt)
 * - GPIO16 is Power LED control (0 = on, 1 = off)
 * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
 * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
 * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
 * - GPIO22 is SATA disk power status ()
 * - GPIO23 is supply status for SATA disk ()
 * - GPIO24 is supply control for board (write 1 to power off)
 * Last GPIO is 25, further bits are supposed to be 0.
 * Enable mask has ones for INPUT, 0 for OUTPUT.
 * Default is LED ON, board ON :)
 */

#define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
#define ORION5X_GPIO_OUT_VALUE		0x00000000
#define ORION5X_GPIO_IN_POLARITY	0x000000d0

/*
 * NS16550 Configuration
 */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE

/*
 * Serial Port configuration
 * The following definitions let you select what serial you want to use
 * for your console driver.
 */

#define CONFIG_SYS_BAUDRATE_TABLE \
	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }

/*
 * FLASH configuration
 */

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_MAX_FLASH_BANKS	1  /* max num of flash banks       */
#define CONFIG_SYS_MAX_FLASH_SECT	11 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BASE		0xfff80000

/* auto boot */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs  */
#define CONFIG_INITRD_TAG	1	/* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 1	/* enable memory tag */

#define	CONFIG_SYS_CBSIZE	1024	/* Console I/O Buff Size */
/*
 * Commands configuration
 */

/*
 * Network
 */

#ifdef CONFIG_CMD_NET
#define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
#define CONFIG_PHY_BASE_ADR	0x8
#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
#endif

/*
 * IDE
 */
#ifdef CONFIG_IDE
#define __io
#define CONFIG_IDE_PREINIT
/* ED Mini V has an IDE-compatible SATA connector for port 1 */
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE		4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* A single bus, a single device */
#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	1
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR	ORION5X_SATA_BASE
/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
#define CONFIG_SYS_ATA_IDE0_OFFSET	ORION5X_SATA_PORT1_OFFSET
/* end of IDE defines */
#endif /* CMD_IDE */

/*
 * Common USB/EHCI configuration
 */
#ifdef CONFIG_CMD_USB
#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
#endif /* CONFIG_CMD_USB */

/*
 * I2C related stuff
 */
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		ORION5X_TWSI_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000
#endif

/*
 *  Environment variables configurations
 */
#define CONFIG_ENV_SECT_SIZE		0x2000	/* 16K */
#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_ENV_OFFSET		0x4000	/* env starts here */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN	(1024 * 256) /* 256kB for malloc() */

/*
 * Other required minimal configurations
 */
#define CONFIG_ARCH_CPU_INIT		/* call arch_cpu_init() */

#define CONFIG_SYS_LOAD_ADDR		0x00800000
#define CONFIG_SYS_MEMTEST_START	0x00400000
#define CONFIG_SYS_MEMTEST_END		0x007fffff
#define CONFIG_SYS_RESET_ADDRESS	0xffff0000

/* Enable command line editing */

/* provide extensive help */

/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0
#define CONFIG_SYS_INIT_SP_ADDR	\
	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)

#endif /* _CONFIG_EDMINIV2_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
ce9c227c	2	/*
57b4bce9	3	* Copyright (C) 2010 Albert ARIBAUD <[email protected]>
ce9c227c AA	4	*
	5	* Based on original Kirkwood support which is
	6	* (C) Copyright 2009
	7	* Marvell Semiconductor <www.marvell.com>
	8	* Written-by: Prafulla Wadaskar <[email protected]>
ce9c227c AA	9	*/
	10
	11	#ifndef _CONFIG_EDMINIV2_H
	12	#define _CONFIG_EDMINIV2_H
	13
9608e7de AA	14	/*
	15	* SPL
	16	*/
	17
9608e7de AA	18	#define CONFIG_SPL_TEXT_BASE 0xffff0000
	19	#define CONFIG_SPL_MAX_SIZE 0x0000fff0
	20	#define CONFIG_SPL_STACK 0x00020000
	21	#define CONFIG_SPL_BSS_START_ADDR 0x00020000
	22	#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff
	23	#define CONFIG_SYS_SPL_MALLOC_START 0x00040000
	24	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff
9608e7de AA	25	#define CONFIG_SYS_UBOOT_BASE 0xfff90000
9608e7de AA	26	#define CONFIG_SYS_UBOOT_START 0x00800000
9608e7de	27
ce9c227c AA	28	/*
	29	* High Level Configuration Options (easy to change)
	30	*/
	31
	32	#define CONFIG_MARVELL 1
ce9c227c	33	#define CONFIG_FEROCEON 1 /* CPU Core subversion */
ce9c227c	34	#define CONFIG_88F5182 1 /* SOC Name */
ce9c227c	35
5ff8b354	36	#include <asm/arch/orion5x.h>
ce9c227c AA	37	/*
	38	* CLKs configurations
	39	*/
	40
ce9c227c AA	41	/*
	42	* Board-specific values for Orion5x MPP low level init:
	43	* - MPPs 12 to 15 are SATA LEDs (mode 5)
	44	* - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
	45	* MPP16 to MPP19, mode 0 for others
	46	*/
	47
	48	#define ORION5X_MPP0_7 0x00000003
	49	#define ORION5X_MPP8_15 0x55550000
ecaf3af2	50	#define ORION5X_MPP16_23 0x00005555
ce9c227c AA	51
	52	/*
	53	* Board-specific values for Orion5x GPIO low level init:
	54	* - GPIO3 is input (RTC interrupt)
	55	* - GPIO16 is Power LED control (0 = on, 1 = off)
	56	* - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
	57	* - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
491f6c2f AA	58	* - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
	59	* - GPIO22 is SATA disk power status ()
	60	* - GPIO23 is supply status for SATA disk ()
	61	* - GPIO24 is supply control for board (write 1 to power off)
	62	* Last GPIO is 25, further bits are supposed to be 0.
ce9c227c	63	* Enable mask has ones for INPUT, 0 for OUTPUT.
491f6c2f	64	* Default is LED ON, board ON :)
ce9c227c AA	65	*/
ce9c227c AA	66
491f6c2f AA	67	#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca
	68	#define ORION5X_GPIO_OUT_VALUE 0x00000000
	69	#define ORION5X_GPIO_IN_POLARITY 0x000000d0
ce9c227c AA	70
	71	/*
	72	* NS16550 Configuration
	73	*/
	74
ce9c227c AA	75	#define CONFIG_SYS_NS16550_SERIAL
	76	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	77	#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
	78	#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
	79
	80	/*
	81	* Serial Port configuration
	82	* The following definitions let you select what serial you want to use
	83	* for your console driver.
	84	*/
	85
ce9c227c AA	86	#define CONFIG_SYS_BAUDRATE_TABLE \
	87	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
	88
	89	/*
	90	* FLASH configuration
	91	*/
	92
	93	#define CONFIG_SYS_FLASH_CFI
	94	#define CONFIG_FLASH_CFI_DRIVER
ce9c227c AA	95	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	96	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */
	97	#define CONFIG_SYS_FLASH_BASE 0xfff80000
ce9c227c AA	98
ce9c227c AA	99	/* auto boot */
ce9c227c AA	100
	101	/*
	102	* For booting Linux, the board info and command line data
	103	* have to be in the first 8 MB of memory, since this is
	104	* the maximum mapped by the Linux kernel during initialization.
	105	*/
	106	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	107	#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
	108	#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
	109
ce9c227c	110	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
ce9c227c	111	/*
ef0f2f57	112	* Commands configuration
ce9c227c	113	*/
ab9164d0	114
ce9c227c	115	/*
ab9164d0	116	* Network
ce9c227c	117	*/
ab9164d0 AA	118
ab9164d0 AA	119	#ifdef CONFIG_CMD_NET
ab9164d0 AA	120	#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */
	121	#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */
	122	#define CONFIG_PHY_BASE_ADR 0x8
	123	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
	124	#define CONFIG_NETCONSOLE /* include NetConsole support */
ab9164d0 AA	125	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
	126	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
	127	#endif
ce9c227c	128
ecaf3af2 AA	129	/*
	130	* IDE
	131	*/
fc843a02	132	#ifdef CONFIG_IDE
ecaf3af2 AA	133	#define __io
ecaf3af2 AA	134	#define CONFIG_IDE_PREINIT
ecaf3af2	135	/* ED Mini V has an IDE-compatible SATA connector for port 1 */
ecaf3af2 AA	136	#define CONFIG_MVSATA_IDE_USE_PORT1
	137	/* Needs byte-swapping for ATA data register */
	138	#define CONFIG_IDE_SWAP_IO
	139	/* Data, registers and alternate blocks are at the same offset */
	140	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
	141	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
	142	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
	143	/* Each 8-bit ATA register is aligned to a 4-bytes address */
	144	#define CONFIG_SYS_ATA_STRIDE 4
	145	/* Controller supports 48-bits LBA addressing */
	146	#define CONFIG_LBA48
	147	/* A single bus, a single device */
	148	#define CONFIG_SYS_IDE_MAXBUS 1
	149	#define CONFIG_SYS_IDE_MAXDEVICE 1
	150	/* ATA registers base is at SATA controller base */
	151	#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE
	152	/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
	153	#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET
	154	/* end of IDE defines */
	155	#endif /* CMD_IDE */
	156
81a6c009 AA	157	/*
	158	* Common USB/EHCI configuration
	159	*/
	160	#ifdef CONFIG_CMD_USB
81a6c009	161	#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
81a6c009 AA	162	#endif /* CONFIG_CMD_USB */
81a6c009 AA	163
c2ca44c2 AA	164	/*
	165	* I2C related stuff
	166	*/
	167	#ifdef CONFIG_CMD_I2C
0db2bbdc HG	168	#define CONFIG_SYS_I2C
0db2bbdc HG	169	#define CONFIG_SYS_I2C_MVTWSI
dd82242b	170	#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE
c2ca44c2 AA	171	#define CONFIG_SYS_I2C_SLAVE 0x0
	172	#define CONFIG_SYS_I2C_SPEED 100000
	173	#endif
	174
ce9c227c AA	175	/*
	176	* Environment variables configurations
	177	*/
ce9c227c AA	178	#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
	179	#define CONFIG_ENV_SIZE 0x2000
	180	#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
	181
	182	/*
	183	* Size of malloc() pool
	184	*/
84fb04b6	185	#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */
ce9c227c AA	186
	187	/*
	188	* Other required minimal configurations
	189	*/
ce9c227c	190	#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
ce9c227c	191
ce9c227c AA	192	#define CONFIG_SYS_LOAD_ADDR 0x00800000
	193	#define CONFIG_SYS_MEMTEST_START 0x00400000
	194	#define CONFIG_SYS_MEMTEST_END 0x007fffff
	195	#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
ce9c227c	196
a203a7c8	197	/* Enable command line editing */
a203a7c8 AA	198
a203a7c8 AA	199	/* provide extensive help */
a203a7c8	200
0693923c AA	201	/* additions for new relocation code, must be added to all boards */
	202	#define CONFIG_SYS_SDRAM_BASE 0
	203	#define CONFIG_SYS_INIT_SP_ADDR \
25ddd1fb	204	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
0693923c	205
ce9c227c	206	#endif /* _CONFIG_EDMINIV2_H */