[J-u-boot.git] / board / esd / pmc440 / cmd_pmc440.c

/*
 * (C) Copyright 2007-2008
 * Matthias Fuchs, esd Gmbh, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/processor.h>
#if defined(CONFIG_LOGBUFFER)
#include <logbuff.h>
#endif

#include "pmc440.h"

int is_monarch(void);
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
			   uchar *buffer, unsigned cnt);
int eeprom_write_enable(unsigned dev_addr, int state);

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_CMD_BSP)

static int got_fifoirq;
static int got_hcirq;

int fpga_interrupt(u32 arg)
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
	int rc = -1; /* not for us */
	u32 status = FPGA_IN32(&fpga->status);

	/* check for interrupt from fifo module */
	if (status & STATUS_FIFO_ISF) {
		/* disable this int source */
		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
		rc = 0;
		got_fifoirq = 1; /* trigger backend */
	}

	if (status & STATUS_HOST_ISF) {
		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
		rc = 0;
		got_hcirq = 1;
	}

	return rc;
}

int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;

	got_hcirq = 0;

	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);

	irq_install_handler(IRQ0_FPGA,
			    (interrupt_handler_t *)fpga_interrupt,
			    fpga);

	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);

	while (!got_hcirq) {
		/* Abort if ctrl-c was pressed */
		if (ctrlc()) {
			puts("\nAbort\n");
			break;
		}
	}
	if (got_hcirq)
		printf("Got interrupt!\n");

	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	irq_free_handler(IRQ0_FPGA);
	return 0;
}
U_BOOT_CMD(
	waithci,	1,	1,	do_waithci,
	"Wait for host control interrupt",
	""
);

void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
{
	u32 ctrl;

	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
		printf("%5d  %d    %3d  %08x",
		       (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
		       FPGA_IN32(&fpga->fifo[f].data));
		if (ctrl & FIFO_OVERFLOW) {
			printf(" OVERFLOW\n");
			FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
		} else
			printf("\n");
	}
}

int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
	int i;
	int n = 0;
	u32 ctrl, data, f;
	char str[] = "\\|/-";
	int abort = 0;
	int count = 0;
	int count2 = 0;

	switch (argc) {
	case 1:
		/* print all fifos status information */
		printf("fifo level status\n");
		printf("______________________________\n");
		for (i=0; i<FIFO_COUNT; i++) {
			ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
			printf(" %d    %3d  %s%s%s %s\n",
			       i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
			       ctrl & FIFO_FULL ? "FULL     " : "",
			       ctrl & FIFO_EMPTY ? "EMPTY    " : "",
			       ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
			       ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
		}
		break;

	case 2:
		/* completely read out fifo 'n' */
		if (!strcmp(argv[1],"read")) {
			printf("  #   fifo level data\n");
			printf("______________________________\n");

			for (i=0; i<FIFO_COUNT; i++)
				dump_fifo(fpga, i, &n);

		} else if (!strcmp(argv[1],"wait")) {
			got_fifoirq = 0;

			irq_install_handler(IRQ0_FPGA,
					    (interrupt_handler_t *)fpga_interrupt,
					    fpga);

			printf("  #   fifo level data\n");
			printf("______________________________\n");

			/* enable all fifo interrupts */
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
			for (i=0; i<FIFO_COUNT; i++) {
				/* enable interrupts from all fifos */
				FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
			}

			while (1) {
				/* wait loop */
				while (!got_fifoirq) {
					count++;
					if (!(count % 100)) {
						count2++;
						putc(0x08); /* backspace */
						putc(str[count2 % 4]);
					}

					/* Abort if ctrl-c was pressed */
					if ((abort = ctrlc())) {
						puts("\nAbort\n");
						break;
					}
					udelay(1000);
				}
				if (abort)
					break;

				/* simple fifo backend */
				if (got_fifoirq) {
					for (i=0; i<FIFO_COUNT; i++)
						dump_fifo(fpga, i, &n);

					got_fifoirq = 0;
					/* unmask global fifo irq */
					FPGA_OUT32(&fpga->hostctrl,
						   HOSTCTRL_FIFOIE_GATE |
						   HOSTCTRL_FIFOIE_FLAG);
				}
			}

			/* disable all fifo interrupts */
			FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
			for (i=0; i<FIFO_COUNT; i++)
				FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);

			irq_free_handler(IRQ0_FPGA);

		} else {
			printf("Usage:\nfifo %s\n", cmdtp->help);
			return 1;
		}
		break;

	case 4:
	case 5:
		if (!strcmp(argv[1],"write")) {
			/* get fifo number or fifo address */
			f = simple_strtoul(argv[2], NULL, 16);

			/* data paramter */
			data = simple_strtoul(argv[3], NULL, 16);

			/* get optional count parameter */
			n = 1;
			if (argc >= 5)
				n = (int)simple_strtoul(argv[4], NULL, 10);

			if (f < FIFO_COUNT) {
				printf("writing %d x %08x to fifo %d\n",
				       n, data, f);
				for (i=0; i<n; i++)
					FPGA_OUT32(&fpga->fifo[f].data, data);
			} else {
				printf("writing %d x %08x to fifo port at "
				       "address %08x\n",
				       n, data, f);
				for (i=0; i<n; i++)
					out_be32((void *)f, data);
			}
		} else {
			printf("Usage:\nfifo %s\n", cmdtp->help);
			return 1;
		}
		break;

	default:
		printf("Usage:\nfifo %s\n", cmdtp->help);
		return 1;
	}
	return 0;
}
U_BOOT_CMD(
	fifo,	5,	1,	do_fifo,
	"Fifo module operations",
	"wait\nfifo read\n"
	"fifo write fifo(0..3) data [cnt=1]\n"
	"fifo write address(>=4) data [cnt=1]\n"
	"  - without arguments: print all fifo's status\n"
	"  - with 'wait' argument: interrupt driven read from all fifos\n"
	"  - with 'read' argument: read current contents from all fifos\n"
	"  - with 'write' argument: write 'data' 'cnt' times to "
	"'fifo' or 'address'"
);

int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong sdsdp[5];
	ulong delay;
	int count=16;

	if (argc < 2) {
		printf("Usage:\nsbe %s\n", cmdtp->help);
		return -1;
	}

	if (argc > 1) {
		if (!strcmp(argv[1], "400")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 400MHz\n");
			sdsdp[0]=0x8678624e;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else if (!strcmp(argv[1], "533")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 533MHz\n");
			sdsdp[0]=0x87788252;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else if (!strcmp(argv[1], "667")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 667MHz\n");
			sdsdp[0]=0x8778a256;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else {
			printf("Usage:\nsbe %s\n", cmdtp->help);
			return -1;
		}
	}

	if (argc > 2) {
		sdsdp[4] = 0;
		if (argv[2][0]=='1')
			sdsdp[4]=0x19750100;
		else if (argv[2][0]=='0')
			sdsdp[4]=0x19750000;
		if (sdsdp[4])
			count += 4;
	}

	if (argc > 3) {
		delay = simple_strtoul(argv[3], NULL, 10);
		if (delay > 20)
			delay = 20;
		sdsdp[4] |= delay;
	}

	printf("Writing boot EEPROM ...\n");
	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
				   0, (uchar*)sdsdp, count) != 0)
		printf("bootstrap_eeprom_write failed\n");
	else
		printf("done (dump via 'i2c md 52 0.1 14')\n");

	return 0;
}
U_BOOT_CMD(
	sbe, 4, 0, do_setup_bootstrap_eeprom,
	"setup bootstrap eeprom",
	"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
);

#if defined(CONFIG_PRAM)
#include <environment.h>
#include <search.h>
#include <errno.h>

int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	u32 pram, nextbase, base;
	char *v;
	u32 param;
	ulong *lptr;

	env_t *envp;
	char *res;
	int len;

	v = getenv("pram");
	if (v)
		pram = simple_strtoul(v, NULL, 10);
	else {
		printf("Error: pram undefined. Please define pram in KiB\n");
		return 1;
	}

	base = gd->bd->bi_memsize;
#if defined(CONFIG_LOGBUFFER)
	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
#endif
	/*
	 * gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
	 */
	param = base - (pram << 10);
	printf("PARAM: @%08x\n", param);
	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);

	/* clear entire PA ram */
	memset((void*)param, 0, (pram << 10));

	/* reserve 4k for pointer field */
	nextbase = base - 4096;
	lptr = (ulong*)(base);

	/*
	 * *(--lptr) = item_size;
	 * *(--lptr) = base - item_base = distance from field top;
	 */

	/* env is first (4k aligned) */
	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
	envp = (env_t *)nextbase;
	res = (char *)envp->data;
	len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
	if (len < 0) {
		error("Cannot export environment: errno = %d\n", errno);
		return 1;
	}
	envp->crc = crc32(0, envp->data, ENV_SIZE);

	*(--lptr) = CONFIG_ENV_SIZE;     /* size */
	*(--lptr) = base - nextbase;  /* offset | type=0 */

	/* free section */
	*(--lptr) = nextbase - param; /* size */
	*(--lptr) = (base - param) | 126; /* offset | type=126 */

	/* terminate pointer field */
	*(--lptr) = crc32(0, (void*)(base - 0x10), 0x10);
	*(--lptr) = 0;                /* offset=0 -> terminator */
	return 0;
}
U_BOOT_CMD(
	painit,	1,	1,	do_painit,
	"prepare PciAccess system",
	""
);
#endif /* CONFIG_PRAM */

int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	in_be32((void*)CONFIG_SYS_RESET_BASE);
	return 0;
}
U_BOOT_CMD(
	selfreset,	1,	1,	do_selfreset,
	"assert self-reset# signal",
	""
);

int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;

	/* requiers bootet FPGA and PLD_IOEN_N active */
	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
		printf("Error: resetout requires a bootet FPGA\n");
		return -1;
	}

	if (argc > 1) {
		if (argv[1][0] == '0') {
			/* assert */
			printf("PMC-RESETOUT# asserted\n");
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_PMCRSTOUT_GATE);
		} else {
			/* deassert */
			printf("PMC-RESETOUT# deasserted\n");
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_PMCRSTOUT_GATE |
				   HOSTCTRL_PMCRSTOUT_FLAG);
		}
	} else {
		printf("PMC-RESETOUT# is %s\n",
		       FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
		       "inactive" : "active");
	}

	return 0;
}
U_BOOT_CMD(
	resetout,	2,	1,	do_resetout,
	"assert PMC-RESETOUT# signal",
	""
);

int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	if (is_monarch()) {
		printf("This command is only supported in non-monarch mode\n");
		return -1;
	}

	if (argc > 1) {
		if (argv[1][0] == '0') {
			/* assert */
			printf("inta# asserted\n");
			out_be32((void*)GPIO1_TCR,
				 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
		} else {
			/* deassert */
			printf("inta# deasserted\n");
			out_be32((void*)GPIO1_TCR,
				 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
		}
	} else {
		printf("inta# is %s\n",
		       in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
		       "active" : "inactive");
	}
	return 0;
}
U_BOOT_CMD(
	inta,	2,	1,	do_inta,
	"Assert/Deassert or query INTA# state in non-monarch mode",
	""
);

/* test-only */
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong pciaddr;

	if (argc > 1) {
		pciaddr = simple_strtoul(argv[1], NULL, 16);

		pciaddr &= 0xf0000000;

		/* map PCI address at 0xc0000000 in PLB space */

		/* PMM1 Mask/Attribute - disabled b4 setting */
		out32r(PCIL0_PMM1MA, 0x00000000);
		/* PMM1 Local Address */
		out32r(PCIL0_PMM1LA, 0xc0000000);
		/* PMM1 PCI Low Address */
		out32r(PCIL0_PMM1PCILA, pciaddr);
		/* PMM1 PCI High Address */
		out32r(PCIL0_PMM1PCIHA, 0x00000000);
		/* 256MB + No prefetching, and enable region */
		out32r(PCIL0_PMM1MA, 0xf0000001);
	} else {
		printf("Usage:\npmm %s\n", cmdtp->help);
	}
	return 0;
}
U_BOOT_CMD(
	pmm,	2,	1,	do_pmm,
	"Setup pmm[1] registers",
	"<pciaddr> (pciaddr will be aligned to 256MB)"
);

#if defined(CONFIG_SYS_EEPROM_WREN)
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	int query = argc == 1;
	int state = 0;

	if (query) {
		/* Query write access state. */
		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
		if (state < 0) {
			puts("Query of write access state failed.\n");
		} else {
			printf("Write access for device 0x%0x is %sabled.\n",
			       CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
			state = 0;
		}
	} else {
		if ('0' == argv[1][0]) {
			/* Disable write access. */
			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
		} else {
			/* Enable write access. */
			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
		}
		if (state < 0) {
			puts("Setup of write access state failed.\n");
		}
	}

	return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
	"Enable / disable / query EEPROM write access",
	""
);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */

#endif /* CONFIG_CMD_BSP */
Commit	Line	Data
407843a5	1	/*
034394ab	2	* (C) Copyright 2007-2008
407843a5 MF	3	* Matthias Fuchs, esd Gmbh, [email protected].
407843a5 MF	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
407843a5	6	*/
407843a5 MF	7	#include <common.h>
	8	#include <command.h>
	9	#include <asm/io.h>
	10	#include <asm/cache.h>
	11	#include <asm/processor.h>
75183b1a MF	12	#if defined(CONFIG_LOGBUFFER)
	13	#include <logbuff.h>
	14	#endif
407843a5 MF	15
	16	#include "pmc440.h"
	17
	18	int is_monarch(void);
034394ab MF	19	int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
034394ab MF	20	uchar *buffer, unsigned cnt);
407843a5 MF	21	int eeprom_write_enable(unsigned dev_addr, int state);
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	#if defined(CONFIG_CMD_BSP)
	26
	27	static int got_fifoirq;
	28	static int got_hcirq;
	29
	30	int fpga_interrupt(u32 arg)
	31	{
	32	pmc440_fpga_t fpga = (pmc440_fpga_t )arg;
	33	int rc = -1; /* not for us */
	34	u32 status = FPGA_IN32(&fpga->status);
	35
	36	/* check for interrupt from fifo module */
	37	if (status & STATUS_FIFO_ISF) {
	38	/* disable this int source */
	39	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
	40	rc = 0;
	41	got_fifoirq = 1; /* trigger backend */
	42	}
	43
	44	if (status & STATUS_HOST_ISF) {
	45	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
	46	rc = 0;
	47	got_hcirq = 1;
	48	}
	49
	50	return rc;
	51	}
	52
54841ab5	53	int do_waithci(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	54	{
	55	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	56
	57	got_hcirq = 0;
	58
	59	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	60	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
	61
	62	irq_install_handler(IRQ0_FPGA,
	63	(interrupt_handler_t *)fpga_interrupt,
	64	fpga);
	65
	66	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
	67
	68	while (!got_hcirq) {
	69	/* Abort if ctrl-c was pressed */
	70	if (ctrlc()) {
	71	puts("\nAbort\n");
	72	break;
	73	}
	74	}
	75	if (got_hcirq)
	76	printf("Got interrupt!\n");
	77
	78	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	79	irq_free_handler(IRQ0_FPGA);
	80	return 0;
	81	}
	82	U_BOOT_CMD(
	83	waithci, 1, 1, do_waithci,
2fb2604d	84	"Wait for host control interrupt",
a89c33db WD	85	""
a89c33db WD	86	);
407843a5	87
407843a5 MF	88	void dump_fifo(pmc440_fpga_t fpga, int f, int n)
	89	{
	90	u32 ctrl;
	91
	92	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
	93	printf("%5d %d %3d %08x",
	94	(*n)++, f, ctrl & (FIFO_LEVEL_MASK \| FIFO_FULL),
	95	FPGA_IN32(&fpga->fifo[f].data));
	96	if (ctrl & FIFO_OVERFLOW) {
	97	printf(" OVERFLOW\n");
	98	FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
	99	} else
	100	printf("\n");
	101	}
	102	}
	103
54841ab5	104	int do_fifo(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	105	{
	106	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	107	int i;
	108	int n = 0;
	109	u32 ctrl, data, f;
	110	char str[] = "\\\|/-";
	111	int abort = 0;
	112	int count = 0;
	113	int count2 = 0;
	114
	115	switch (argc) {
	116	case 1:
	117	/* print all fifos status information */
	118	printf("fifo level status\n");
	119	printf("______________________________\n");
	120	for (i=0; i<FIFO_COUNT; i++) {
	121	ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
	122	printf(" %d %3d %s%s%s %s\n",
	123	i, ctrl & (FIFO_LEVEL_MASK \| FIFO_FULL),
	124	ctrl & FIFO_FULL ? "FULL " : "",
	125	ctrl & FIFO_EMPTY ? "EMPTY " : "",
	126	ctrl & (FIFO_FULL\|FIFO_EMPTY) ? "" : "NOT EMPTY",
	127	ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
	128	}
	129	break;
	130
	131	case 2:
	132	/* completely read out fifo 'n' */
	133	if (!strcmp(argv[1],"read")) {
	134	printf(" # fifo level data\n");
	135	printf("______________________________\n");
	136
	137	for (i=0; i<FIFO_COUNT; i++)
	138	dump_fifo(fpga, i, &n);
	139
	140	} else if (!strcmp(argv[1],"wait")) {
	141	got_fifoirq = 0;
	142
	143	irq_install_handler(IRQ0_FPGA,
	144	(interrupt_handler_t *)fpga_interrupt,
	145	fpga);
	146
	147	printf(" # fifo level data\n");
	148	printf("______________________________\n");
	149
	150	/* enable all fifo interrupts */
	151	FPGA_OUT32(&fpga->hostctrl,
	152	HOSTCTRL_FIFOIE_GATE \| HOSTCTRL_FIFOIE_FLAG);
	153	for (i=0; i<FIFO_COUNT; i++) {
	154	/* enable interrupts from all fifos */
	155	FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
	156	}
	157
	158	while (1) {
	159	/* wait loop */
	160	while (!got_fifoirq) {
	161	count++;
	162	if (!(count % 100)) {
	163	count2++;
	164	putc(0x08); /* backspace */
	165	putc(str[count2 % 4]);
	166	}
	167
	168	/* Abort if ctrl-c was pressed */
169	if ((abort = ctrlc())) {
170	puts("\nAbort\n");
171	break;
172	}
173	udelay(1000);
174	}
175	if (abort)
176	break;
177
178	/* simple fifo backend */
179	if (got_fifoirq) {
180	for (i=0; i<FIFO_COUNT; i++)
181	dump_fifo(fpga, i, &n);
182
183	got_fifoirq = 0;
184	/* unmask global fifo irq */
185	FPGA_OUT32(&fpga->hostctrl,
034394ab MF	186	HOSTCTRL_FIFOIE_GATE \|
034394ab MF	187	HOSTCTRL_FIFOIE_FLAG);
407843a5 MF	188	}
	189	}
	190
	191	/* disable all fifo interrupts */
	192	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
	193	for (i=0; i<FIFO_COUNT; i++)
	194	FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
	195
	196	irq_free_handler(IRQ0_FPGA);
	197
	198	} else {
	199	printf("Usage:\nfifo %s\n", cmdtp->help);
	200	return 1;
	201	}
	202	break;
	203
	204	case 4:
	205	case 5:
	206	if (!strcmp(argv[1],"write")) {
	207	/* get fifo number or fifo address */
	208	f = simple_strtoul(argv[2], NULL, 16);
	209
	210	/* data paramter */
	211	data = simple_strtoul(argv[3], NULL, 16);
	212
	213	/* get optional count parameter */
	214	n = 1;
	215	if (argc >= 5)
	216	n = (int)simple_strtoul(argv[4], NULL, 10);
	217
	218	if (f < FIFO_COUNT) {
	219	printf("writing %d x %08x to fifo %d\n",
	220	n, data, f);
	221	for (i=0; i<n; i++)
	222	FPGA_OUT32(&fpga->fifo[f].data, data);
	223	} else {
034394ab MF	224	printf("writing %d x %08x to fifo port at "
034394ab MF	225	"address %08x\n",
407843a5 MF	226	n, data, f);
407843a5 MF	227	for (i=0; i<n; i++)
bb57ad4b	228	out_be32((void *)f, data);
407843a5 MF	229	}
	230	} else {
	231	printf("Usage:\nfifo %s\n", cmdtp->help);
	232	return 1;
	233	}
	234	break;
	235
	236	default:
	237	printf("Usage:\nfifo %s\n", cmdtp->help);
	238	return 1;
	239	}
	240	return 0;
	241	}
	242	U_BOOT_CMD(
	243	fifo, 5, 1, do_fifo,
2fb2604d	244	"Fifo module operations",
407843a5 MF	245	"wait\nfifo read\n"
	246	"fifo write fifo(0..3) data [cnt=1]\n"
	247	"fifo write address(>=4) data [cnt=1]\n"
	248	" - without arguments: print all fifo's status\n"
	249	" - with 'wait' argument: interrupt driven read from all fifos\n"
	250	" - with 'read' argument: read current contents from all fifos\n"
034394ab	251	" - with 'write' argument: write 'data' 'cnt' times to "
a89c33db WD	252	"'fifo' or 'address'"
a89c33db WD	253	);
407843a5	254
54841ab5	255	int do_setup_bootstrap_eeprom(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	256	{
	257	ulong sdsdp[5];
	258	ulong delay;
	259	int count=16;
	260
	261	if (argc < 2) {
	262	printf("Usage:\nsbe %s\n", cmdtp->help);
	263	return -1;
	264	}
	265
	266	if (argc > 1) {
	267	if (!strcmp(argv[1], "400")) {
ff5fb8a6	268	/* PLB=133MHz, PLB/PCI=3 */
407843a5 MF	269	printf("Bootstrapping for 400MHz\n");
407843a5 MF	270	sdsdp[0]=0x8678624e;
ff5fb8a6	271	sdsdp[1]=0x095fa030;
407843a5 MF	272	sdsdp[2]=0x40082350;
	273	sdsdp[3]=0x0d050000;
	274	} else if (!strcmp(argv[1], "533")) {
	275	/* PLB=133MHz, PLB/PCI=3 */
	276	printf("Bootstrapping for 533MHz\n");
	277	sdsdp[0]=0x87788252;
	278	sdsdp[1]=0x095fa030;
	279	sdsdp[2]=0x40082350;
	280	sdsdp[3]=0x0d050000;
	281	} else if (!strcmp(argv[1], "667")) {
79941d63	282	/* PLB=133MHz, PLB/PCI=3 */
407843a5 MF	283	printf("Bootstrapping for 667MHz\n");
407843a5 MF	284	sdsdp[0]=0x8778a256;
407843a5 MF	285	sdsdp[1]=0x095fa030;
	286	sdsdp[2]=0x40082350;
	287	sdsdp[3]=0x0d050000;
	288	} else {
	289	printf("Usage:\nsbe %s\n", cmdtp->help);
	290	return -1;
	291	}
	292	}
	293
	294	if (argc > 2) {
	295	sdsdp[4] = 0;
	296	if (argv[2][0]=='1')
	297	sdsdp[4]=0x19750100;
	298	else if (argv[2][0]=='0')
	299	sdsdp[4]=0x19750000;
	300	if (sdsdp[4])
	301	count += 4;
	302	}
	303
	304	if (argc > 3) {
	305	delay = simple_strtoul(argv[3], NULL, 10);
	306	if (delay > 20)
	307	delay = 20;
	308	sdsdp[4] \|= delay;
	309	}
	310
	311	printf("Writing boot EEPROM ...\n");
6d0f6bcf	312	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
407843a5 MF	313	0, (uchar*)sdsdp, count) != 0)
	314	printf("bootstrap_eeprom_write failed\n");
	315	else
	316	printf("done (dump via 'i2c md 52 0.1 14')\n");
	317
	318	return 0;
	319	}
	320	U_BOOT_CMD(
	321	sbe, 4, 0, do_setup_bootstrap_eeprom,
2fb2604d	322	"setup bootstrap eeprom",
407843a5	323	"<cpufreq:400\|533\|667> [<console-uart:0\|1> [<bringup delay (0..20s)>]]"
a89c33db	324	);
407843a5	325
407843a5 MF	326	#if defined(CONFIG_PRAM)
407843a5 MF	327	#include <environment.h>
a6569c63 MF	328	#include <search.h>
a6569c63 MF	329	#include <errno.h>
407843a5	330
54841ab5	331	int do_painit(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5	332	{
75183b1a	333	u32 pram, nextbase, base;
407843a5 MF	334	char *v;
	335	u32 param;
	336	ulong *lptr;
	337
a6569c63 MF	338	env_t *envp;
	339	char *res;
	340	int len;
	341
407843a5 MF	342	v = getenv("pram");
	343	if (v)
	344	pram = simple_strtoul(v, NULL, 10);
	345	else {
	346	printf("Error: pram undefined. Please define pram in KiB\n");
	347	return 1;
	348	}
	349
75183b1a MF	350	base = gd->bd->bi_memsize;
	351	#if defined(CONFIG_LOGBUFFER)
	352	base -= LOGBUFF_LEN + LOGBUFF_OVERHEAD;
	353	#endif
	354	/*
3aed3aa2	355	* gd->bd->bi_memsize == physical ram size - CONFIG_SYS_MEM_TOP_HIDE
75183b1a MF	356	*/
75183b1a MF	357	param = base - (pram << 10);
407843a5	358	printf("PARAM: @%08x\n", param);
2bf0758a	359	debug("memsize=0x%08x, base=0x%08x\n", (u32)gd->bd->bi_memsize, base);
407843a5	360
75183b1a	361	/* clear entire PA ram */
407843a5	362	memset((void*)param, 0, (pram << 10));
407843a5	363
75183b1a MF	364	/* reserve 4k for pointer field */
	365	nextbase = base - 4096;
	366	lptr = (ulong*)(base);
	367
	368	/*
	369	* *(--lptr) = item_size;
	370	* *(--lptr) = base - item_base = distance from field top;
	371	*/
	372
	373	/* env is first (4k aligned) */
	374	nextbase -= ((CONFIG_ENV_SIZE + 4096 - 1) & ~(4096 - 1));
a6569c63 MF	375	envp = (env_t *)nextbase;
a6569c63 MF	376	res = (char *)envp->data;
be11235a	377	len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
a6569c63 MF	378	if (len < 0) {
	379	error("Cannot export environment: errno = %d\n", errno);
	380	return 1;
	381	}
	382	envp->crc = crc32(0, envp->data, ENV_SIZE);
	383
75183b1a MF	384	(--lptr) = CONFIG_ENV_SIZE; / size */
75183b1a MF	385	(--lptr) = base - nextbase; / offset \| type=0 */
407843a5	386
75183b1a MF	387	/* free section */
	388	(--lptr) = nextbase - param; / size */
	389	(--lptr) = (base - param) \| 126; / offset \| type=126 */
	390
	391	/* terminate pointer field */
	392	(--lptr) = crc32(0, (void)(base - 0x10), 0x10);
	393	(--lptr) = 0; / offset=0 -> terminator */
407843a5 MF	394	return 0;
	395	}
	396	U_BOOT_CMD(
	397	painit, 1, 1, do_painit,
2fb2604d	398	"prepare PciAccess system",
a89c33db WD	399	""
a89c33db WD	400	);
407843a5 MF	401	#endif /* CONFIG_PRAM */
407843a5 MF	402
54841ab5	403	int do_selfreset(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5	404	{
75183b1a	405	in_be32((void*)CONFIG_SYS_RESET_BASE);
407843a5 MF	406	return 0;
	407	}
	408	U_BOOT_CMD(
75183b1a	409	selfreset, 1, 1, do_selfreset,
2fb2604d	410	"assert self-reset# signal",
a89c33db WD	411	""
a89c33db WD	412	);
407843a5	413
54841ab5	414	int do_resetout(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	415	{
	416	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	417
	418	/* requiers bootet FPGA and PLD_IOEN_N active */
	419	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
	420	printf("Error: resetout requires a bootet FPGA\n");
	421	return -1;
	422	}
	423
	424	if (argc > 1) {
	425	if (argv[1][0] == '0') {
	426	/* assert */
	427	printf("PMC-RESETOUT# asserted\n");
	428	FPGA_OUT32(&fpga->hostctrl,
	429	HOSTCTRL_PMCRSTOUT_GATE);
	430	} else {
	431	/* deassert */
	432	printf("PMC-RESETOUT# deasserted\n");
	433	FPGA_OUT32(&fpga->hostctrl,
034394ab MF	434	HOSTCTRL_PMCRSTOUT_GATE \|
034394ab MF	435	HOSTCTRL_PMCRSTOUT_FLAG);
407843a5 MF	436	}
	437	} else {
	438	printf("PMC-RESETOUT# is %s\n",
	439	FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
	440	"inactive" : "active");
	441	}
	442
	443	return 0;
	444	}
	445	U_BOOT_CMD(
	446	resetout, 2, 1, do_resetout,
2fb2604d	447	"assert PMC-RESETOUT# signal",
a89c33db WD	448	""
a89c33db WD	449	);
407843a5	450
54841ab5	451	int do_inta(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	452	{
	453	if (is_monarch()) {
	454	printf("This command is only supported in non-monarch mode\n");
	455	return -1;
	456	}
	457
	458	if (argc > 1) {
	459	if (argv[1][0] == '0') {
	460	/* assert */
	461	printf("inta# asserted\n");
	462	out_be32((void*)GPIO1_TCR,
	463	in_be32((void*)GPIO1_TCR) \| GPIO1_INTA_FAKE);
	464	} else {
	465	/* deassert */
	466	printf("inta# deasserted\n");
	467	out_be32((void*)GPIO1_TCR,
	468	in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
	469	}
	470	} else {
034394ab MF	471	printf("inta# is %s\n",
	472	in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
	473	"active" : "inactive");
407843a5 MF	474	}
	475	return 0;
	476	}
	477	U_BOOT_CMD(
	478	inta, 2, 1, do_inta,
2fb2604d	479	"Assert/Deassert or query INTA# state in non-monarch mode",
a89c33db WD	480	""
a89c33db WD	481	);
407843a5	482
407843a5	483	/* test-only */
54841ab5	484	int do_pmm(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	485	{
	486	ulong pciaddr;
	487
	488	if (argc > 1) {
	489	pciaddr = simple_strtoul(argv[1], NULL, 16);
	490
	491	pciaddr &= 0xf0000000;
	492
	493	/* map PCI address at 0xc0000000 in PLB space */
034394ab	494
02e38920	495	/* PMM1 Mask/Attribute - disabled b4 setting */
ddc922ff	496	out32r(PCIL0_PMM1MA, 0x00000000);
02e38920	497	/* PMM1 Local Address */
ddc922ff	498	out32r(PCIL0_PMM1LA, 0xc0000000);
02e38920	499	/* PMM1 PCI Low Address */
ddc922ff	500	out32r(PCIL0_PMM1PCILA, pciaddr);
02e38920	501	/* PMM1 PCI High Address */
ddc922ff	502	out32r(PCIL0_PMM1PCIHA, 0x00000000);
02e38920	503	/* 256MB + No prefetching, and enable region */
ddc922ff	504	out32r(PCIL0_PMM1MA, 0xf0000001);
407843a5 MF	505	} else {
	506	printf("Usage:\npmm %s\n", cmdtp->help);
	507	}
	508	return 0;
	509	}
	510	U_BOOT_CMD(
	511	pmm, 2, 1, do_pmm,
2fb2604d	512	"Setup pmm[1] registers",
a89c33db WD	513	"<pciaddr> (pciaddr will be aligned to 256MB)"
a89c33db WD	514	);
407843a5	515
6d0f6bcf	516	#if defined(CONFIG_SYS_EEPROM_WREN)
54841ab5	517	int do_eep_wren(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
407843a5 MF	518	{
	519	int query = argc == 1;
	520	int state = 0;
	521
	522	if (query) {
	523	/* Query write access state. */
6d0f6bcf	524	state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
407843a5 MF	525	if (state < 0) {
	526	puts("Query of write access state failed.\n");
	527	} else {
	528	printf("Write access for device 0x%0x is %sabled.\n",
6d0f6bcf	529	CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
407843a5 MF	530	state = 0;
	531	}
	532	} else {
	533	if ('0' == argv[1][0]) {
	534	/* Disable write access. */
6d0f6bcf	535	state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
407843a5 MF	536	} else {
407843a5 MF	537	/* Enable write access. */
6d0f6bcf	538	state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
407843a5 MF	539	}
	540	if (state < 0) {
	541	puts("Setup of write access state failed.\n");
	542	}
	543	}
	544
	545	return state;
	546	}
	547	U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
a89c33db WD	548	"Enable / disable / query EEPROM write access",
	549	""
	550	);
6d0f6bcf	551	#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
407843a5 MF	552
407843a5 MF	553	#endif /* CONFIG_CMD_BSP */