[J-u-boot.git] / board / esd / pmc440 / cmd_pmc440.c

/*
 * (C) Copyright 2007-2008
 * Matthias Fuchs, esd Gmbh, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/processor.h>

#include "pmc440.h"

int is_monarch(void);
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
			   uchar *buffer, unsigned cnt);
int eeprom_write_enable(unsigned dev_addr, int state);

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_CMD_BSP)

static int got_fifoirq;
static int got_hcirq;

int fpga_interrupt(u32 arg)
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)arg;
	int rc = -1; /* not for us */
	u32 status = FPGA_IN32(&fpga->status);

	/* check for interrupt from fifo module */
	if (status & STATUS_FIFO_ISF) {
		/* disable this int source */
		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
		rc = 0;
		got_fifoirq = 1; /* trigger backend */
	}

	if (status & STATUS_HOST_ISF) {
		FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
		rc = 0;
		got_hcirq = 1;
	}

	return rc;
}

int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;

	got_hcirq = 0;

	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);

	irq_install_handler(IRQ0_FPGA,
			    (interrupt_handler_t *)fpga_interrupt,
			    fpga);

	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);

	while (!got_hcirq) {
		/* Abort if ctrl-c was pressed */
		if (ctrlc()) {
			puts("\nAbort\n");
			break;
		}
	}
	if (got_hcirq)
		printf("Got interrupt!\n");

	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	irq_free_handler(IRQ0_FPGA);
	return 0;
}
U_BOOT_CMD(
	waithci,	1,	1,	do_waithci,
	"waithci - Wait for host control interrupt\n",
	NULL
	);

void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
{
	u32 ctrl;

	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
		printf("%5d  %d    %3d  %08x",
		       (*n)++, f, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
		       FPGA_IN32(&fpga->fifo[f].data));
		if (ctrl & FIFO_OVERFLOW) {
			printf(" OVERFLOW\n");
			FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
		} else
			printf("\n");
	}
}

int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
	int i;
	int n = 0;
	u32 ctrl, data, f;
	char str[] = "\\|/-";
	int abort = 0;
	int count = 0;
	int count2 = 0;

	switch (argc) {
	case 1:
		/* print all fifos status information */
		printf("fifo level status\n");
		printf("______________________________\n");
		for (i=0; i<FIFO_COUNT; i++) {
			ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
			printf(" %d    %3d  %s%s%s %s\n",
			       i, ctrl & (FIFO_LEVEL_MASK | FIFO_FULL),
			       ctrl & FIFO_FULL ? "FULL     " : "",
			       ctrl & FIFO_EMPTY ? "EMPTY    " : "",
			       ctrl & (FIFO_FULL|FIFO_EMPTY) ? "" : "NOT EMPTY",
			       ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
		}
		break;

	case 2:
		/* completely read out fifo 'n' */
		if (!strcmp(argv[1],"read")) {
			printf("  #   fifo level data\n");
			printf("______________________________\n");

			for (i=0; i<FIFO_COUNT; i++)
				dump_fifo(fpga, i, &n);

		} else if (!strcmp(argv[1],"wait")) {
			got_fifoirq = 0;

			irq_install_handler(IRQ0_FPGA,
					    (interrupt_handler_t *)fpga_interrupt,
					    fpga);

			printf("  #   fifo level data\n");
			printf("______________________________\n");

			/* enable all fifo interrupts */
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
			for (i=0; i<FIFO_COUNT; i++) {
				/* enable interrupts from all fifos */
				FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
			}

			while (1) {
				/* wait loop */
				while (!got_fifoirq) {
					count++;
					if (!(count % 100)) {
						count2++;
						putc(0x08); /* backspace */
						putc(str[count2 % 4]);
					}

					/* Abort if ctrl-c was pressed */
					if ((abort = ctrlc())) {
						puts("\nAbort\n");
						break;
					}
					udelay(1000);
				}
				if (abort)
					break;

				/* simple fifo backend */
				if (got_fifoirq) {
					for (i=0; i<FIFO_COUNT; i++)
						dump_fifo(fpga, i, &n);

					got_fifoirq = 0;
					/* unmask global fifo irq */
					FPGA_OUT32(&fpga->hostctrl,
						   HOSTCTRL_FIFOIE_GATE |
						   HOSTCTRL_FIFOIE_FLAG);
				}
			}

			/* disable all fifo interrupts */
			FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
			for (i=0; i<FIFO_COUNT; i++)
				FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);

			irq_free_handler(IRQ0_FPGA);

		} else {
			printf("Usage:\nfifo %s\n", cmdtp->help);
			return 1;
		}
		break;

	case 4:
	case 5:
		if (!strcmp(argv[1],"write")) {
			/* get fifo number or fifo address */
			f = simple_strtoul(argv[2], NULL, 16);

			/* data paramter */
			data = simple_strtoul(argv[3], NULL, 16);

			/* get optional count parameter */
			n = 1;
			if (argc >= 5)
				n = (int)simple_strtoul(argv[4], NULL, 10);

			if (f < FIFO_COUNT) {
				printf("writing %d x %08x to fifo %d\n",
				       n, data, f);
				for (i=0; i<n; i++)
					FPGA_OUT32(&fpga->fifo[f].data, data);
			} else {
				printf("writing %d x %08x to fifo port at "
				       "address %08x\n",
				       n, data, f);
				for (i=0; i<n; i++)
					out32(f, data);
			}
		} else {
			printf("Usage:\nfifo %s\n", cmdtp->help);
			return 1;
		}
		break;

	default:
		printf("Usage:\nfifo %s\n", cmdtp->help);
		return 1;
	}
	return 0;
}
U_BOOT_CMD(
	fifo,	5,	1,	do_fifo,
	"fifo    - Fifo module operations\n",
	"wait\nfifo read\n"
	"fifo write fifo(0..3) data [cnt=1]\n"
	"fifo write address(>=4) data [cnt=1]\n"
	"  - without arguments: print all fifo's status\n"
	"  - with 'wait' argument: interrupt driven read from all fifos\n"
	"  - with 'read' argument: read current contents from all fifos\n"
	"  - with 'write' argument: write 'data' 'cnt' times to "
	"'fifo' or 'address'\n"
	);

int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	ulong sdsdp[5];
	ulong delay;
	int count=16;

	if (argc < 2) {
		printf("Usage:\nsbe %s\n", cmdtp->help);
		return -1;
	}

	if (argc > 1) {
		if (!strcmp(argv[1], "400")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 400MHz\n");
			sdsdp[0]=0x8678624e;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else if (!strcmp(argv[1], "533")) {
			/* PLB=133MHz, PLB/PCI=3 */
			printf("Bootstrapping for 533MHz\n");
			sdsdp[0]=0x87788252;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else if (!strcmp(argv[1], "667")) {
			/* PLB=133MHz, PLB/PCI=4 */
			printf("Bootstrapping for 667MHz\n");
			sdsdp[0]=0x8778a256;
			sdsdp[1]=0x0947a030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else if (!strcmp(argv[1], "test")) {
			/*
			 * TODO: this will replace the 667 MHz config above.
			 * But it needs some more testing on a real 667 MHz CPU.
			 */
			printf("Bootstrapping for test"
			       " (667MHz PLB=133PLB PLB/PCI=3)\n");
			sdsdp[0]=0x8778a256;
			sdsdp[1]=0x095fa030;
			sdsdp[2]=0x40082350;
			sdsdp[3]=0x0d050000;
		} else {
			printf("Usage:\nsbe %s\n", cmdtp->help);
			return -1;
		}
	}

	if (argc > 2) {
		sdsdp[4] = 0;
		if (argv[2][0]=='1')
			sdsdp[4]=0x19750100;
		else if (argv[2][0]=='0')
			sdsdp[4]=0x19750000;
		if (sdsdp[4])
			count += 4;
	}

	if (argc > 3) {
		delay = simple_strtoul(argv[3], NULL, 10);
		if (delay > 20)
			delay = 20;
		sdsdp[4] |= delay;
	}

	printf("Writing boot EEPROM ...\n");
	if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
				   0, (uchar*)sdsdp, count) != 0)
		printf("bootstrap_eeprom_write failed\n");
	else
		printf("done (dump via 'i2c md 52 0.1 14')\n");

	return 0;
}
U_BOOT_CMD(
	sbe, 4, 0, do_setup_bootstrap_eeprom,
	"sbe     - setup bootstrap eeprom\n",
	"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
	);

#if defined(CONFIG_PRAM)
#include <environment.h>
extern env_t *env_ptr;

int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	u32 memsize;
	u32 pram, env_base;
	char *v;
	u32 param;
	ulong *lptr;

	memsize = gd->bd->bi_memsize;

	v = getenv("pram");
	if (v)
		pram = simple_strtoul(v, NULL, 10);
	else {
		printf("Error: pram undefined. Please define pram in KiB\n");
		return 1;
	}

	param = memsize - (pram << 10);
	printf("PARAM: @%08x\n", param);

	memset((void*)param, 0, (pram << 10));
	env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
	memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);

	lptr = (ulong*)memsize;
	*(--lptr) = CFG_ENV_SIZE;
	*(--lptr) = memsize - env_base;
	*(--lptr) = crc32(0, (void*)(memsize - 0x08), 0x08);
	*(--lptr) = 0;

	/* make sure data can be accessed through PCI */
	flush_dcache_range(param, param + (pram << 10) - 1);
	return 0;
}
U_BOOT_CMD(
	painit,	1,	1,	do_painit,
	"painit  - prepare PciAccess system\n",
	NULL
	);
#endif /* CONFIG_PRAM */

int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	if (argc > 1) {
		if (argv[1][0] == '0') {
			/* assert */
			printf("self-reset# asserted\n");
			out_be32((void*)GPIO0_TCR,
				 in_be32((void*)GPIO0_TCR) | GPIO0_SELF_RST);
		} else {
			/* deassert */
			printf("self-reset# deasserted\n");
			out_be32((void*)GPIO0_TCR,
				 in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
		}
	} else {
		printf("self-reset# is %s\n",
		       in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
		       "active" : "inactive");
	}

	return 0;
}
U_BOOT_CMD(
	selfreset,	2,	1,	do_selfreset,
	"selfreset- assert self-reset# signal\n",
	NULL
	);

int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;

	/* requiers bootet FPGA and PLD_IOEN_N active */
	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
		printf("Error: resetout requires a bootet FPGA\n");
		return -1;
	}

	if (argc > 1) {
		if (argv[1][0] == '0') {
			/* assert */
			printf("PMC-RESETOUT# asserted\n");
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_PMCRSTOUT_GATE);
		} else {
			/* deassert */
			printf("PMC-RESETOUT# deasserted\n");
			FPGA_OUT32(&fpga->hostctrl,
				   HOSTCTRL_PMCRSTOUT_GATE |
				   HOSTCTRL_PMCRSTOUT_FLAG);
		}
	} else {
		printf("PMC-RESETOUT# is %s\n",
		       FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
		       "inactive" : "active");
	}

	return 0;
}
U_BOOT_CMD(
	resetout,	2,	1,	do_resetout,
	"resetout - assert PMC-RESETOUT# signal\n",
	NULL
	);

int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	if (is_monarch()) {
		printf("This command is only supported in non-monarch mode\n");
		return -1;
	}

	if (argc > 1) {
		if (argv[1][0] == '0') {
			/* assert */
			printf("inta# asserted\n");
			out_be32((void*)GPIO1_TCR,
				 in_be32((void*)GPIO1_TCR) | GPIO1_INTA_FAKE);
		} else {
			/* deassert */
			printf("inta# deasserted\n");
			out_be32((void*)GPIO1_TCR,
				 in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
		}
	} else {
		printf("inta# is %s\n",
		       in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
		       "active" : "inactive");
	}
	return 0;
}
U_BOOT_CMD(
	inta,	2,	1,	do_inta,
	"inta    - Assert/Deassert or query INTA# state in non-monarch mode\n",
	NULL
	);

/* test-only */
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	ulong pciaddr;

	if (argc > 1) {
		pciaddr = simple_strtoul(argv[1], NULL, 16);

		pciaddr &= 0xf0000000;

		/* map PCI address at 0xc0000000 in PLB space */

		/* PMM1 Mask/Attribute - disabled b4 setting */
		out32r(PCIX0_PMM1MA, 0x00000000);
		/* PMM1 Local Address */
		out32r(PCIX0_PMM1LA, 0xc0000000);
		/* PMM1 PCI Low Address */
		out32r(PCIX0_PMM1PCILA, pciaddr);
		/* PMM1 PCI High Address */
		out32r(PCIX0_PMM1PCIHA, 0x00000000);
		/* 256MB + No prefetching, and enable region */
		out32r(PCIX0_PMM1MA, 0xf0000001);
	} else {
		printf("Usage:\npmm %s\n", cmdtp->help);
	}
	return 0;
}
U_BOOT_CMD(
	pmm,	2,	1,	do_pmm,
	"pmm     - Setup pmm[1] registers\n",
	"<pciaddr> (pciaddr will be aligned to 256MB)\n"
	);

#if defined(CFG_EEPROM_WREN)
int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	int query = argc == 1;
	int state = 0;

	if (query) {
		/* Query write access state. */
		state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
		if (state < 0) {
			puts("Query of write access state failed.\n");
		} else {
			printf("Write access for device 0x%0x is %sabled.\n",
			       CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
			state = 0;
		}
	} else {
		if ('0' == argv[1][0]) {
			/* Disable write access. */
			state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
		} else {
			/* Enable write access. */
			state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
		}
		if (state < 0) {
			puts("Setup of write access state failed.\n");
		}
	}

	return state;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
	   "eepwren - Enable / disable / query EEPROM write access\n",
	   NULL);
#endif /* #if defined(CFG_EEPROM_WREN) */

#endif /* CONFIG_CMD_BSP */
Commit	Line	Data
407843a5	1	/*
034394ab	2	* (C) Copyright 2007-2008
407843a5 MF	3	* Matthias Fuchs, esd Gmbh, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
407843a5 MF	24	#include <common.h>
	25	#include <command.h>
	26	#include <asm/io.h>
	27	#include <asm/cache.h>
	28	#include <asm/processor.h>
	29
	30	#include "pmc440.h"
	31
	32	int is_monarch(void);
034394ab MF	33	int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
034394ab MF	34	uchar *buffer, unsigned cnt);
407843a5 MF	35	int eeprom_write_enable(unsigned dev_addr, int state);
	36
	37	DECLARE_GLOBAL_DATA_PTR;
	38
	39	#if defined(CONFIG_CMD_BSP)
	40
	41	static int got_fifoirq;
	42	static int got_hcirq;
	43
	44	int fpga_interrupt(u32 arg)
	45	{
	46	pmc440_fpga_t fpga = (pmc440_fpga_t )arg;
	47	int rc = -1; /* not for us */
	48	u32 status = FPGA_IN32(&fpga->status);
	49
	50	/* check for interrupt from fifo module */
	51	if (status & STATUS_FIFO_ISF) {
	52	/* disable this int source */
	53	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
	54	rc = 0;
	55	got_fifoirq = 1; /* trigger backend */
	56	}
	57
	58	if (status & STATUS_HOST_ISF) {
	59	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
	60	rc = 0;
	61	got_hcirq = 1;
	62	}
	63
	64	return rc;
	65	}
	66
407843a5 MF	67	int do_waithci(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	68	{
	69	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	70
	71	got_hcirq = 0;
	72
	73	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	74	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_HCINT_GATE);
	75
	76	irq_install_handler(IRQ0_FPGA,
	77	(interrupt_handler_t *)fpga_interrupt,
	78	fpga);
	79
	80	FPGA_SETBITS(&fpga->ctrla, CTRL_HOST_IE);
	81
	82	while (!got_hcirq) {
	83	/* Abort if ctrl-c was pressed */
	84	if (ctrlc()) {
	85	puts("\nAbort\n");
	86	break;
	87	}
	88	}
	89	if (got_hcirq)
	90	printf("Got interrupt!\n");
	91
	92	FPGA_CLRBITS(&fpga->ctrla, CTRL_HOST_IE);
	93	irq_free_handler(IRQ0_FPGA);
	94	return 0;
	95	}
	96	U_BOOT_CMD(
	97	waithci, 1, 1, do_waithci,
	98	"waithci - Wait for host control interrupt\n",
	99	NULL
	100	);
	101
407843a5 MF	102	void dump_fifo(pmc440_fpga_t fpga, int f, int n)
	103	{
	104	u32 ctrl;
	105
	106	while (!((ctrl = FPGA_IN32(&fpga->fifo[f].ctrl)) & FIFO_EMPTY)) {
	107	printf("%5d %d %3d %08x",
	108	(*n)++, f, ctrl & (FIFO_LEVEL_MASK \| FIFO_FULL),
	109	FPGA_IN32(&fpga->fifo[f].data));
	110	if (ctrl & FIFO_OVERFLOW) {
	111	printf(" OVERFLOW\n");
	112	FPGA_CLRBITS(&fpga->fifo[f].ctrl, FIFO_OVERFLOW);
	113	} else
	114	printf("\n");
	115	}
	116	}
	117
407843a5 MF	118	int do_fifo(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	119	{
	120	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	121	int i;
	122	int n = 0;
	123	u32 ctrl, data, f;
	124	char str[] = "\\\|/-";
	125	int abort = 0;
	126	int count = 0;
	127	int count2 = 0;
	128
	129	switch (argc) {
	130	case 1:
	131	/* print all fifos status information */
	132	printf("fifo level status\n");
	133	printf("______________________________\n");
	134	for (i=0; i<FIFO_COUNT; i++) {
	135	ctrl = FPGA_IN32(&fpga->fifo[i].ctrl);
	136	printf(" %d %3d %s%s%s %s\n",
	137	i, ctrl & (FIFO_LEVEL_MASK \| FIFO_FULL),
	138	ctrl & FIFO_FULL ? "FULL " : "",
	139	ctrl & FIFO_EMPTY ? "EMPTY " : "",
	140	ctrl & (FIFO_FULL\|FIFO_EMPTY) ? "" : "NOT EMPTY",
	141	ctrl & FIFO_OVERFLOW ? "OVERFLOW" : "");
	142	}
	143	break;
	144
	145	case 2:
	146	/* completely read out fifo 'n' */
	147	if (!strcmp(argv[1],"read")) {
	148	printf(" # fifo level data\n");
	149	printf("______________________________\n");
	150
	151	for (i=0; i<FIFO_COUNT; i++)
	152	dump_fifo(fpga, i, &n);
	153
	154	} else if (!strcmp(argv[1],"wait")) {
	155	got_fifoirq = 0;
	156
	157	irq_install_handler(IRQ0_FPGA,
	158	(interrupt_handler_t *)fpga_interrupt,
	159	fpga);
	160
	161	printf(" # fifo level data\n");
	162	printf("______________________________\n");
	163
	164	/* enable all fifo interrupts */
	165	FPGA_OUT32(&fpga->hostctrl,
	166	HOSTCTRL_FIFOIE_GATE \| HOSTCTRL_FIFOIE_FLAG);
	167	for (i=0; i<FIFO_COUNT; i++) {
	168	/* enable interrupts from all fifos */
	169	FPGA_SETBITS(&fpga->fifo[i].ctrl, FIFO_IE);
	170	}
	171
	172	while (1) {
	173	/* wait loop */
	174	while (!got_fifoirq) {
	175	count++;
	176	if (!(count % 100)) {
	177	count2++;
	178	putc(0x08); /* backspace */
	179	putc(str[count2 % 4]);
	180	}
	181
182	/* Abort if ctrl-c was pressed */
183	if ((abort = ctrlc())) {
184	puts("\nAbort\n");
185	break;
186	}
187	udelay(1000);
188	}
189	if (abort)
190	break;
191
192	/* simple fifo backend */
193	if (got_fifoirq) {
194	for (i=0; i<FIFO_COUNT; i++)
195	dump_fifo(fpga, i, &n);
196
197	got_fifoirq = 0;
198	/* unmask global fifo irq */
199	FPGA_OUT32(&fpga->hostctrl,
034394ab MF	200	HOSTCTRL_FIFOIE_GATE \|
034394ab MF	201	HOSTCTRL_FIFOIE_FLAG);
407843a5 MF	202	}
	203	}
	204
	205	/* disable all fifo interrupts */
	206	FPGA_OUT32(&fpga->hostctrl, HOSTCTRL_FIFOIE_GATE);
	207	for (i=0; i<FIFO_COUNT; i++)
	208	FPGA_CLRBITS(&fpga->fifo[i].ctrl, FIFO_IE);
	209
	210	irq_free_handler(IRQ0_FPGA);
	211
	212	} else {
	213	printf("Usage:\nfifo %s\n", cmdtp->help);
	214	return 1;
	215	}
	216	break;
	217
	218	case 4:
	219	case 5:
	220	if (!strcmp(argv[1],"write")) {
	221	/* get fifo number or fifo address */
	222	f = simple_strtoul(argv[2], NULL, 16);
	223
	224	/* data paramter */
	225	data = simple_strtoul(argv[3], NULL, 16);
	226
	227	/* get optional count parameter */
	228	n = 1;
	229	if (argc >= 5)
	230	n = (int)simple_strtoul(argv[4], NULL, 10);
	231
	232	if (f < FIFO_COUNT) {
	233	printf("writing %d x %08x to fifo %d\n",
	234	n, data, f);
	235	for (i=0; i<n; i++)
	236	FPGA_OUT32(&fpga->fifo[f].data, data);
	237	} else {
034394ab MF	238	printf("writing %d x %08x to fifo port at "
034394ab MF	239	"address %08x\n",
407843a5 MF	240	n, data, f);
	241	for (i=0; i<n; i++)
	242	out32(f, data);
	243	}
	244	} else {
	245	printf("Usage:\nfifo %s\n", cmdtp->help);
	246	return 1;
	247	}
	248	break;
	249
	250	default:
	251	printf("Usage:\nfifo %s\n", cmdtp->help);
	252	return 1;
	253	}
	254	return 0;
	255	}
	256	U_BOOT_CMD(
	257	fifo, 5, 1, do_fifo,
	258	"fifo - Fifo module operations\n",
	259	"wait\nfifo read\n"
	260	"fifo write fifo(0..3) data [cnt=1]\n"
	261	"fifo write address(>=4) data [cnt=1]\n"
	262	" - without arguments: print all fifo's status\n"
	263	" - with 'wait' argument: interrupt driven read from all fifos\n"
	264	" - with 'read' argument: read current contents from all fifos\n"
034394ab MF	265	" - with 'write' argument: write 'data' 'cnt' times to "
034394ab MF	266	"'fifo' or 'address'\n"
407843a5 MF	267	);
407843a5 MF	268
407843a5 MF	269	int do_setup_bootstrap_eeprom(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	270	{
	271	ulong sdsdp[5];
	272	ulong delay;
	273	int count=16;
	274
	275	if (argc < 2) {
	276	printf("Usage:\nsbe %s\n", cmdtp->help);
	277	return -1;
	278	}
	279
	280	if (argc > 1) {
	281	if (!strcmp(argv[1], "400")) {
ff5fb8a6	282	/* PLB=133MHz, PLB/PCI=3 */
407843a5 MF	283	printf("Bootstrapping for 400MHz\n");
407843a5 MF	284	sdsdp[0]=0x8678624e;
ff5fb8a6	285	sdsdp[1]=0x095fa030;
407843a5 MF	286	sdsdp[2]=0x40082350;
	287	sdsdp[3]=0x0d050000;
	288	} else if (!strcmp(argv[1], "533")) {
	289	/* PLB=133MHz, PLB/PCI=3 */
	290	printf("Bootstrapping for 533MHz\n");
	291	sdsdp[0]=0x87788252;
	292	sdsdp[1]=0x095fa030;
	293	sdsdp[2]=0x40082350;
	294	sdsdp[3]=0x0d050000;
	295	} else if (!strcmp(argv[1], "667")) {
	296	/* PLB=133MHz, PLB/PCI=4 */
	297	printf("Bootstrapping for 667MHz\n");
	298	sdsdp[0]=0x8778a256;
	299	sdsdp[1]=0x0947a030;
	300	sdsdp[2]=0x40082350;
	301	sdsdp[3]=0x0d050000;
	302	} else if (!strcmp(argv[1], "test")) {
034394ab MF	303	/*
034394ab MF	304	* TODO: this will replace the 667 MHz config above.
407843a5 MF	305	* But it needs some more testing on a real 667 MHz CPU.
407843a5 MF	306	*/
034394ab MF	307	printf("Bootstrapping for test"
034394ab MF	308	" (667MHz PLB=133PLB PLB/PCI=3)\n");
407843a5 MF	309	sdsdp[0]=0x8778a256;
	310	sdsdp[1]=0x095fa030;
	311	sdsdp[2]=0x40082350;
	312	sdsdp[3]=0x0d050000;
	313	} else {
	314	printf("Usage:\nsbe %s\n", cmdtp->help);
	315	return -1;
	316	}
	317	}
	318
	319	if (argc > 2) {
	320	sdsdp[4] = 0;
	321	if (argv[2][0]=='1')
	322	sdsdp[4]=0x19750100;
	323	else if (argv[2][0]=='0')
	324	sdsdp[4]=0x19750000;
	325	if (sdsdp[4])
	326	count += 4;
	327	}
	328
	329	if (argc > 3) {
	330	delay = simple_strtoul(argv[3], NULL, 10);
	331	if (delay > 20)
	332	delay = 20;
	333	sdsdp[4] \|= delay;
	334	}
	335
	336	printf("Writing boot EEPROM ...\n");
	337	if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
	338	0, (uchar*)sdsdp, count) != 0)
	339	printf("bootstrap_eeprom_write failed\n");
	340	else
	341	printf("done (dump via 'i2c md 52 0.1 14')\n");
	342
	343	return 0;
	344	}
	345	U_BOOT_CMD(
	346	sbe, 4, 0, do_setup_bootstrap_eeprom,
	347	"sbe - setup bootstrap eeprom\n",
	348	"<cpufreq:400\|533\|667> [<console-uart:0\|1> [<bringup delay (0..20s)>]]"
	349	);
	350
407843a5 MF	351	#if defined(CONFIG_PRAM)
	352	#include <environment.h>
	353	extern env_t *env_ptr;
	354
	355	int do_painit(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	356	{
	357	u32 memsize;
	358	u32 pram, env_base;
	359	char *v;
	360	u32 param;
	361	ulong *lptr;
	362
	363	memsize = gd->bd->bi_memsize;
	364
	365	v = getenv("pram");
	366	if (v)
	367	pram = simple_strtoul(v, NULL, 10);
	368	else {
	369	printf("Error: pram undefined. Please define pram in KiB\n");
	370	return 1;
	371	}
	372
	373	param = memsize - (pram << 10);
	374	printf("PARAM: @%08x\n", param);
	375
	376	memset((void*)param, 0, (pram << 10));
	377	env_base = memsize - 4096 - ((CFG_ENV_SIZE + 4096) & ~(4096-1));
	378	memcpy((void*)env_base, env_ptr, CFG_ENV_SIZE);
	379
	380	lptr = (ulong*)memsize;
	381	*(--lptr) = CFG_ENV_SIZE;
	382	*(--lptr) = memsize - env_base;
	383	(--lptr) = crc32(0, (void)(memsize - 0x08), 0x08);
	384	*(--lptr) = 0;
	385
	386	/* make sure data can be accessed through PCI */
	387	flush_dcache_range(param, param + (pram << 10) - 1);
	388	return 0;
	389	}
	390	U_BOOT_CMD(
	391	painit, 1, 1, do_painit,
	392	"painit - prepare PciAccess system\n",
	393	NULL
	394	);
	395	#endif /* CONFIG_PRAM */
	396
407843a5 MF	397	int do_selfreset(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	398	{
	399	if (argc > 1) {
	400	if (argv[1][0] == '0') {
	401	/* assert */
	402	printf("self-reset# asserted\n");
	403	out_be32((void*)GPIO0_TCR,
	404	in_be32((void*)GPIO0_TCR) \| GPIO0_SELF_RST);
	405	} else {
	406	/* deassert */
	407	printf("self-reset# deasserted\n");
	408	out_be32((void*)GPIO0_TCR,
	409	in_be32((void*)GPIO0_TCR) & ~GPIO0_SELF_RST);
	410	}
	411	} else {
	412	printf("self-reset# is %s\n",
	413	in_be32((void*)GPIO0_TCR) & GPIO0_SELF_RST ?
	414	"active" : "inactive");
	415	}
	416
	417	return 0;
	418	}
	419	U_BOOT_CMD(
	420	selfreset, 2, 1, do_selfreset,
	421	"selfreset- assert self-reset# signal\n",
	422	NULL
	423	);
	424
407843a5 MF	425	int do_resetout(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	426	{
	427	pmc440_fpga_t fpga = (pmc440_fpga_t )FPGA_BA;
	428
	429	/* requiers bootet FPGA and PLD_IOEN_N active */
	430	if (in_be32((void*)GPIO1_OR) & GPIO1_IOEN_N) {
	431	printf("Error: resetout requires a bootet FPGA\n");
	432	return -1;
	433	}
	434
	435	if (argc > 1) {
	436	if (argv[1][0] == '0') {
	437	/* assert */
	438	printf("PMC-RESETOUT# asserted\n");
	439	FPGA_OUT32(&fpga->hostctrl,
	440	HOSTCTRL_PMCRSTOUT_GATE);
	441	} else {
	442	/* deassert */
	443	printf("PMC-RESETOUT# deasserted\n");
	444	FPGA_OUT32(&fpga->hostctrl,
034394ab MF	445	HOSTCTRL_PMCRSTOUT_GATE \|
034394ab MF	446	HOSTCTRL_PMCRSTOUT_FLAG);
407843a5 MF	447	}
	448	} else {
	449	printf("PMC-RESETOUT# is %s\n",
	450	FPGA_IN32(&fpga->hostctrl) & HOSTCTRL_PMCRSTOUT_FLAG ?
	451	"inactive" : "active");
	452	}
	453
	454	return 0;
	455	}
	456	U_BOOT_CMD(
	457	resetout, 2, 1, do_resetout,
	458	"resetout - assert PMC-RESETOUT# signal\n",
	459	NULL
	460	);
	461
407843a5 MF	462	int do_inta(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	463	{
	464	if (is_monarch()) {
	465	printf("This command is only supported in non-monarch mode\n");
	466	return -1;
	467	}
	468
	469	if (argc > 1) {
	470	if (argv[1][0] == '0') {
	471	/* assert */
	472	printf("inta# asserted\n");
	473	out_be32((void*)GPIO1_TCR,
	474	in_be32((void*)GPIO1_TCR) \| GPIO1_INTA_FAKE);
	475	} else {
	476	/* deassert */
	477	printf("inta# deasserted\n");
	478	out_be32((void*)GPIO1_TCR,
	479	in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
	480	}
	481	} else {
034394ab MF	482	printf("inta# is %s\n",
	483	in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
	484	"active" : "inactive");
407843a5 MF	485	}
	486	return 0;
	487	}
	488	U_BOOT_CMD(
	489	inta, 2, 1, do_inta,
	490	"inta - Assert/Deassert or query INTA# state in non-monarch mode\n",
	491	NULL
	492	);
	493
407843a5 MF	494	/* test-only */
	495	int do_pmm(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	496	{
	497	ulong pciaddr;
	498
	499	if (argc > 1) {
	500	pciaddr = simple_strtoul(argv[1], NULL, 16);
	501
	502	pciaddr &= 0xf0000000;
	503
	504	/* map PCI address at 0xc0000000 in PLB space */
034394ab	505
02e38920	506	/* PMM1 Mask/Attribute - disabled b4 setting */
034394ab	507	out32r(PCIX0_PMM1MA, 0x00000000);
02e38920	508	/* PMM1 Local Address */
034394ab	509	out32r(PCIX0_PMM1LA, 0xc0000000);
02e38920	510	/* PMM1 PCI Low Address */
034394ab	511	out32r(PCIX0_PMM1PCILA, pciaddr);
02e38920	512	/* PMM1 PCI High Address */
034394ab	513	out32r(PCIX0_PMM1PCIHA, 0x00000000);
02e38920	514	/* 256MB + No prefetching, and enable region */
034394ab	515	out32r(PCIX0_PMM1MA, 0xf0000001);
407843a5 MF	516	} else {
	517	printf("Usage:\npmm %s\n", cmdtp->help);
	518	}
	519	return 0;
	520	}
	521	U_BOOT_CMD(
	522	pmm, 2, 1, do_pmm,
	523	"pmm - Setup pmm[1] registers\n",
	524	"<pciaddr> (pciaddr will be aligned to 256MB)\n"
	525	);
	526
	527	#if defined(CFG_EEPROM_WREN)
	528	int do_eep_wren(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	529	{
	530	int query = argc == 1;
	531	int state = 0;
	532
	533	if (query) {
	534	/* Query write access state. */
	535	state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
	536	if (state < 0) {
	537	puts("Query of write access state failed.\n");
	538	} else {
	539	printf("Write access for device 0x%0x is %sabled.\n",
	540	CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
	541	state = 0;
	542	}
	543	} else {
	544	if ('0' == argv[1][0]) {
	545	/* Disable write access. */
	546	state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
	547	} else {
	548	/* Enable write access. */
	549	state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
	550	}
	551	if (state < 0) {
	552	puts("Setup of write access state failed.\n");
	553	}
	554	}
	555
	556	return state;
	557	}
	558	U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
	559	"eepwren - Enable / disable / query EEPROM write access\n",
	560	NULL);
	561	#endif /* #if defined(CFG_EEPROM_WREN) */
	562
	563	#endif /* CONFIG_CMD_BSP */