[J-u-boot.git] / cmd / pci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <[email protected]>
 *
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * Wolfgang Grandegger, DENX Software Engineering, [email protected].
 */

/*
 * PCI routines
 */

#include <common.h>
#include <bootretry.h>
#include <cli.h>
#include <command.h>
#include <console.h>
#include <dm.h>
#include <init.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

struct pci_reg_info {
	const char *name;
	enum pci_size_t size;
	u8 offset;
};

static int pci_byte_size(enum pci_size_t size)
{
	switch (size) {
	case PCI_SIZE_8:
		return 1;
	case PCI_SIZE_16:
		return 2;
	case PCI_SIZE_32:
	default:
		return 4;
	}
}

static int pci_field_width(enum pci_size_t size)
{
	return pci_byte_size(size) * 2;
}

static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
{
	for (; regs->name; regs++) {
		unsigned long val;

		dm_pci_read_config(dev, regs->offset, &val, regs->size);
		printf("  %s =%*s%#.*lx\n", regs->name,
		       (int)(28 - strlen(regs->name)), "",
		       pci_field_width(regs->size), val);
	}
}

static int pci_bar_show(struct udevice *dev)
{
	u8 header_type;
	int bar_cnt, bar_id, mem_type;
	bool is_64, is_io;
	u32 base_low, base_high;
	u32 size_low, size_high;
	u64 base, size;
	u32 reg_addr;
	int prefetchable;

	dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
	header_type &= 0x7f;

	if (header_type == PCI_HEADER_TYPE_CARDBUS) {
		printf("CardBus doesn't support BARs\n");
		return -ENOSYS;
	} else if (header_type != PCI_HEADER_TYPE_NORMAL &&
		   header_type != PCI_HEADER_TYPE_BRIDGE) {
		printf("unknown header type\n");
		return -ENOSYS;
	}

	bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;

	printf("ID   Base                Size                Width  Type\n");
	printf("----------------------------------------------------------\n");

	bar_id = 0;
	reg_addr = PCI_BASE_ADDRESS_0;
	while (bar_cnt) {
		dm_pci_read_config32(dev, reg_addr, &base_low);
		dm_pci_write_config32(dev, reg_addr, 0xffffffff);
		dm_pci_read_config32(dev, reg_addr, &size_low);
		dm_pci_write_config32(dev, reg_addr, base_low);
		reg_addr += 4;

		base = base_low & ~0xf;
		size = size_low & ~0xf;
		base_high = 0x0;
		size_high = 0xffffffff;
		is_64 = 0;
		prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
		is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
		mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;

		if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
			dm_pci_read_config32(dev, reg_addr, &base_high);
			dm_pci_write_config32(dev, reg_addr, 0xffffffff);
			dm_pci_read_config32(dev, reg_addr, &size_high);
			dm_pci_write_config32(dev, reg_addr, base_high);
			bar_cnt--;
			reg_addr += 4;
			is_64 = 1;
		}

		base = base | ((u64)base_high << 32);
		size = size | ((u64)size_high << 32);

		if ((!is_64 && size_low) || (is_64 && size)) {
			size = ~size + 1;
			printf(" %d   %#018llx  %#018llx  %d     %s   %s\n",
			       bar_id, (unsigned long long)base,
			       (unsigned long long)size, is_64 ? 64 : 32,
			       is_io ? "I/O" : "MEM",
			       prefetchable ? "Prefetchable" : "");
		}

		bar_id++;
		bar_cnt--;
	}

	return 0;
}

static struct pci_reg_info regs_start[] = {
	{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
	{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
	{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
	{ "status register", PCI_SIZE_16, PCI_STATUS },
	{ "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
	{},
};

static struct pci_reg_info regs_rest[] = {
	{ "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
	{ "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
	{ "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
	{ "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
	{ "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
	{ "BIST", PCI_SIZE_8, PCI_BIST },
	{ "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
	{},
};

static struct pci_reg_info regs_normal[] = {
	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	{ "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
	{ "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
	{ "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
	{ "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
	{ "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
	{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
	{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	{ "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
	{ "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
	{},
};

static struct pci_reg_info regs_bridge[] = {
	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	{ "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
	{ "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
	{ "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
	{ "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
	{ "IO base", PCI_SIZE_8, PCI_IO_BASE },
	{ "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
	{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
	{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
	{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
	{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
	{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
	{ "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
	{ "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
	{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
	{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
	{},
};

static struct pci_reg_info regs_cardbus[] = {
	{ "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
	{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
	{ "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
	{ "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
	{ "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
	{ "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
	{ "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
	{ "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
	{ "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
	{ "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
	{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
	{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
	{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
	{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
	{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
	{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
	{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
	{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
	{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
	{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
	{ "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
	{},
};

/**
 * pci_header_show() - Show the header of the specified PCI device.
 *
 * @dev: Bus+Device+Function number
 */
static void pci_header_show(struct udevice *dev)
{
	unsigned long class, header_type;

	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
	pci_show_regs(dev, regs_start);
	printf("  class code =                  0x%.2x (%s)\n", (int)class,
	       pci_class_str(class));
	pci_show_regs(dev, regs_rest);

	switch (header_type & 0x7f) {
	case PCI_HEADER_TYPE_NORMAL:	/* "normal" PCI device */
		pci_show_regs(dev, regs_normal);
		break;
	case PCI_HEADER_TYPE_BRIDGE:	/* PCI-to-PCI bridge */
		pci_show_regs(dev, regs_bridge);
		break;
	case PCI_HEADER_TYPE_CARDBUS:	/* PCI-to-CardBus bridge */
		pci_show_regs(dev, regs_cardbus);
		break;

	default:
		printf("unknown header\n");
		break;
    }
}

static void pciinfo_header(int busnum, bool short_listing)
{
	printf("Scanning PCI devices on bus %d\n", busnum);

	if (short_listing) {
		printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n");
		printf("_____________________________________________________________\n");
	}
}

/**
 * pci_header_show_brief() - Show the short-form PCI device header
 *
 * Reads and prints the header of the specified PCI device in short form.
 *
 * @dev: PCI device to show
 */
static void pci_header_show_brief(struct udevice *dev)
{
	ulong vendor, device;
	ulong class, subclass;

	dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
	dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);

	printf("0x%.4lx     0x%.4lx     %-23s 0x%.2lx\n",
	       vendor, device,
	       pci_class_str(class), subclass);
}

static void pciinfo(struct udevice *bus, bool short_listing)
{
	struct udevice *dev;

	pciinfo_header(dev_seq(bus), short_listing);

	for (device_find_first_child(bus, &dev);
	     dev;
	     device_find_next_child(&dev)) {
		struct pci_child_plat *pplat;

		pplat = dev_get_parent_plat(dev);
		if (short_listing) {
			printf("%02x.%02x.%02x   ", dev_seq(bus),
			       PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
			pci_header_show_brief(dev);
		} else {
			printf("\nFound PCI device %02x.%02x.%02x:\n",
			       dev_seq(bus),
			       PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
			pci_header_show(dev);
		}
	}
}

/**
 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
 *
 * @name: Device string in the form "bus.device.function" where each is in hex
 * Return: encoded pci_dev_t or -1 if the string was invalid
 */
static pci_dev_t get_pci_dev(char *name)
{
	char cnum[12];
	int len, i, iold, n;
	int bdfs[3] = {0,0,0};

	len = strlen(name);
	if (len > 8)
		return -1;
	for (i = 0, iold = 0, n = 0; i < len; i++) {
		if (name[i] == '.') {
			memcpy(cnum, &name[iold], i - iold);
			cnum[i - iold] = '\0';
			bdfs[n++] = hextoul(cnum, NULL);
			iold = i + 1;
		}
	}
	strcpy(cnum, &name[iold]);
	if (n == 0)
		n = 1;
	bdfs[n] = hextoul(cnum, NULL);

	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}

static int pci_cfg_display(struct udevice *dev, ulong addr,
			   enum pci_size_t size, ulong length)
{
#define DISP_LINE_LEN	16
	ulong i, nbytes, linebytes;
	int byte_size;
	int rc = 0;

	byte_size = pci_byte_size(size);
	if (length == 0)
		length = 0x40 / byte_size; /* Standard PCI config space */

	/* Print the lines.
	 * once, and all accesses are with the specified bus width.
	 */
	nbytes = length * byte_size;
	do {
		printf("%08lx:", addr);
		linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
		for (i = 0; i < linebytes; i += byte_size) {
			unsigned long val;

			dm_pci_read_config(dev, addr, &val, size);
			printf(" %0*lx", pci_field_width(size), val);
			addr += byte_size;
		}
		printf("\n");
		nbytes -= linebytes;
		if (ctrlc()) {
			rc = 1;
			break;
		}
	} while (nbytes > 0);

	return (rc);
}

static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
			  ulong value, int incrflag)
{
	ulong	i;
	int	nbytes;
	ulong val;

	/* Print the address, followed by value.  Then accept input for
	 * the next value.  A non-converted value exits.
	 */
	do {
		printf("%08lx:", addr);
		dm_pci_read_config(dev, addr, &val, size);
		printf(" %0*lx", pci_field_width(size), val);

		nbytes = cli_readline(" ? ");
		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
			/* <CR> pressed as only input, don't modify current
			 * location and move to next. "-" pressed will go back.
			 */
			if (incrflag)
				addr += nbytes ? -size : size;
			nbytes = 1;
			/* good enough to not time out */
			bootretry_reset_cmd_timeout();
		}
#ifdef CONFIG_BOOT_RETRY_TIME
		else if (nbytes == -2) {
			break;	/* timed out, exit the command	*/
		}
#endif
		else {
			char *endp;
			i = hextoul(console_buffer, &endp);
			nbytes = endp - console_buffer;
			if (nbytes) {
				/* good enough to not time out
				 */
				bootretry_reset_cmd_timeout();
				dm_pci_write_config(dev, addr, i, size);
				if (incrflag)
					addr += size;
			}
		}
	} while (nbytes);

	return 0;
}

static const struct pci_flag_info {
	uint flag;
	const char *name;
} pci_flag_info[] = {
	{ PCI_REGION_IO, "io" },
	{ PCI_REGION_PREFETCH, "prefetch" },
	{ PCI_REGION_SYS_MEMORY, "sysmem" },
	{ PCI_REGION_RO, "readonly" },
	{ PCI_REGION_IO, "io" },
};

static void pci_show_regions(struct udevice *bus)
{
	struct pci_controller *hose = dev_get_uclass_priv(bus);
	const struct pci_region *reg;
	int i, j;

	if (!hose) {
		printf("Bus '%s' is not a PCI controller\n", bus->name);
		return;
	}

	printf("#   %-18s %-18s %-18s  %s\n", "Bus start", "Phys start", "Size",
	       "Flags");
	for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
		printf("%d   %#018llx %#018llx %#018llx  ", i,
		       (unsigned long long)reg->bus_start,
		       (unsigned long long)reg->phys_start,
		       (unsigned long long)reg->size);
		if (!(reg->flags & PCI_REGION_TYPE))
			printf("mem ");
		for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
			if (reg->flags & pci_flag_info[j].flag)
				printf("%s ", pci_flag_info[j].name);
		}
		printf("\n");
	}
}

/* PCI Configuration Space access commands
 *
 * Syntax:
 *	pci display[.b, .w, .l] bus.device.function} [addr] [len]
 *	pci next[.b, .w, .l] bus.device.function [addr]
 *      pci modify[.b, .w, .l] bus.device.function [addr]
 *      pci write[.b, .w, .l] bus.device.function addr value
 */
static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	ulong addr = 0, value = 0, cmd_size = 0;
	enum pci_size_t size = PCI_SIZE_32;
	struct udevice *dev, *bus;
	int busnum = 0;
	pci_dev_t bdf = 0;
	char cmd = 's';
	int ret = 0;

	if (argc > 1)
		cmd = argv[1][0];

	switch (cmd) {
	case 'd':		/* display */
	case 'n':		/* next */
	case 'm':		/* modify */
	case 'w':		/* write */
		/* Check for a size specification. */
		cmd_size = cmd_get_data_size(argv[1], 4);
		size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
		if (argc > 3)
			addr = hextoul(argv[3], NULL);
		if (argc > 4)
			value = hextoul(argv[4], NULL);
	case 'h':		/* header */
	case 'b':		/* bars */
		if (argc < 3)
			goto usage;
		if ((bdf = get_pci_dev(argv[2])) == -1)
			return 1;
		break;
	case 'e':
		pci_init();
		return 0;
	case 'r': /* no break */
	default:		/* scan bus */
		value = 1; /* short listing */
		if (argc > 1) {
			if (cmd != 'r' && argv[argc-1][0] == 'l') {
				value = 0;
				argc--;
			}
			if (argc > 1)
				busnum = hextoul(argv[1], NULL);
		}
		ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
		if (ret) {
			printf("No such bus\n");
			return CMD_RET_FAILURE;
		}
		if (cmd == 'r')
			pci_show_regions(bus);
		else
			pciinfo(bus, value);
		return 0;
	}

	ret = dm_pci_bus_find_bdf(bdf, &dev);
	if (ret) {
		printf("No such device\n");
		return CMD_RET_FAILURE;
	}

	switch (argv[1][0]) {
	case 'h':		/* header */
		pci_header_show(dev);
		break;
	case 'd':		/* display */
		return pci_cfg_display(dev, addr, size, value);
	case 'n':		/* next */
		if (argc < 4)
			goto usage;
		ret = pci_cfg_modify(dev, addr, size, value, 0);
		break;
	case 'm':		/* modify */
		if (argc < 4)
			goto usage;
		ret = pci_cfg_modify(dev, addr, size, value, 1);
		break;
	case 'w':		/* write */
		if (argc < 5)
			goto usage;
		ret = dm_pci_write_config(dev, addr, value, size);
		break;
	case 'b':		/* bars */
		return pci_bar_show(dev);
	default:
		ret = CMD_RET_USAGE;
		break;
	}

	return ret;
 usage:
	return CMD_RET_USAGE;
}

/***************************************************/

#ifdef CONFIG_SYS_LONGHELP
static char pci_help_text[] =
	"[bus] [long]\n"
	"    - short or long list of PCI devices on bus 'bus'\n"
	"pci enum\n"
	"    - Enumerate PCI buses\n"
	"pci header b.d.f\n"
	"    - show header of PCI device 'bus.device.function'\n"
	"pci bar b.d.f\n"
	"    - show BARs base and size for device b.d.f'\n"
	"pci regions\n"
	"    - show PCI regions\n"
	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	"    - display PCI configuration space (CFG)\n"
	"pci next[.b, .w, .l] b.d.f address\n"
	"    - modify, read and keep CFG address\n"
	"pci modify[.b, .w, .l] b.d.f address\n"
	"    -  modify, auto increment CFG address\n"
	"pci write[.b, .w, .l] b.d.f address value\n"
	"    - write to CFG address";
#endif

U_BOOT_CMD(
	pci,	5,	1,	do_pci,
	"list and access PCI Configuration Space", pci_help_text
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
c609719b WD	2	/*
	3	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Andreas Heppel <[email protected]>
	5	*
	6	* (C) Copyright 2002
	7	* Wolfgang Denk, DENX Software Engineering, [email protected].
	8	* Wolfgang Grandegger, DENX Software Engineering, [email protected].
c609719b WD	9	*/
	10
	11	/*
	12	* PCI routines
	13	*/
	14
	15	#include <common.h>
0098e179	16	#include <bootretry.h>
18d66533	17	#include <cli.h>
c609719b	18	#include <command.h>
24b852a7	19	#include <console.h>
cab24b34	20	#include <dm.h>
691d719d	21	#include <init.h>
c609719b WD	22	#include <asm/processor.h>
c609719b WD	23	#include <asm/io.h>
c609719b WD	24	#include <pci.h>
c609719b WD	25
07a58870 SG	26	struct pci_reg_info {
	27	const char *name;
	28	enum pci_size_t size;
	29	u8 offset;
	30	};
	31
72ef5b60	32	static int pci_byte_size(enum pci_size_t size)
07a58870 SG	33	{
	34	switch (size) {
	35	case PCI_SIZE_8:
72ef5b60	36	return 1;
07a58870	37	case PCI_SIZE_16:
72ef5b60	38	return 2;
07a58870 SG	39	case PCI_SIZE_32:
07a58870 SG	40	default:
72ef5b60	41	return 4;
07a58870 SG	42	}
	43	}
	44
72ef5b60 SG	45	static int pci_field_width(enum pci_size_t size)
	46	{
	47	return pci_byte_size(size) * 2;
	48	}
	49
cab24b34 SG	50	static void pci_show_regs(struct udevice dev, struct pci_reg_info regs)
	51	{
	52	for (; regs->name; regs++) {
	53	unsigned long val;
	54
	55	dm_pci_read_config(dev, regs->offset, &val, regs->size);
	56	printf(" %s =%s%#.lx\n", regs->name,
	57	(int)(28 - strlen(regs->name)), "",
	58	pci_field_width(regs->size), val);
	59	}
	60	}
07a58870	61
f5164f6b	62	static int pci_bar_show(struct udevice *dev)
e5f96a87 YY	63	{
	64	u8 header_type;
	65	int bar_cnt, bar_id, mem_type;
	66	bool is_64, is_io;
	67	u32 base_low, base_high;
	68	u32 size_low, size_high;
	69	u64 base, size;
	70	u32 reg_addr;
	71	int prefetchable;
	72
	73	dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
e6335d3e	74	header_type &= 0x7f;
e5f96a87 YY	75
	76	if (header_type == PCI_HEADER_TYPE_CARDBUS) {
	77	printf("CardBus doesn't support BARs\n");
	78	return -ENOSYS;
e6335d3e T	79	} else if (header_type != PCI_HEADER_TYPE_NORMAL &&
	80	header_type != PCI_HEADER_TYPE_BRIDGE) {
	81	printf("unknown header type\n");
	82	return -ENOSYS;
e5f96a87 YY	83	}
	84
	85	bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
	86
	87	printf("ID Base Size Width Type\n");
	88	printf("----------------------------------------------------------\n");
	89
	90	bar_id = 0;
	91	reg_addr = PCI_BASE_ADDRESS_0;
	92	while (bar_cnt) {
	93	dm_pci_read_config32(dev, reg_addr, &base_low);
	94	dm_pci_write_config32(dev, reg_addr, 0xffffffff);
	95	dm_pci_read_config32(dev, reg_addr, &size_low);
	96	dm_pci_write_config32(dev, reg_addr, base_low);
	97	reg_addr += 4;
	98
	99	base = base_low & ~0xf;
	100	size = size_low & ~0xf;
	101	base_high = 0x0;
	102	size_high = 0xffffffff;
	103	is_64 = 0;
	104	prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
	105	is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
	106	mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
	107
	108	if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
	109	dm_pci_read_config32(dev, reg_addr, &base_high);
	110	dm_pci_write_config32(dev, reg_addr, 0xffffffff);
	111	dm_pci_read_config32(dev, reg_addr, &size_high);
	112	dm_pci_write_config32(dev, reg_addr, base_high);
	113	bar_cnt--;
	114	reg_addr += 4;
	115	is_64 = 1;
	116	}
	117
	118	base = base \| ((u64)base_high << 32);
	119	size = size \| ((u64)size_high << 32);
	120
	121	if ((!is_64 && size_low) \|\| (is_64 && size)) {
	122	size = ~size + 1;
4ebeb4c5	123	printf(" %d %#018llx %#018llx %d %s %s\n",
84d7f916 SG	124	bar_id, (unsigned long long)base,
84d7f916 SG	125	(unsigned long long)size, is_64 ? 64 : 32,
e5f96a87 YY	126	is_io ? "I/O" : "MEM",
	127	prefetchable ? "Prefetchable" : "");
	128	}
	129
	130	bar_id++;
	131	bar_cnt--;
	132	}
	133
	134	return 0;
	135	}
e5f96a87	136
07a58870 SG	137	static struct pci_reg_info regs_start[] = {
	138	{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
	139	{ "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
	140	{ "command register ID", PCI_SIZE_16, PCI_COMMAND },
	141	{ "status register", PCI_SIZE_16, PCI_STATUS },
	142	{ "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
	143	{},
	144	};
	145
	146	static struct pci_reg_info regs_rest[] = {
	147	{ "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
	148	{ "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
	149	{ "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
	150	{ "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
	151	{ "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
	152	{ "BIST", PCI_SIZE_8, PCI_BIST },
	153	{ "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
	154	{},
	155	};
	156
	157	static struct pci_reg_info regs_normal[] = {
	158	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	159	{ "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
	160	{ "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
	161	{ "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
	162	{ "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
	163	{ "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
	164	{ "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
	165	{ "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
	166	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
	167	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	168	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	169	{ "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
	170	{ "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
	171	{},
	172	};
	173
	174	static struct pci_reg_info regs_bridge[] = {
	175	{ "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
	176	{ "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
	177	{ "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
	178	{ "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
	179	{ "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
	180	{ "IO base", PCI_SIZE_8, PCI_IO_BASE },
	181	{ "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
	182	{ "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
	183	{ "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
	184	{ "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
	185	{ "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
	186	{ "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
	187	{ "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
	188	{ "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
	189	{ "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
	190	{ "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
	191	{ "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
	192	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
	193	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
	194	{ "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
	195	{},
	196	};
	197
	198	static struct pci_reg_info regs_cardbus[] = {
	199	{ "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
	200	{ "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
201	{ "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
202	{ "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
203	{ "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
204	{ "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
205	{ "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
206	{ "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
207	{ "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
208	{ "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
209	{ "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
210	{ "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
211	{ "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
212	{ "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
213	{ "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
214	{ "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
215	{ "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
216	{ "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
217	{ "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
218	{ "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
219	{ "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
220	{ "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
221	{ "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
222	{ "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
223	{},
224	};
225
c2be0700 SG	226	/**
c2be0700 SG	227	* pci_header_show() - Show the header of the specified PCI device.
c609719b	228	*
c2be0700	229	* @dev: Bus+Device+Function number
c609719b	230	*/
a95f8ee9	231	static void pci_header_show(struct udevice *dev)
c609719b	232	{
cab24b34 SG	233	unsigned long class, header_type;
	234
	235	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	236	dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
07a58870	237	pci_show_regs(dev, regs_start);
cab24b34	238	printf(" class code = 0x%.2x (%s)\n", (int)class,
07a58870 SG	239	pci_class_str(class));
07a58870 SG	240	pci_show_regs(dev, regs_rest);
c609719b	241
43dad07c	242	switch (header_type & 0x7f) {
7c7a23bd	243	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
07a58870	244	pci_show_regs(dev, regs_normal);
7c7a23bd	245	break;
7c7a23bd	246	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
07a58870	247	pci_show_regs(dev, regs_bridge);
7c7a23bd	248	break;
7c7a23bd	249	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
07a58870	250	pci_show_regs(dev, regs_cardbus);
7c7a23bd	251	break;
8bde7f77	252
7c7a23bd WD	253	default:
7c7a23bd WD	254	printf("unknown header\n");
8bde7f77	255	break;
c609719b	256	}
c609719b WD	257	}
c609719b WD	258
577fd581	259	static void pciinfo_header(int busnum, bool short_listing)
c4f32bb2 SG	260	{
	261	printf("Scanning PCI devices on bus %d\n", busnum);
	262
	263	if (short_listing) {
	264	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
	265	printf("_____________________________________________________________\n");
	266	}
	267	}
	268
cab24b34 SG	269	/**
	270	* pci_header_show_brief() - Show the short-form PCI device header
	271	*
	272	* Reads and prints the header of the specified PCI device in short form.
	273	*
	274	* @dev: PCI device to show
	275	*/
	276	static void pci_header_show_brief(struct udevice *dev)
	277	{
	278	ulong vendor, device;
	279	ulong class, subclass;
	280
	281	dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
	282	dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
	283	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
	284	dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
	285
	286	printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
	287	vendor, device,
	288	pci_class_str(class), subclass);
	289	}
	290
	291	static void pciinfo(struct udevice *bus, bool short_listing)
	292	{
	293	struct udevice *dev;
	294
8b85dfc6	295	pciinfo_header(dev_seq(bus), short_listing);
cab24b34 SG	296
	297	for (device_find_first_child(bus, &dev);
	298	dev;
	299	device_find_next_child(&dev)) {
8a8d24bd	300	struct pci_child_plat *pplat;
cab24b34	301
caa4daa2	302	pplat = dev_get_parent_plat(dev);
cab24b34	303	if (short_listing) {
8b85dfc6	304	printf("%02x.%02x.%02x ", dev_seq(bus),
cab24b34 SG	305	PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
	306	pci_header_show_brief(dev);
	307	} else {
8b85dfc6 SG	308	printf("\nFound PCI device %02x.%02x.%02x:\n",
8b85dfc6 SG	309	dev_seq(bus),
cab24b34 SG	310	PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
	311	pci_header_show(dev);
	312	}
	313	}
	314	}
	315
c2be0700 SG	316	/**
	317	* get_pci_dev() - Convert the "bus.device.function" identifier into a number
	318	*
	319	* @name: Device string in the form "bus.device.function" where each is in hex
185f812c	320	* Return: encoded pci_dev_t or -1 if the string was invalid
c609719b	321	*/
c2be0700	322	static pci_dev_t get_pci_dev(char *name)
c609719b WD	323	{
	324	char cnum[12];
	325	int len, i, iold, n;
	326	int bdfs[3] = {0,0,0};
	327
	328	len = strlen(name);
	329	if (len > 8)
	330	return -1;
	331	for (i = 0, iold = 0, n = 0; i < len; i++) {
	332	if (name[i] == '.') {
	333	memcpy(cnum, &name[iold], i - iold);
	334	cnum[i - iold] = '\0';
7e5f460e	335	bdfs[n++] = hextoul(cnum, NULL);
c609719b WD	336	iold = i + 1;
	337	}
	338	}
	339	strcpy(cnum, &name[iold]);
	340	if (n == 0)
	341	n = 1;
7e5f460e	342	bdfs[n] = hextoul(cnum, NULL);
c2be0700	343
c609719b WD	344	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
	345	}
	346
cab24b34 SG	347	static int pci_cfg_display(struct udevice *dev, ulong addr,
cab24b34 SG	348	enum pci_size_t size, ulong length)
c609719b WD	349	{
	350	#define DISP_LINE_LEN 16
	351	ulong i, nbytes, linebytes;
72ef5b60	352	int byte_size;
c609719b WD	353	int rc = 0;
c609719b WD	354
72ef5b60	355	byte_size = pci_byte_size(size);
c609719b	356	if (length == 0)
72ef5b60	357	length = 0x40 / byte_size; /* Standard PCI config space */
c609719b WD	358
	359	/* Print the lines.
	360	* once, and all accesses are with the specified bus width.
	361	*/
72ef5b60	362	nbytes = length * byte_size;
c609719b	363	do {
c609719b	364	printf("%08lx:", addr);
72ef5b60 SG	365	linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
	366	for (i = 0; i < linebytes; i += byte_size) {
	367	unsigned long val;
	368
cab24b34	369	dm_pci_read_config(dev, addr, &val, size);
72ef5b60 SG	370	printf(" %0*lx", pci_field_width(size), val);
72ef5b60 SG	371	addr += byte_size;
c609719b WD	372	}
	373	printf("\n");
	374	nbytes -= linebytes;
	375	if (ctrlc()) {
	376	rc = 1;
	377	break;
	378	}
	379	} while (nbytes > 0);
	380
	381	return (rc);
	382	}
	383
cab24b34	384	static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
72ef5b60	385	ulong value, int incrflag)
c609719b WD	386	{
	387	ulong i;
	388	int nbytes;
72ef5b60	389	ulong val;
c609719b WD	390
	391	/* Print the address, followed by value. Then accept input for
	392	* the next value. A non-converted value exits.
	393	*/
	394	do {
	395	printf("%08lx:", addr);
cab24b34	396	dm_pci_read_config(dev, addr, &val, size);
72ef5b60	397	printf(" %0*lx", pci_field_width(size), val);
c609719b	398
e1bf824d	399	nbytes = cli_readline(" ? ");
c609719b WD	400	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
	401	/* <CR> pressed as only input, don't modify current
	402	* location and move to next. "-" pressed will go back.
	403	*/
	404	if (incrflag)
	405	addr += nbytes ? -size : size;
	406	nbytes = 1;
b26440f1 SG	407	/* good enough to not time out */
b26440f1 SG	408	bootretry_reset_cmd_timeout();
c609719b WD	409	}
	410	#ifdef CONFIG_BOOT_RETRY_TIME
	411	else if (nbytes == -2) {
	412	break; /* timed out, exit the command */
	413	}
	414	#endif
	415	else {
	416	char *endp;
7e5f460e	417	i = hextoul(console_buffer, &endp);
c609719b WD	418	nbytes = endp - console_buffer;
c609719b WD	419	if (nbytes) {
c609719b WD	420	/* good enough to not time out
c609719b WD	421	*/
b26440f1	422	bootretry_reset_cmd_timeout();
cab24b34	423	dm_pci_write_config(dev, addr, i, size);
c609719b WD	424	if (incrflag)
	425	addr += size;
	426	}
	427	}
	428	} while (nbytes);
	429
	430	return 0;
	431	}
	432
b997a73e SG	433	static const struct pci_flag_info {
	434	uint flag;
	435	const char *name;
	436	} pci_flag_info[] = {
	437	{ PCI_REGION_IO, "io" },
	438	{ PCI_REGION_PREFETCH, "prefetch" },
	439	{ PCI_REGION_SYS_MEMORY, "sysmem" },
	440	{ PCI_REGION_RO, "readonly" },
	441	{ PCI_REGION_IO, "io" },
	442	};
	443
	444	static void pci_show_regions(struct udevice *bus)
	445	{
	446	struct pci_controller *hose = dev_get_uclass_priv(bus);
	447	const struct pci_region *reg;
	448	int i, j;
	449
	450	if (!hose) {
	451	printf("Bus '%s' is not a PCI controller\n", bus->name);
	452	return;
	453	}
	454
4ebeb4c5	455	printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
b997a73e SG	456	"Flags");
b997a73e SG	457	for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
4ebeb4c5	458	printf("%d %#018llx %#018llx %#018llx ", i,
b997a73e SG	459	(unsigned long long)reg->bus_start,
	460	(unsigned long long)reg->phys_start,
	461	(unsigned long long)reg->size);
	462	if (!(reg->flags & PCI_REGION_TYPE))
	463	printf("mem ");
	464	for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
	465	if (reg->flags & pci_flag_info[j].flag)
	466	printf("%s ", pci_flag_info[j].name);
	467	}
	468	printf("\n");
	469	}
	470	}
b997a73e	471
c609719b WD	472	/* PCI Configuration Space access commands
	473	*
	474	* Syntax:
	475	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
	476	* pci next[.b, .w, .l] bus.device.function [addr]
	477	* pci modify[.b, .w, .l] bus.device.function [addr]
	478	* pci write[.b, .w, .l] bus.device.function addr value
	479	*/
09140113	480	static int do_pci(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
c609719b	481	{
72ef5b60 SG	482	ulong addr = 0, value = 0, cmd_size = 0;
72ef5b60 SG	483	enum pci_size_t size = PCI_SIZE_32;
cab24b34	484	struct udevice dev, bus;
ca7de76d	485	int busnum = 0;
c609719b WD	486	pci_dev_t bdf = 0;
c609719b WD	487	char cmd = 's';
bfa4191e	488	int ret = 0;
c609719b WD	489
	490	if (argc > 1)
	491	cmd = argv[1][0];
	492
	493	switch (cmd) {
	494	case 'd': /* display */
	495	case 'n': /* next */
	496	case 'm': /* modify */
	497	case 'w': /* write */
	498	/* Check for a size specification. */
72ef5b60 SG	499	cmd_size = cmd_get_data_size(argv[1], 4);
72ef5b60 SG	500	size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
c609719b	501	if (argc > 3)
7e5f460e	502	addr = hextoul(argv[3], NULL);
c609719b	503	if (argc > 4)
7e5f460e	504	value = hextoul(argv[4], NULL);
c609719b	505	case 'h': /* header */
e5f96a87	506	case 'b': /* bars */
c609719b WD	507	if (argc < 3)
	508	goto usage;
	509	if ((bdf = get_pci_dev(argv[2])) == -1)
	510	return 1;
	511	break;
96d61603	512	case 'e':
e578b92c SW	513	pci_init();
e578b92c SW	514	return 0;
b997a73e	515	case 'r': /* no break */
c609719b WD	516	default: /* scan bus */
c609719b WD	517	value = 1; /* short listing */
c609719b	518	if (argc > 1) {
b997a73e	519	if (cmd != 'r' && argv[argc-1][0] == 'l') {
c609719b WD	520	value = 0;
	521	argc--;
	522	}
	523	if (argc > 1)
7e5f460e	524	busnum = hextoul(argv[1], NULL);
c609719b	525	}
cab24b34 SG	526	ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
	527	if (ret) {
	528	printf("No such bus\n");
	529	return CMD_RET_FAILURE;
	530	}
b997a73e SG	531	if (cmd == 'r')
	532	pci_show_regions(bus);
	533	else
	534	pciinfo(bus, value);
c609719b WD	535	return 0;
	536	}
	537
f3f1faef	538	ret = dm_pci_bus_find_bdf(bdf, &dev);
cab24b34 SG	539	if (ret) {
	540	printf("No such device\n");
	541	return CMD_RET_FAILURE;
	542	}
32ec5b34	543
c609719b WD	544	switch (argv[1][0]) {
c609719b WD	545	case 'h': /* header */
32ec5b34	546	pci_header_show(dev);
bfa4191e	547	break;
c609719b	548	case 'd': /* display */
32ec5b34	549	return pci_cfg_display(dev, addr, size, value);
c609719b WD	550	case 'n': /* next */
	551	if (argc < 4)
	552	goto usage;
32ec5b34	553	ret = pci_cfg_modify(dev, addr, size, value, 0);
bfa4191e	554	break;
c609719b WD	555	case 'm': /* modify */
	556	if (argc < 4)
	557	goto usage;
32ec5b34	558	ret = pci_cfg_modify(dev, addr, size, value, 1);
bfa4191e	559	break;
c609719b WD	560	case 'w': /* write */
	561	if (argc < 5)
	562	goto usage;
cab24b34	563	ret = dm_pci_write_config(dev, addr, value, size);
bfa4191e	564	break;
e5f96a87 YY	565	case 'b': /* bars */
e5f96a87 YY	566	return pci_bar_show(dev);
bfa4191e SG	567	default:
	568	ret = CMD_RET_USAGE;
	569	break;
c609719b WD	570	}
c609719b WD	571
bfa4191e	572	return ret;
c609719b	573	usage:
4c12eeb8	574	return CMD_RET_USAGE;
c609719b WD	575	}
c609719b WD	576
8bde7f77 WD	577	/***************************************************/
8bde7f77 WD	578
088f1b19 KP	579	#ifdef CONFIG_SYS_LONGHELP
088f1b19 KP	580	static char pci_help_text[] =
8bde7f77 WD	581	"[bus] [long]\n"
8bde7f77 WD	582	" - short or long list of PCI devices on bus 'bus'\n"
96d61603	583	"pci enum\n"
e578b92c	584	" - Enumerate PCI buses\n"
8bde7f77 WD	585	"pci header b.d.f\n"
8bde7f77 WD	586	" - show header of PCI device 'bus.device.function'\n"
e5f96a87 YY	587	"pci bar b.d.f\n"
e5f96a87 YY	588	" - show BARs base and size for device b.d.f'\n"
b997a73e SG	589	"pci regions\n"
b997a73e SG	590	" - show PCI regions\n"
8bde7f77 WD	591	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	592	" - display PCI configuration space (CFG)\n"
	593	"pci next[.b, .w, .l] b.d.f address\n"
	594	" - modify, read and keep CFG address\n"
	595	"pci modify[.b, .w, .l] b.d.f address\n"
	596	" - modify, auto increment CFG address\n"
	597	"pci write[.b, .w, .l] b.d.f address value\n"
088f1b19 KP	598	" - write to CFG address";
	599	#endif
	600
	601	U_BOOT_CMD(
	602	pci, 5, 1, do_pci,
	603	"list and access PCI Configuration Space", pci_help_text
8bde7f77	604	);