[J-u-boot.git] / common / cmd_pci.c

/*
 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Andreas Heppel <[email protected]>
 *
 * (C) Copyright 2002
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 * Wolfgang Grandegger, DENX Software Engineering, [email protected].
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * PCI routines
 */

#include <common.h>
#include <cli.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <pci.h>

/*
 * Follows routines for the output of infos about devices on PCI bus.
 */

void pci_header_show(pci_dev_t dev);
void pci_header_show_brief(pci_dev_t dev);

/*
 * Subroutine:  pciinfo
 *
 * Description: Show information about devices on PCI bus.
 *				Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
 *				the output will be more or less exhaustive.
 *
 * Inputs:	bus_no		the number of the bus to be scanned.
 *
 * Return:      None
 *
 */
void pciinfo(int BusNum, int ShortPCIListing)
{
	int Device;
	int Function;
	unsigned char HeaderType;
	unsigned short VendorID;
	pci_dev_t dev;

	printf("Scanning PCI devices on bus %d\n", BusNum);

	if (ShortPCIListing) {
		printf("BusDevFun  VendorId   DeviceId   Device Class       Sub-Class\n");
		printf("_____________________________________________________________\n");
	}

	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
		HeaderType = 0;
		VendorID = 0;
		for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
			/*
			 * If this is not a multi-function device, we skip the rest.
			 */
			if (Function && !(HeaderType & 0x80))
				break;

			dev = PCI_BDF(BusNum, Device, Function);

			pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
			if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
				continue;

			if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);

			if (ShortPCIListing)
			{
				printf("%02x.%02x.%02x   ", BusNum, Device, Function);
				pci_header_show_brief(dev);
			}
			else
			{
				printf("\nFound PCI device %02x.%02x.%02x:\n",
				       BusNum, Device, Function);
				pci_header_show(dev);
			}
	    }
    }
}


/*
 * Subroutine:  pci_header_show_brief
 *
 * Description: Reads and prints the header of the
 *		specified PCI device in short form.
 *
 * Inputs:	dev      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show_brief(pci_dev_t dev)
{
	u16 vendor, device;
	u8 class, subclass;

	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);

	printf("0x%.4x     0x%.4x     %-23s 0x%.2x\n",
	       vendor, device,
	       pci_class_str(class), subclass);
}

/*
 * Subroutine:  PCI_Header_Show
 *
 * Description: Reads the header of the specified PCI device.
 *
 * Inputs:		BusDevFunc      Bus+Device+Function number
 *
 * Return:      None
 *
 */
void pci_header_show(pci_dev_t dev)
{
	u8 _byte, header_type;
	u16 _word;
	u32 _dword;

#define PRINT(msg, type, reg) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type)

#define PRINT2(msg, type, reg, func) \
	pci_read_config_##type(dev, reg, &_##type); \
	printf(msg, _##type, func(_##type))

	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);

	PRINT ("  vendor ID =                   0x%.4x\n", word, PCI_VENDOR_ID);
	PRINT ("  device ID =                   0x%.4x\n", word, PCI_DEVICE_ID);
	PRINT ("  command register =            0x%.4x\n", word, PCI_COMMAND);
	PRINT ("  status register =             0x%.4x\n", word, PCI_STATUS);
	PRINT ("  revision ID =                 0x%.2x\n", byte, PCI_REVISION_ID);
	PRINT2("  class code =                  0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
								pci_class_str);
	PRINT ("  sub class code =              0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	PRINT ("  programming interface =       0x%.2x\n", byte, PCI_CLASS_PROG);
	PRINT ("  cache line =                  0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	PRINT ("  latency time =                0x%.2x\n", byte, PCI_LATENCY_TIMER);
	PRINT ("  header type =                 0x%.2x\n", byte, PCI_HEADER_TYPE);
	PRINT ("  BIST =                        0x%.2x\n", byte, PCI_BIST);
	PRINT ("  base address 0 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_0);

	switch (header_type & 0x03) {
	case PCI_HEADER_TYPE_NORMAL:	/* "normal" PCI device */
		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  base address 2 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
		PRINT ("  base address 3 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
		PRINT ("  base address 4 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
		PRINT ("  base address 5 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
		PRINT ("  cardBus CIS pointer =         0x%.8x\n", dword, PCI_CARDBUS_CIS);
		PRINT ("  sub system vendor ID =        0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
		PRINT ("  sub system ID =               0x%.4x\n", word, PCI_SUBSYSTEM_ID);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  min Grant =                   0x%.2x\n", byte, PCI_MIN_GNT);
		PRINT ("  max Latency =                 0x%.2x\n", byte, PCI_MAX_LAT);
		break;

	case PCI_HEADER_TYPE_BRIDGE:	/* PCI-to-PCI bridge */

		PRINT ("  base address 1 =              0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_PRIMARY_BUS);
		PRINT ("  secondary bus number =        0x%.2x\n", byte, PCI_SECONDARY_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
		PRINT ("  secondary latency timer =     0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
		PRINT ("  IO base =                     0x%.2x\n", byte, PCI_IO_BASE);
		PRINT ("  IO limit =                    0x%.2x\n", byte, PCI_IO_LIMIT);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_SEC_STATUS);
		PRINT ("  memory base =                 0x%.4x\n", word, PCI_MEMORY_BASE);
		PRINT ("  memory limit =                0x%.4x\n", word, PCI_MEMORY_LIMIT);
		PRINT ("  prefetch memory base =        0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
		PRINT ("  prefetch memory limit =       0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
		PRINT ("  prefetch memory base upper =  0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
		PRINT ("  prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
		PRINT ("  IO base upper 16 bits =       0x%.4x\n", word, PCI_IO_BASE_UPPER16);
		PRINT ("  IO limit upper 16 bits =      0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
		PRINT ("  expansion ROM base address =  0x%.8x\n", dword, PCI_ROM_ADDRESS1);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_BRIDGE_CONTROL);
		break;

	case PCI_HEADER_TYPE_CARDBUS:	/* PCI-to-CardBus bridge */

		PRINT ("  capabilities =                0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
		PRINT ("  secondary status =            0x%.4x\n", word, PCI_CB_SEC_STATUS);
		PRINT ("  primary bus number =          0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
		PRINT ("  CardBus number =              0x%.2x\n", byte, PCI_CB_CARD_BUS);
		PRINT ("  subordinate bus number =      0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
		PRINT ("  CardBus latency timer =       0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
		PRINT ("  CardBus memory base 0 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
		PRINT ("  CardBus memory limit 0 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
		PRINT ("  CardBus memory base 1 =       0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
		PRINT ("  CardBus memory limit 1 =      0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
		PRINT ("  CardBus IO base 0 =           0x%.4x\n", word, PCI_CB_IO_BASE_0);
		PRINT ("  CardBus IO base high 0 =      0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
		PRINT ("  CardBus IO limit 0 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
		PRINT ("  CardBus IO limit high 0 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
		PRINT ("  CardBus IO base 1 =           0x%.4x\n", word, PCI_CB_IO_BASE_1);
		PRINT ("  CardBus IO base high 1 =      0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
		PRINT ("  CardBus IO limit 1 =          0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
		PRINT ("  CardBus IO limit high 1 =     0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
		PRINT ("  interrupt line =              0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		PRINT ("  interrupt pin =               0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		PRINT ("  bridge control =              0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
		PRINT ("  subvendor ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
		PRINT ("  subdevice ID =                0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
		PRINT ("  PC Card 16bit base address =  0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
		break;

	default:
		printf("unknown header\n");
		break;
    }

#undef PRINT
#undef PRINT2
}

/* Convert the "bus.device.function" identifier into a number.
 */
static pci_dev_t get_pci_dev(char* name)
{
	char cnum[12];
	int len, i, iold, n;
	int bdfs[3] = {0,0,0};

	len = strlen(name);
	if (len > 8)
		return -1;
	for (i = 0, iold = 0, n = 0; i < len; i++) {
		if (name[i] == '.') {
			memcpy(cnum, &name[iold], i - iold);
			cnum[i - iold] = '\0';
			bdfs[n++] = simple_strtoul(cnum, NULL, 16);
			iold = i + 1;
		}
	}
	strcpy(cnum, &name[iold]);
	if (n == 0)
		n = 1;
	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}

static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
{
#define DISP_LINE_LEN	16
	ulong i, nbytes, linebytes;
	int rc = 0;

	if (length == 0)
		length = 0x40 / size; /* Standard PCI configuration space */

	/* Print the lines.
	 * once, and all accesses are with the specified bus width.
	 */
	nbytes = length * size;
	do {
		uint	val4;
		ushort  val2;
		u_char	val1;

		printf("%08lx:", addr);
		linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
		for (i=0; i<linebytes; i+= size) {
			if (size == 4) {
				pci_read_config_dword(bdf, addr, &val4);
				printf(" %08x", val4);
			} else if (size == 2) {
				pci_read_config_word(bdf, addr, &val2);
				printf(" %04x", val2);
			} else {
				pci_read_config_byte(bdf, addr, &val1);
				printf(" %02x", val1);
			}
			addr += size;
		}
		printf("\n");
		nbytes -= linebytes;
		if (ctrlc()) {
			rc = 1;
			break;
		}
	} while (nbytes > 0);

	return (rc);
}

static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
{
	if (size == 4) {
		pci_write_config_dword(bdf, addr, value);
	}
	else if (size == 2) {
		ushort val = value & 0xffff;
		pci_write_config_word(bdf, addr, val);
	}
	else {
		u_char val = value & 0xff;
		pci_write_config_byte(bdf, addr, val);
	}
	return 0;
}

static int
pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
{
	ulong	i;
	int	nbytes;
	uint	val4;
	ushort  val2;
	u_char	val1;

	/* Print the address, followed by value.  Then accept input for
	 * the next value.  A non-converted value exits.
	 */
	do {
		printf("%08lx:", addr);
		if (size == 4) {
			pci_read_config_dword(bdf, addr, &val4);
			printf(" %08x", val4);
		}
		else if (size == 2) {
			pci_read_config_word(bdf, addr, &val2);
			printf(" %04x", val2);
		}
		else {
			pci_read_config_byte(bdf, addr, &val1);
			printf(" %02x", val1);
		}

		nbytes = readline (" ? ");
		if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
			/* <CR> pressed as only input, don't modify current
			 * location and move to next. "-" pressed will go back.
			 */
			if (incrflag)
				addr += nbytes ? -size : size;
			nbytes = 1;
#ifdef CONFIG_BOOT_RETRY_TIME
			reset_cmd_timeout(); /* good enough to not time out */
#endif
		}
#ifdef CONFIG_BOOT_RETRY_TIME
		else if (nbytes == -2) {
			break;	/* timed out, exit the command	*/
		}
#endif
		else {
			char *endp;
			i = simple_strtoul(console_buffer, &endp, 16);
			nbytes = endp - console_buffer;
			if (nbytes) {
#ifdef CONFIG_BOOT_RETRY_TIME
				/* good enough to not time out
				 */
				reset_cmd_timeout();
#endif
				pci_cfg_write (bdf, addr, size, i);
				if (incrflag)
					addr += size;
			}
		}
	} while (nbytes);

	return 0;
}

/* PCI Configuration Space access commands
 *
 * Syntax:
 *	pci display[.b, .w, .l] bus.device.function} [addr] [len]
 *	pci next[.b, .w, .l] bus.device.function [addr]
 *      pci modify[.b, .w, .l] bus.device.function [addr]
 *      pci write[.b, .w, .l] bus.device.function addr value
 */
static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong addr = 0, value = 0, size = 0;
	pci_dev_t bdf = 0;
	char cmd = 's';

	if (argc > 1)
		cmd = argv[1][0];

	switch (cmd) {
	case 'd':		/* display */
	case 'n':		/* next */
	case 'm':		/* modify */
	case 'w':		/* write */
		/* Check for a size specification. */
		size = cmd_get_data_size(argv[1], 4);
		if (argc > 3)
			addr = simple_strtoul(argv[3], NULL, 16);
		if (argc > 4)
			value = simple_strtoul(argv[4], NULL, 16);
	case 'h':		/* header */
		if (argc < 3)
			goto usage;
		if ((bdf = get_pci_dev(argv[2])) == -1)
			return 1;
		break;
#ifdef CONFIG_CMD_PCI_ENUM
	case 'e':
		break;
#endif
	default:		/* scan bus */
		value = 1; /* short listing */
		bdf = 0;   /* bus number  */
		if (argc > 1) {
			if (argv[argc-1][0] == 'l') {
				value = 0;
				argc--;
			}
			if (argc > 1)
				bdf = simple_strtoul(argv[1], NULL, 16);
		}
		pciinfo(bdf, value);
		return 0;
	}

	switch (argv[1][0]) {
	case 'h':		/* header */
		pci_header_show(bdf);
		return 0;
	case 'd':		/* display */
		return pci_cfg_display(bdf, addr, size, value);
#ifdef CONFIG_CMD_PCI_ENUM
	case 'e':
		pci_init();
		return 0;
#endif
	case 'n':		/* next */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 0);
	case 'm':		/* modify */
		if (argc < 4)
			goto usage;
		return pci_cfg_modify(bdf, addr, size, value, 1);
	case 'w':		/* write */
		if (argc < 5)
			goto usage;
		return pci_cfg_write(bdf, addr, size, value);
	}

	return 1;
 usage:
	return CMD_RET_USAGE;
}

/***************************************************/

#ifdef CONFIG_SYS_LONGHELP
static char pci_help_text[] =
	"[bus] [long]\n"
	"    - short or long list of PCI devices on bus 'bus'\n"
#ifdef CONFIG_CMD_PCI_ENUM
	"pci enum\n"
	"    - re-enumerate PCI buses\n"
#endif
	"pci header b.d.f\n"
	"    - show header of PCI device 'bus.device.function'\n"
	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	"    - display PCI configuration space (CFG)\n"
	"pci next[.b, .w, .l] b.d.f address\n"
	"    - modify, read and keep CFG address\n"
	"pci modify[.b, .w, .l] b.d.f address\n"
	"    -  modify, auto increment CFG address\n"
	"pci write[.b, .w, .l] b.d.f address value\n"
	"    - write to CFG address";
#endif

U_BOOT_CMD(
	pci,	5,	1,	do_pci,
	"list and access PCI Configuration Space", pci_help_text
);
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	3	* Andreas Heppel <[email protected]>
	4	*
	5	* (C) Copyright 2002
	6	* Wolfgang Denk, DENX Software Engineering, [email protected].
	7	* Wolfgang Grandegger, DENX Software Engineering, [email protected].
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	10	*/
	11
	12	/*
	13	* PCI routines
	14	*/
	15
	16	#include <common.h>
18d66533	17	#include <cli.h>
c609719b	18	#include <command.h>
c609719b WD	19	#include <asm/processor.h>
c609719b WD	20	#include <asm/io.h>
c609719b WD	21	#include <pci.h>
c609719b WD	22
c609719b WD	23	/*
	24	* Follows routines for the output of infos about devices on PCI bus.
	25	*/
	26
	27	void pci_header_show(pci_dev_t dev);
	28	void pci_header_show_brief(pci_dev_t dev);
	29
	30	/*
	31	* Subroutine: pciinfo
	32	*
	33	* Description: Show information about devices on PCI bus.
6d0f6bcf	34	* Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
c609719b WD	35	* the output will be more or less exhaustive.
	36	*
	37	* Inputs: bus_no the number of the bus to be scanned.
	38	*
	39	* Return: None
	40	*
	41	*/
	42	void pciinfo(int BusNum, int ShortPCIListing)
	43	{
	44	int Device;
	45	int Function;
	46	unsigned char HeaderType;
	47	unsigned short VendorID;
	48	pci_dev_t dev;
	49
	50	printf("Scanning PCI devices on bus %d\n", BusNum);
	51
	52	if (ShortPCIListing) {
	53	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
	54	printf("_____________________________________________________________\n");
	55	}
	56
	57	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
	58	HeaderType = 0;
	59	VendorID = 0;
	60	for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
	61	/*
	62	* If this is not a multi-function device, we skip the rest.
	63	*/
	64	if (Function && !(HeaderType & 0x80))
	65	break;
	66
	67	dev = PCI_BDF(BusNum, Device, Function);
	68
	69	pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
	70	if ((VendorID == 0xFFFF) \|\| (VendorID == 0x0000))
	71	continue;
	72
c7de829c	73	if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
c609719b WD	74
	75	if (ShortPCIListing)
	76	{
	77	printf("%02x.%02x.%02x ", BusNum, Device, Function);
	78	pci_header_show_brief(dev);
	79	}
	80	else
	81	{
	82	printf("\nFound PCI device %02x.%02x.%02x:\n",
	83	BusNum, Device, Function);
	84	pci_header_show(dev);
	85	}
	86	}
	87	}
	88	}
	89
c609719b WD	90
	91	/*
	92	* Subroutine: pci_header_show_brief
	93	*
	94	* Description: Reads and prints the header of the
53677ef1	95	* specified PCI device in short form.
c609719b WD	96	*
	97	* Inputs: dev Bus+Device+Function number
	98	*
	99	* Return: None
	100	*
	101	*/
	102	void pci_header_show_brief(pci_dev_t dev)
	103	{
	104	u16 vendor, device;
	105	u8 class, subclass;
	106
	107	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
	108	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
	109	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
	110	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
	111
5d232d0e	112	printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
c609719b	113	vendor, device,
983eb9d1	114	pci_class_str(class), subclass);
c609719b WD	115	}
	116
	117	/*
	118	* Subroutine: PCI_Header_Show
	119	*
	120	* Description: Reads the header of the specified PCI device.
	121	*
	122	* Inputs: BusDevFunc Bus+Device+Function number
	123	*
	124	* Return: None
	125	*
	126	*/
	127	void pci_header_show(pci_dev_t dev)
	128	{
	129	u8 _byte, header_type;
	130	u16 _word;
	131	u32 _dword;
	132
	133	#define PRINT(msg, type, reg) \
	134	pci_read_config_##type(dev, reg, &_##type); \
	135	printf(msg, _##type)
	136
	137	#define PRINT2(msg, type, reg, func) \
	138	pci_read_config_##type(dev, reg, &_##type); \
	139	printf(msg, _##type, func(_##type))
	140
	141	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
	142
	143	PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
	144	PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
	145	PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
	146	PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
	147	PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
	148	PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
983eb9d1	149	pci_class_str);
c609719b WD	150	PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
	151	PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
	152	PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
	153	PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
	154	PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
	155	PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
	156	PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
c609719b	157
7c7a23bd WD	158	switch (header_type & 0x03) {
	159	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
	160	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
	161	PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
	162	PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
	163	PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
	164	PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
	165	PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
	166	PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
	167	PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
	168	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
	169	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	170	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	171	PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
	172	PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
	173	break;
8bde7f77	174
7c7a23bd WD	175	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
	176
	177	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
c609719b WD	178	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
	179	PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
	180	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
	181	PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
	182	PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
	183	PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
	184	PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
	185	PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
	186	PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
	187	PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
	188	PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
	189	PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
	190	PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
	191	PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
	192	PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
	193	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
	194	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	195	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	196	PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
7c7a23bd WD	197	break;
	198
	199	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
	200
	201	PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
	202	PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
	203	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
	204	PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
	205	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
8bde7f77	206	PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
7c7a23bd WD	207	PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
	208	PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
	209	PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
	210	PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
	211	PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
	212	PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
	213	PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
	214	PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
	215	PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
	216	PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
	217	PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
	218	PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
	219	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
	220	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
	221	PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
	222	PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
	223	PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
	224	PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
	225	break;
8bde7f77	226
7c7a23bd WD	227	default:
7c7a23bd WD	228	printf("unknown header\n");
8bde7f77	229	break;
c609719b WD	230	}
	231
	232	#undef PRINT
	233	#undef PRINT2
	234	}
	235
	236	/* Convert the "bus.device.function" identifier into a number.
	237	*/
	238	static pci_dev_t get_pci_dev(char* name)
	239	{
	240	char cnum[12];
	241	int len, i, iold, n;
	242	int bdfs[3] = {0,0,0};
	243
	244	len = strlen(name);
	245	if (len > 8)
	246	return -1;
	247	for (i = 0, iold = 0, n = 0; i < len; i++) {
	248	if (name[i] == '.') {
	249	memcpy(cnum, &name[iold], i - iold);
	250	cnum[i - iold] = '\0';
	251	bdfs[n++] = simple_strtoul(cnum, NULL, 16);
	252	iold = i + 1;
	253	}
	254	}
	255	strcpy(cnum, &name[iold]);
	256	if (n == 0)
	257	n = 1;
	258	bdfs[n] = simple_strtoul(cnum, NULL, 16);
	259	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
	260	}
	261
	262	static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
	263	{
	264	#define DISP_LINE_LEN 16
	265	ulong i, nbytes, linebytes;
	266	int rc = 0;
	267
	268	if (length == 0)
	269	length = 0x40 / size; /* Standard PCI configuration space */
	270
	271	/* Print the lines.
	272	* once, and all accesses are with the specified bus width.
	273	*/
	274	nbytes = length * size;
	275	do {
	276	uint val4;
	277	ushort val2;
	278	u_char val1;
	279
	280	printf("%08lx:", addr);
	281	linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
	282	for (i=0; i<linebytes; i+= size) {
	283	if (size == 4) {
	284	pci_read_config_dword(bdf, addr, &val4);
	285	printf(" %08x", val4);
	286	} else if (size == 2) {
	287	pci_read_config_word(bdf, addr, &val2);
	288	printf(" %04x", val2);
	289	} else {
	290	pci_read_config_byte(bdf, addr, &val1);
	291	printf(" %02x", val1);
	292	}
	293	addr += size;
294	}
295	printf("\n");
296	nbytes -= linebytes;
297	if (ctrlc()) {
298	rc = 1;
299	break;
300	}
301	} while (nbytes > 0);
302
303	return (rc);
304	}
305
306	static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
307	{
308	if (size == 4) {
309	pci_write_config_dword(bdf, addr, value);
310	}
311	else if (size == 2) {
312	ushort val = value & 0xffff;
313	pci_write_config_word(bdf, addr, val);
314	}
315	else {
316	u_char val = value & 0xff;
317	pci_write_config_byte(bdf, addr, val);
318	}
319	return 0;
320	}
321
322	static int
323	pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
324	{
325	ulong i;
326	int nbytes;
c609719b WD	327	uint val4;
	328	ushort val2;
	329	u_char val1;
	330
	331	/* Print the address, followed by value. Then accept input for
	332	* the next value. A non-converted value exits.
	333	*/
	334	do {
	335	printf("%08lx:", addr);
	336	if (size == 4) {
	337	pci_read_config_dword(bdf, addr, &val4);
	338	printf(" %08x", val4);
	339	}
	340	else if (size == 2) {
	341	pci_read_config_word(bdf, addr, &val2);
	342	printf(" %04x", val2);
	343	}
	344	else {
	345	pci_read_config_byte(bdf, addr, &val1);
	346	printf(" %02x", val1);
	347	}
	348
	349	nbytes = readline (" ? ");
	350	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
	351	/* <CR> pressed as only input, don't modify current
	352	* location and move to next. "-" pressed will go back.
	353	*/
	354	if (incrflag)
	355	addr += nbytes ? -size : size;
	356	nbytes = 1;
	357	#ifdef CONFIG_BOOT_RETRY_TIME
	358	reset_cmd_timeout(); /* good enough to not time out */
	359	#endif
	360	}
	361	#ifdef CONFIG_BOOT_RETRY_TIME
	362	else if (nbytes == -2) {
	363	break; /* timed out, exit the command */
	364	}
	365	#endif
	366	else {
	367	char *endp;
	368	i = simple_strtoul(console_buffer, &endp, 16);
	369	nbytes = endp - console_buffer;
	370	if (nbytes) {
	371	#ifdef CONFIG_BOOT_RETRY_TIME
	372	/* good enough to not time out
	373	*/
	374	reset_cmd_timeout();
	375	#endif
	376	pci_cfg_write (bdf, addr, size, i);
	377	if (incrflag)
	378	addr += size;
	379	}
	380	}
	381	} while (nbytes);
	382
	383	return 0;
	384	}
	385
	386	/* PCI Configuration Space access commands
	387	*
	388	* Syntax:
	389	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
	390	* pci next[.b, .w, .l] bus.device.function [addr]
391	* pci modify[.b, .w, .l] bus.device.function [addr]
392	* pci write[.b, .w, .l] bus.device.function addr value
393	*/
088f1b19	394	static int do_pci(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
c609719b WD	395	{
	396	ulong addr = 0, value = 0, size = 0;
	397	pci_dev_t bdf = 0;
	398	char cmd = 's';
	399
	400	if (argc > 1)
	401	cmd = argv[1][0];
	402
	403	switch (cmd) {
	404	case 'd': /* display */
	405	case 'n': /* next */
	406	case 'm': /* modify */
	407	case 'w': /* write */
	408	/* Check for a size specification. */
	409	size = cmd_get_data_size(argv[1], 4);
	410	if (argc > 3)
	411	addr = simple_strtoul(argv[3], NULL, 16);
	412	if (argc > 4)
	413	value = simple_strtoul(argv[4], NULL, 16);
	414	case 'h': /* header */
	415	if (argc < 3)
	416	goto usage;
	417	if ((bdf = get_pci_dev(argv[2])) == -1)
	418	return 1;
	419	break;
96d61603 JS	420	#ifdef CONFIG_CMD_PCI_ENUM
	421	case 'e':
	422	break;
	423	#endif
c609719b WD	424	default: /* scan bus */
	425	value = 1; /* short listing */
	426	bdf = 0; /* bus number */
	427	if (argc > 1) {
	428	if (argv[argc-1][0] == 'l') {
	429	value = 0;
	430	argc--;
	431	}
	432	if (argc > 1)
	433	bdf = simple_strtoul(argv[1], NULL, 16);
	434	}
	435	pciinfo(bdf, value);
	436	return 0;
	437	}
	438
	439	switch (argv[1][0]) {
	440	case 'h': /* header */
	441	pci_header_show(bdf);
	442	return 0;
	443	case 'd': /* display */
	444	return pci_cfg_display(bdf, addr, size, value);
96d61603 JS	445	#ifdef CONFIG_CMD_PCI_ENUM
	446	case 'e':
	447	pci_init();
	448	return 0;
	449	#endif
c609719b WD	450	case 'n': /* next */
	451	if (argc < 4)
	452	goto usage;
	453	return pci_cfg_modify(bdf, addr, size, value, 0);
	454	case 'm': /* modify */
	455	if (argc < 4)
	456	goto usage;
	457	return pci_cfg_modify(bdf, addr, size, value, 1);
	458	case 'w': /* write */
	459	if (argc < 5)
	460	goto usage;
	461	return pci_cfg_write(bdf, addr, size, value);
	462	}
	463
	464	return 1;
	465	usage:
4c12eeb8	466	return CMD_RET_USAGE;
c609719b WD	467	}
c609719b WD	468
8bde7f77 WD	469	/***************************************************/
8bde7f77 WD	470
088f1b19 KP	471	#ifdef CONFIG_SYS_LONGHELP
088f1b19 KP	472	static char pci_help_text[] =
8bde7f77 WD	473	"[bus] [long]\n"
8bde7f77 WD	474	" - short or long list of PCI devices on bus 'bus'\n"
96d61603 JS	475	#ifdef CONFIG_CMD_PCI_ENUM
	476	"pci enum\n"
	477	" - re-enumerate PCI buses\n"
	478	#endif
8bde7f77 WD	479	"pci header b.d.f\n"
	480	" - show header of PCI device 'bus.device.function'\n"
	481	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
	482	" - display PCI configuration space (CFG)\n"
	483	"pci next[.b, .w, .l] b.d.f address\n"
	484	" - modify, read and keep CFG address\n"
	485	"pci modify[.b, .w, .l] b.d.f address\n"
	486	" - modify, auto increment CFG address\n"
	487	"pci write[.b, .w, .l] b.d.f address value\n"
088f1b19 KP	488	" - write to CFG address";
	489	#endif
	490
	491	U_BOOT_CMD(
	492	pci, 5, 1, do_pci,
	493	"list and access PCI Configuration Space", pci_help_text
8bde7f77	494	);