[J-u-boot.git] / include / configs / colibri_pxa270.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Toradex Colibri PXA270 configuration file
 *
 * Copyright (C) 2010 Marek Vasut <[email protected]>
 * Copyright (C) 2015-2016 Marcel Ziswiler <[email protected]>
 */

#ifndef	__CONFIG_H
#define	__CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT		0x40000

/*
 * Environment settings
 */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
#define	CONFIG_ARCH_CPU_INIT
#define	CONFIG_BOOTCOMMAND						\
	"if fatload mmc 0 0xa0000000 uImage; then "			\
		"bootm 0xa0000000; "					\
	"fi; "								\
	"if usb reset && fatload usb 0 0xa0000000 uImage; then "	\
		"bootm 0xa0000000; "					\
	"fi; "								\
	"bootm 0xc0000;"
#define	CONFIG_TIMESTAMP
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS

/*
 * Serial Console Configuration
 */

/*
 * Bootloader Components Configuration
 */

/* I2C support */
#ifdef CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PXA
#define CONFIG_PXA_STD_I2C
#define CONFIG_PXA_PWR_I2C
#define CONFIG_SYS_I2C_SPEED		100000
#endif

/* LCD support */
#ifdef CONFIG_LCD
#define CONFIG_PXA_LCD
#define CONFIG_PXA_VGA
#define CONFIG_LCD_LOGO
#endif

/*
 * Networking Configuration
 */
#ifdef	CONFIG_CMD_NET

#define	CONFIG_DRIVER_DM9000		1
#define CONFIG_DM9000_BASE		0x08000000
#define DM9000_IO			(CONFIG_DM9000_BASE)
#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
#define	CONFIG_NET_RETRY_COUNT		10

#define	CONFIG_BOOTP_BOOTFILESIZE
#endif

#define	CONFIG_SYS_DEVICE_NULLDEV	1

/*
 * Clock Configuration
 */
#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */

/*
 * DRAM Map
 */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x04000000	/* 64 MB DRAM */

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000

/*
 * NOR FLASH
 */
#ifdef	CONFIG_CMD_FLASH
#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define	PHYS_FLASH_SIZE			0x02000000	/* 32 MB */
#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define	CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_32BIT

#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
#define	CONFIG_SYS_MAX_FLASH_BANKS	1

#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25 * CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25 * CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_LOCK_TOUT	(25 * CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_UNLOCK_TOUT	(25 * CONFIG_SYS_HZ)
#endif

#define	CONFIG_SYS_MONITOR_BASE		0x0
#define	CONFIG_SYS_MONITOR_LEN		0x40000

/* Skip factory configuration block */
#define	CONFIG_ENV_ADDR			\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
#define	CONFIG_ENV_SIZE			0x40000
#define	CONFIG_ENV_SECT_SIZE		0x40000

/*
 * GPIO settings
 */
#define	CONFIG_SYS_GPSR0_VAL	0x00000000
#define	CONFIG_SYS_GPSR1_VAL	0x00020000
#define	CONFIG_SYS_GPSR2_VAL	0x0002c000
#define	CONFIG_SYS_GPSR3_VAL	0x00000000

#define	CONFIG_SYS_GPCR0_VAL	0x00000000
#define	CONFIG_SYS_GPCR1_VAL	0x00000000
#define	CONFIG_SYS_GPCR2_VAL	0x00000000
#define	CONFIG_SYS_GPCR3_VAL	0x00000000

#define	CONFIG_SYS_GPDR0_VAL	0xc8008000
#define	CONFIG_SYS_GPDR1_VAL	0xfc02a981
#define	CONFIG_SYS_GPDR2_VAL	0x92c3ffff
#define	CONFIG_SYS_GPDR3_VAL	0x0061e804

#define	CONFIG_SYS_GAFR0_L_VAL	0x80100000
#define	CONFIG_SYS_GAFR0_U_VAL	0xa5c00010
#define	CONFIG_SYS_GAFR1_L_VAL	0x6992901a
#define	CONFIG_SYS_GAFR1_U_VAL	0xaaa50008
#define	CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
#define	CONFIG_SYS_GAFR2_U_VAL	0x4109a002
#define	CONFIG_SYS_GAFR3_L_VAL	0x54000310
#define	CONFIG_SYS_GAFR3_U_VAL	0x00005401

#define	CONFIG_SYS_PSSR_VAL	0x30

/*
 * Clock settings
 */
#define	CONFIG_SYS_CKEN		0x00500240
#define	CONFIG_SYS_CCCR		0x02000290

/*
 * Memory settings
 */
#define	CONFIG_SYS_MSC0_VAL	0x9ee1c5f2
#define	CONFIG_SYS_MSC1_VAL	0x9ee1f994
#define	CONFIG_SYS_MSC2_VAL	0x9ee19ee1
#define	CONFIG_SYS_MDCNFG_VAL	0x090009c9
#define	CONFIG_SYS_MDREFR_VAL	0x2003a031
#define	CONFIG_SYS_MDMRS_VAL	0x00220022
#define	CONFIG_SYS_FLYCNFG_VAL	0x00010001
#define	CONFIG_SYS_SXCNFG_VAL	0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define	CONFIG_SYS_MECR_VAL	0x00000000
#define	CONFIG_SYS_MCMEM0_VAL	0x00028307
#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
#define	CONFIG_SYS_MCATT0_VAL	0x00038787
#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
#define	CONFIG_SYS_MCIO0_VAL	0x0002830f
#define	CONFIG_SYS_MCIO1_VAL	0x0001430f

#include "pxa-common.h"

#endif /* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
2e49984b MV	2	/*
	3	* Toradex Colibri PXA270 configuration file
	4	*
	5	* Copyright (C) 2010 Marek Vasut <[email protected]>
b891d010	6	* Copyright (C) 2015-2016 Marcel Ziswiler <[email protected]>
2e49984b MV	7	*/
2e49984b MV	8
7c49b523 MZ	9	#ifndef __CONFIG_H
7c49b523 MZ	10	#define __CONFIG_H
2e49984b MV	11
	12	/*
	13	* High Level Board Configuration Options
	14	*/
abc20aba	15	#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
7c49b523 MZ	16	/* Avoid overwriting factory configuration block */
7c49b523 MZ	17	#define CONFIG_BOARD_SIZE_LIMIT 0x40000
2e49984b	18
2e49984b MV	19	/*
	20	* Environment settings
	21	*/
f9f5486c MV	22	#define CONFIG_ENV_OVERWRITE
	23	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	24	#define CONFIG_ARCH_CPU_INIT
2e49984b	25	#define CONFIG_BOOTCOMMAND \
99d672fa	26	"if fatload mmc 0 0xa0000000 uImage; then " \
2e49984b MV	27	"bootm 0xa0000000; " \
	28	"fi; " \
	29	"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
	30	"bootm 0xa0000000; " \
	31	"fi; " \
99d672fa	32	"bootm 0xc0000;"
2e49984b	33	#define CONFIG_TIMESTAMP
2e49984b MV	34	#define CONFIG_CMDLINE_TAG
2e49984b MV	35	#define CONFIG_SETUP_MEMORY_TAGS
2e49984b MV	36
	37	/*
	38	* Serial Console Configuration
	39	*/
2e49984b MV	40
	41	/*
	42	* Bootloader Components Configuration
	43	*/
2e49984b	44
3664fa1b MZ	45	/* I2C support */
3664fa1b MZ	46	#ifdef CONFIG_SYS_I2C
3664fa1b MZ	47	#define CONFIG_SYS_I2C_PXA
	48	#define CONFIG_PXA_STD_I2C
	49	#define CONFIG_PXA_PWR_I2C
	50	#define CONFIG_SYS_I2C_SPEED 100000
	51	#endif
	52
4f9bbd9e MZ	53	/* LCD support */
	54	#ifdef CONFIG_LCD
	55	#define CONFIG_PXA_LCD
	56	#define CONFIG_PXA_VGA
4f9bbd9e MZ	57	#define CONFIG_LCD_LOGO
	58	#endif
	59
2e49984b MV	60	/*
2e49984b MV	61	* Networking Configuration
2e49984b MV	62	*/
2e49984b MV	63	#ifdef CONFIG_CMD_NET
2e49984b	64
2e49984b MV	65	#define CONFIG_DRIVER_DM9000 1
	66	#define CONFIG_DM9000_BASE 0x08000000
	67	#define DM9000_IO (CONFIG_DM9000_BASE)
	68	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	69	#define CONFIG_NET_RETRY_COUNT 10
	70
	71	#define CONFIG_BOOTP_BOOTFILESIZE
2e49984b MV	72	#endif
2e49984b MV	73
2e49984b	74	#define CONFIG_SYS_DEVICE_NULLDEV 1
f9f5486c	75
2e49984b MV	76	/*
	77	* Clock Configuration
	78	*/
f9f5486c	79	#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
2e49984b	80
2e49984b MV	81	/*
	82	* DRAM Map
	83	*/
2e49984b MV	84	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	85	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	86
	87	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	88	#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
	89
	90	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	91	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	92
f9f5486c	93	#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
6ef6eb91	94	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
f9f5486c	95	#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
6ef6eb91	96
2e49984b MV	97	/*
	98	* NOR FLASH
	99	*/
	100	#ifdef CONFIG_CMD_FLASH
	101	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
d817889b	102	#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
2e49984b MV	103	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
2e49984b MV	104
d817889b	105	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
2e49984b MV	106
	107	#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
	108	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	109
f9f5486c MV	110	#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
f9f5486c MV	111	#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
d817889b MZ	112	#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
d817889b MZ	113	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
2e49984b MV	114	#endif
2e49984b MV	115
f9f5486c	116	#define CONFIG_SYS_MONITOR_BASE 0x0
7c49b523	117	#define CONFIG_SYS_MONITOR_LEN 0x40000
2e49984b	118
7c49b523	119	/* Skip factory configuration block */
f9f5486c	120	#define CONFIG_ENV_ADDR \
7c49b523	121	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
f9f5486c MV	122	#define CONFIG_ENV_SIZE 0x40000
f9f5486c MV	123	#define CONFIG_ENV_SECT_SIZE 0x40000
2e49984b MV	124
	125	/*
	126	* GPIO settings
	127	*/
	128	#define CONFIG_SYS_GPSR0_VAL 0x00000000
	129	#define CONFIG_SYS_GPSR1_VAL 0x00020000
44ba7a37	130	#define CONFIG_SYS_GPSR2_VAL 0x0002c000
2e49984b MV	131	#define CONFIG_SYS_GPSR3_VAL 0x00000000
	132
	133	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	134	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	135	#define CONFIG_SYS_GPCR2_VAL 0x00000000
	136	#define CONFIG_SYS_GPCR3_VAL 0x00000000
	137
44ba7a37 MZ	138	#define CONFIG_SYS_GPDR0_VAL 0xc8008000
	139	#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
	140	#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
	141	#define CONFIG_SYS_GPDR3_VAL 0x0061e804
2e49984b	142
44ba7a37 MZ	143	#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
	144	#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
	145	#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
	146	#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
	147	#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
	148	#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
	149	#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
	150	#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
2e49984b MV	151
	152	#define CONFIG_SYS_PSSR_VAL 0x30
	153
	154	/*
	155	* Clock settings
	156	*/
	157	#define CONFIG_SYS_CKEN 0x00500240
	158	#define CONFIG_SYS_CCCR 0x02000290
	159
	160	/*
	161	* Memory settings
	162	*/
44ba7a37 MZ	163	#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
	164	#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
	165	#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
	166	#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
	167	#define CONFIG_SYS_MDREFR_VAL 0x2003a031
	168	#define CONFIG_SYS_MDMRS_VAL 0x00220022
	169	#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
2e49984b MV	170	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
	171
	172	/*
	173	* PCMCIA and CF Interfaces
	174	*/
44ba7a37 MZ	175	#define CONFIG_SYS_MECR_VAL 0x00000000
44ba7a37 MZ	176	#define CONFIG_SYS_MCMEM0_VAL 0x00028307
2e49984b	177	#define CONFIG_SYS_MCMEM1_VAL 0x00014307
44ba7a37	178	#define CONFIG_SYS_MCATT0_VAL 0x00038787
2e49984b	179	#define CONFIG_SYS_MCATT1_VAL 0x0001c787
44ba7a37	180	#define CONFIG_SYS_MCIO0_VAL 0x0002830f
2e49984b MV	181	#define CONFIG_SYS_MCIO1_VAL 0x0001430f
2e49984b MV	182
67a1f00c	183	#include "pxa-common.h"
2e49984b	184
7c49b523	185	#endif /* __CONFIG_H */