[J-u-boot.git] / include / configs / colibri_pxa270.h

/*
 * Toradex Colibri PXA270 configuration file
 *
 * Copyright (C) 2010 Marek Vasut <[email protected]>
 * Copyright (C) 2015 Marcel Ziswiler <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef	__CONFIG_H
#define	__CONFIG_H

/*
 * High Level Board Configuration Options
 */
#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
#define CONFIG_SYS_GENERIC_BOARD
#define	CONFIG_SYS_TEXT_BASE		0x0
/* Avoid overwriting factory configuration block */
#define CONFIG_BOARD_SIZE_LIMIT		0x40000

/*
 * Environment settings
 */
#define	CONFIG_ENV_OVERWRITE
#define	CONFIG_SYS_MALLOC_LEN		(128 * 1024)
#define	CONFIG_ARCH_CPU_INIT
#define	CONFIG_BOOTCOMMAND						\
	"if fatload mmc 0 0xa0000000 uImage; then "			\
		"bootm 0xa0000000; "					\
	"fi; "								\
	"if usb reset && fatload usb 0 0xa0000000 uImage; then "	\
		"bootm 0xa0000000; "					\
	"fi; "								\
	"bootm 0xc0000;"
#define	CONFIG_BOOTARGS			"console=tty0 console=ttyS0,115200"
#define	CONFIG_TIMESTAMP
#define	CONFIG_BOOTDELAY		2	/* Autoboot delay */
#define	CONFIG_CMDLINE_TAG
#define	CONFIG_SETUP_MEMORY_TAGS
#define	CONFIG_LZMA			/* LZMA compression support */
#define	CONFIG_OF_LIBFDT

/*
 * Serial Console Configuration
 */
#define	CONFIG_PXA_SERIAL
#define	CONFIG_FFUART			1
#define CONFIG_CONS_INDEX		3
#define	CONFIG_BAUDRATE			115200

/*
 * Bootloader Components Configuration
 */
#include <config_cmd_default.h>

#undef CONFIG_CMD_LOADB			/* Both together */
#undef CONFIG_CMD_LOADS			/* saves 10 KB */
#define	CONFIG_CMD_NET
#define	CONFIG_CMD_ENV
#undef	CONFIG_CMD_IMLS
#define	CONFIG_CMD_MMC
#define	CONFIG_CMD_USB
#define	CONFIG_CMD_FLASH

/*
 * Networking Configuration
 */
#ifdef	CONFIG_CMD_NET
#define	CONFIG_CMD_PING
#define	CONFIG_CMD_DHCP

#define	CONFIG_DRIVER_DM9000		1
#define CONFIG_DM9000_BASE		0x08000000
#define DM9000_IO			(CONFIG_DM9000_BASE)
#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
#define	CONFIG_NET_RETRY_COUNT		10

#define	CONFIG_BOOTP_BOOTFILESIZE
#define	CONFIG_BOOTP_BOOTPATH
#define	CONFIG_BOOTP_GATEWAY
#define	CONFIG_BOOTP_HOSTNAME
#endif

/*
 * HUSH Shell Configuration
 */
#define	CONFIG_SYS_HUSH_PARSER		1

#undef	CONFIG_SYS_LONGHELP		/* Saves 10 KB */
#ifdef	CONFIG_SYS_HUSH_PARSER
#define	CONFIG_SYS_PROMPT		"$ "
#else
#endif
#define	CONFIG_SYS_CBSIZE		256
#define	CONFIG_SYS_PBSIZE		\
	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define	CONFIG_SYS_MAXARGS		16
#define	CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define	CONFIG_SYS_DEVICE_NULLDEV	1
#define	CONFIG_CMDLINE_EDITING		1
#define	CONFIG_AUTO_COMPLETE		1

/*
 * Clock Configuration
 */
#define	CONFIG_SYS_CPUSPEED		0x290		/* 520MHz */

/*
 * DRAM Map
 */
#define	CONFIG_NR_DRAM_BANKS		1		/* We have 1 bank of DRAM */
#define	PHYS_SDRAM_1			0xa0000000	/* SDRAM Bank #1 */
#define	PHYS_SDRAM_1_SIZE		0x04000000	/* 64 MB */

#define	CONFIG_SYS_DRAM_BASE		0xa0000000	/* CS0 */
#define	CONFIG_SYS_DRAM_SIZE		0x04000000	/* 64 MB DRAM */

#define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM */

#define	CONFIG_SYS_LOAD_ADDR		PHYS_SDRAM_1
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define	CONFIG_SYS_INIT_SP_ADDR		0x5c010000

/*
 * NOR FLASH
 */
#ifdef	CONFIG_CMD_FLASH
#define	PHYS_FLASH_1			0x00000000	/* Flash Bank #1 */
#define	CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1

#define	CONFIG_SYS_FLASH_CFI
#define	CONFIG_FLASH_CFI_DRIVER		1

#define	CONFIG_SYS_MAX_FLASH_SECT	(4 + 255)
#define	CONFIG_SYS_MAX_FLASH_BANKS	1

#define	CONFIG_SYS_FLASH_ERASE_TOUT	(25 * CONFIG_SYS_HZ)
#define	CONFIG_SYS_FLASH_WRITE_TOUT	(25 * CONFIG_SYS_HZ)

#define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#define	CONFIG_SYS_FLASH_PROTECTION		1

#define CONFIG_ENV_IS_IN_FLASH		1

#else	/* No flash */
#define	CONFIG_SYS_NO_FLASH
#define	CONFIG_ENV_IS_NOWHERE
#endif

#define	CONFIG_SYS_MONITOR_BASE		0x0
#define	CONFIG_SYS_MONITOR_LEN		0x40000

/* Skip factory configuration block */
#define	CONFIG_ENV_ADDR			\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
#define	CONFIG_ENV_SIZE			0x40000
#define	CONFIG_ENV_SECT_SIZE		0x40000

/*
 * GPIO settings
 */
#define	CONFIG_SYS_GPSR0_VAL	0x00000000
#define	CONFIG_SYS_GPSR1_VAL	0x00020000
#define	CONFIG_SYS_GPSR2_VAL	0x0002C000
#define	CONFIG_SYS_GPSR3_VAL	0x00000000

#define	CONFIG_SYS_GPCR0_VAL	0x00000000
#define	CONFIG_SYS_GPCR1_VAL	0x00000000
#define	CONFIG_SYS_GPCR2_VAL	0x00000000
#define	CONFIG_SYS_GPCR3_VAL	0x00000000

#define	CONFIG_SYS_GPDR0_VAL	0x08000000
#define	CONFIG_SYS_GPDR1_VAL	0x0002A981
#define	CONFIG_SYS_GPDR2_VAL	0x0202FC00
#define	CONFIG_SYS_GPDR3_VAL	0x00000000

#define	CONFIG_SYS_GAFR0_L_VAL	0x00100000
#define	CONFIG_SYS_GAFR0_U_VAL	0x00C00010
#define	CONFIG_SYS_GAFR1_L_VAL	0x999A901A
#define	CONFIG_SYS_GAFR1_U_VAL	0xAAA00008
#define	CONFIG_SYS_GAFR2_L_VAL	0xAAAAAAAA
#define	CONFIG_SYS_GAFR2_U_VAL	0x0109A000
#define	CONFIG_SYS_GAFR3_L_VAL	0x54000300
#define	CONFIG_SYS_GAFR3_U_VAL	0x00024001

#define	CONFIG_SYS_PSSR_VAL	0x30

/*
 * Clock settings
 */
#define	CONFIG_SYS_CKEN		0x00500240
#define	CONFIG_SYS_CCCR		0x02000290

/*
 * Memory settings
 */
#define	CONFIG_SYS_MSC0_VAL	0x000095f2
#define	CONFIG_SYS_MSC1_VAL	0x00007ff4
#define	CONFIG_SYS_MSC2_VAL	0x00000000
#define	CONFIG_SYS_MDCNFG_VAL	0x08000ac9
#define	CONFIG_SYS_MDREFR_VAL	0x2013e01e
#define	CONFIG_SYS_MDMRS_VAL	0x00320032
#define	CONFIG_SYS_FLYCNFG_VAL	0x00000000
#define	CONFIG_SYS_SXCNFG_VAL	0x40044004

/*
 * PCMCIA and CF Interfaces
 */
#define	CONFIG_SYS_MECR_VAL	0x00000001
#define	CONFIG_SYS_MCMEM0_VAL	0x00014307
#define	CONFIG_SYS_MCMEM1_VAL	0x00014307
#define	CONFIG_SYS_MCATT0_VAL	0x0001c787
#define	CONFIG_SYS_MCATT1_VAL	0x0001c787
#define	CONFIG_SYS_MCIO0_VAL	0x0001430f
#define	CONFIG_SYS_MCIO1_VAL	0x0001430f

#include "pxa-common.h"

#endif /* __CONFIG_H */
Commit	Line	Data
2e49984b MV	1	/*
	2	* Toradex Colibri PXA270 configuration file
	3	*
	4	* Copyright (C) 2010 Marek Vasut <[email protected]>
85559679	5	* Copyright (C) 2015 Marcel Ziswiler <[email protected]>
2e49984b	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
2e49984b MV	8	*/
2e49984b MV	9
7c49b523 MZ	10	#ifndef __CONFIG_H
7c49b523 MZ	11	#define __CONFIG_H
2e49984b MV	12
	13	/*
	14	* High Level Board Configuration Options
	15	*/
abc20aba	16	#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
85559679	17	#define CONFIG_SYS_GENERIC_BOARD
f9f5486c	18	#define CONFIG_SYS_TEXT_BASE 0x0
7c49b523 MZ	19	/* Avoid overwriting factory configuration block */
7c49b523 MZ	20	#define CONFIG_BOARD_SIZE_LIMIT 0x40000
2e49984b	21
2e49984b MV	22	/*
	23	* Environment settings
	24	*/
f9f5486c MV	25	#define CONFIG_ENV_OVERWRITE
	26	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	27	#define CONFIG_ARCH_CPU_INIT
2e49984b	28	#define CONFIG_BOOTCOMMAND \
99d672fa	29	"if fatload mmc 0 0xa0000000 uImage; then " \
2e49984b MV	30	"bootm 0xa0000000; " \
	31	"fi; " \
	32	"if usb reset && fatload usb 0 0xa0000000 uImage; then " \
	33	"bootm 0xa0000000; " \
	34	"fi; " \
99d672fa	35	"bootm 0xc0000;"
2e49984b MV	36	#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200"
	37	#define CONFIG_TIMESTAMP
	38	#define CONFIG_BOOTDELAY 2 /* Autoboot delay */
	39	#define CONFIG_CMDLINE_TAG
	40	#define CONFIG_SETUP_MEMORY_TAGS
2e49984b	41	#define CONFIG_LZMA /* LZMA compression support */
f9f5486c	42	#define CONFIG_OF_LIBFDT
2e49984b MV	43
	44	/*
	45	* Serial Console Configuration
	46	*/
	47	#define CONFIG_PXA_SERIAL
	48	#define CONFIG_FFUART 1
ce6971cd	49	#define CONFIG_CONS_INDEX 3
2e49984b	50	#define CONFIG_BAUDRATE 115200
2e49984b MV	51
	52	/*
	53	* Bootloader Components Configuration
	54	*/
	55	#include <config_cmd_default.h>
	56
fe488a85 MZ	57	#undef CONFIG_CMD_LOADB /* Both together */
fe488a85 MZ	58	#undef CONFIG_CMD_LOADS /* saves 10 KB */
2e49984b MV	59	#define CONFIG_CMD_NET
	60	#define CONFIG_CMD_ENV
	61	#undef CONFIG_CMD_IMLS
	62	#define CONFIG_CMD_MMC
	63	#define CONFIG_CMD_USB
	64	#define CONFIG_CMD_FLASH
	65
	66	/*
	67	* Networking Configuration
2e49984b MV	68	*/
	69	#ifdef CONFIG_CMD_NET
	70	#define CONFIG_CMD_PING
	71	#define CONFIG_CMD_DHCP
	72
2e49984b MV	73	#define CONFIG_DRIVER_DM9000 1
	74	#define CONFIG_DM9000_BASE 0x08000000
	75	#define DM9000_IO (CONFIG_DM9000_BASE)
	76	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	77	#define CONFIG_NET_RETRY_COUNT 10
	78
	79	#define CONFIG_BOOTP_BOOTFILESIZE
	80	#define CONFIG_BOOTP_BOOTPATH
	81	#define CONFIG_BOOTP_GATEWAY
	82	#define CONFIG_BOOTP_HOSTNAME
	83	#endif
	84
2e49984b MV	85	/*
	86	* HUSH Shell Configuration
	87	*/
	88	#define CONFIG_SYS_HUSH_PARSER 1
2e49984b	89
fe488a85	90	#undef CONFIG_SYS_LONGHELP /* Saves 10 KB */
2e49984b	91	#ifdef CONFIG_SYS_HUSH_PARSER
f9f5486c	92	#define CONFIG_SYS_PROMPT "$ "
2e49984b	93	#else
2e49984b	94	#endif
f9f5486c MV	95	#define CONFIG_SYS_CBSIZE 256
	96	#define CONFIG_SYS_PBSIZE \
	97	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	98	#define CONFIG_SYS_MAXARGS 16
	99	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
2e49984b	100	#define CONFIG_SYS_DEVICE_NULLDEV 1
f9f5486c MV	101	#define CONFIG_CMDLINE_EDITING 1
	102	#define CONFIG_AUTO_COMPLETE 1
	103
2e49984b MV	104	/*
	105	* Clock Configuration
	106	*/
f9f5486c	107	#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
2e49984b	108
2e49984b MV	109	/*
	110	* DRAM Map
	111	*/
	112	#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
	113	#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
	114	#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
	115
	116	#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
	117	#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
	118
	119	#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
	120	#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
	121
f9f5486c	122	#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
6ef6eb91	123	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
f9f5486c	124	#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
6ef6eb91	125
2e49984b MV	126	/*
	127	* NOR FLASH
	128	*/
	129	#ifdef CONFIG_CMD_FLASH
	130	#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
	131	#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
	132
	133	#define CONFIG_SYS_FLASH_CFI
	134	#define CONFIG_FLASH_CFI_DRIVER 1
	135
	136	#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
	137	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	138
f9f5486c MV	139	#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
f9f5486c MV	140	#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
2e49984b MV	141
	142	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
	143	#define CONFIG_SYS_FLASH_PROTECTION 1
	144
	145	#define CONFIG_ENV_IS_IN_FLASH 1
	146
	147	#else /* No flash */
	148	#define CONFIG_SYS_NO_FLASH
50dea462	149	#define CONFIG_ENV_IS_NOWHERE
2e49984b MV	150	#endif
2e49984b MV	151
f9f5486c	152	#define CONFIG_SYS_MONITOR_BASE 0x0
7c49b523	153	#define CONFIG_SYS_MONITOR_LEN 0x40000
2e49984b	154
7c49b523	155	/* Skip factory configuration block */
f9f5486c	156	#define CONFIG_ENV_ADDR \
7c49b523	157	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000)
f9f5486c MV	158	#define CONFIG_ENV_SIZE 0x40000
f9f5486c MV	159	#define CONFIG_ENV_SECT_SIZE 0x40000
2e49984b MV	160
	161	/*
	162	* GPIO settings
	163	*/
	164	#define CONFIG_SYS_GPSR0_VAL 0x00000000
	165	#define CONFIG_SYS_GPSR1_VAL 0x00020000
	166	#define CONFIG_SYS_GPSR2_VAL 0x0002C000
	167	#define CONFIG_SYS_GPSR3_VAL 0x00000000
	168
	169	#define CONFIG_SYS_GPCR0_VAL 0x00000000
	170	#define CONFIG_SYS_GPCR1_VAL 0x00000000
	171	#define CONFIG_SYS_GPCR2_VAL 0x00000000
	172	#define CONFIG_SYS_GPCR3_VAL 0x00000000
	173
	174	#define CONFIG_SYS_GPDR0_VAL 0x08000000
	175	#define CONFIG_SYS_GPDR1_VAL 0x0002A981
	176	#define CONFIG_SYS_GPDR2_VAL 0x0202FC00
	177	#define CONFIG_SYS_GPDR3_VAL 0x00000000
	178
	179	#define CONFIG_SYS_GAFR0_L_VAL 0x00100000
	180	#define CONFIG_SYS_GAFR0_U_VAL 0x00C00010
	181	#define CONFIG_SYS_GAFR1_L_VAL 0x999A901A
	182	#define CONFIG_SYS_GAFR1_U_VAL 0xAAA00008
	183	#define CONFIG_SYS_GAFR2_L_VAL 0xAAAAAAAA
	184	#define CONFIG_SYS_GAFR2_U_VAL 0x0109A000
	185	#define CONFIG_SYS_GAFR3_L_VAL 0x54000300
	186	#define CONFIG_SYS_GAFR3_U_VAL 0x00024001
	187
	188	#define CONFIG_SYS_PSSR_VAL 0x30
	189
	190	/*
	191	* Clock settings
	192	*/
	193	#define CONFIG_SYS_CKEN 0x00500240
	194	#define CONFIG_SYS_CCCR 0x02000290
	195
	196	/*
	197	* Memory settings
	198	*/
	199	#define CONFIG_SYS_MSC0_VAL 0x000095f2
	200	#define CONFIG_SYS_MSC1_VAL 0x00007ff4
	201	#define CONFIG_SYS_MSC2_VAL 0x00000000
	202	#define CONFIG_SYS_MDCNFG_VAL 0x08000ac9
	203	#define CONFIG_SYS_MDREFR_VAL 0x2013e01e
	204	#define CONFIG_SYS_MDMRS_VAL 0x00320032
	205	#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
	206	#define CONFIG_SYS_SXCNFG_VAL 0x40044004
	207
	208	/*
	209	* PCMCIA and CF Interfaces
	210	*/
	211	#define CONFIG_SYS_MECR_VAL 0x00000001
	212	#define CONFIG_SYS_MCMEM0_VAL 0x00014307
	213	#define CONFIG_SYS_MCMEM1_VAL 0x00014307
	214	#define CONFIG_SYS_MCATT0_VAL 0x0001c787
	215	#define CONFIG_SYS_MCATT1_VAL 0x0001c787
	216	#define CONFIG_SYS_MCIO0_VAL 0x0001430f
	217	#define CONFIG_SYS_MCIO1_VAL 0x0001430f
	218
67a1f00c	219	#include "pxa-common.h"
2e49984b	220
7c49b523	221	#endif /* __CONFIG_H */