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c609719b
WD
1/*
2 * (C) Copyright 2001
3 * Gerald Van Baren, Custom IDEAS, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This provides a bit-banged interface to the ethernet MII management
26 * channel.
27 */
28
29#include <common.h>
30#include <miiphy.h>
5f184715 31#include <phy.h>
c609719b 32
63ff004c
MB
33#include <asm/types.h>
34#include <linux/list.h>
35#include <malloc.h>
36#include <net.h>
37
38/* local debug macro */
63ff004c
MB
39#undef MII_DEBUG
40
41#undef debug
42#ifdef MII_DEBUG
16a53238 43#define debug(fmt, args...) printf(fmt, ##args)
63ff004c 44#else
16a53238 45#define debug(fmt, args...)
63ff004c
MB
46#endif /* MII_DEBUG */
47
63ff004c
MB
48static struct list_head mii_devs;
49static struct mii_dev *current_mii;
50
0daac978
MF
51/*
52 * Lookup the mii_dev struct by the registered device name.
53 */
5f184715 54struct mii_dev *miiphy_get_dev_by_name(const char *devname)
0daac978
MF
55{
56 struct list_head *entry;
57 struct mii_dev *dev;
58
59 if (!devname) {
60 printf("NULL device name!\n");
61 return NULL;
62 }
63
64 list_for_each(entry, &mii_devs) {
65 dev = list_entry(entry, struct mii_dev, link);
66 if (strcmp(dev->name, devname) == 0)
67 return dev;
68 }
69
0daac978
MF
70 return NULL;
71}
72
d9785c14
MB
73/*****************************************************************************
74 *
75 * Initialize global data. Need to be called before any other miiphy routine.
76 */
5700bb63 77void miiphy_init(void)
d9785c14 78{
16a53238 79 INIT_LIST_HEAD(&mii_devs);
298035df 80 current_mii = NULL;
d9785c14
MB
81}
82
5f184715
AF
83static int legacy_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg)
84{
85 unsigned short val;
86 int ret;
87 struct legacy_mii_dev *ldev = bus->priv;
88
89 ret = ldev->read(bus->name, addr, reg, &val);
90
91 return ret ? -1 : (int)val;
92}
93
94static int legacy_miiphy_write(struct mii_dev *bus, int addr, int devad,
95 int reg, u16 val)
96{
97 struct legacy_mii_dev *ldev = bus->priv;
98
99 return ldev->write(bus->name, addr, reg, val);
100}
101
63ff004c
MB
102/*****************************************************************************
103 *
104 * Register read and write MII access routines for the device <name>.
105 */
5700bb63 106void miiphy_register(const char *name,
16a53238 107 int (*read)(const char *devname, unsigned char addr,
298035df 108 unsigned char reg, unsigned short *value),
16a53238 109 int (*write)(const char *devname, unsigned char addr,
298035df 110 unsigned char reg, unsigned short value))
63ff004c 111{
63ff004c 112 struct mii_dev *new_dev;
5f184715 113 struct legacy_mii_dev *ldev;
07c07635
LW
114
115 BUG_ON(strlen(name) >= MDIO_NAME_LEN);
63ff004c 116
63ff004c 117 /* check if we have unique name */
5f184715 118 new_dev = miiphy_get_dev_by_name(name);
0daac978
MF
119 if (new_dev) {
120 printf("miiphy_register: non unique device name '%s'\n", name);
121 return;
63ff004c
MB
122 }
123
124 /* allocate memory */
5f184715
AF
125 new_dev = mdio_alloc();
126 ldev = malloc(sizeof(*ldev));
63ff004c 127
5f184715 128 if (new_dev == NULL || ldev == NULL) {
16a53238 129 printf("miiphy_register: cannot allocate memory for '%s'\n",
298035df 130 name);
63ff004c
MB
131 return;
132 }
63ff004c
MB
133
134 /* initalize mii_dev struct fields */
5f184715
AF
135 new_dev->read = legacy_miiphy_read;
136 new_dev->write = legacy_miiphy_write;
07c07635
LW
137 strncpy(new_dev->name, name, MDIO_NAME_LEN);
138 new_dev->name[MDIO_NAME_LEN - 1] = 0;
5f184715
AF
139 ldev->read = read;
140 ldev->write = write;
141 new_dev->priv = ldev;
63ff004c 142
16a53238 143 debug("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
5f184715 144 new_dev->name, ldev->read, ldev->write);
63ff004c
MB
145
146 /* add it to the list */
16a53238 147 list_add_tail(&new_dev->link, &mii_devs);
63ff004c
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148
149 if (!current_mii)
150 current_mii = new_dev;
151}
152
5f184715
AF
153struct mii_dev *mdio_alloc(void)
154{
155 struct mii_dev *bus;
156
157 bus = malloc(sizeof(*bus));
158 if (!bus)
159 return bus;
160
161 memset(bus, 0, sizeof(*bus));
162
163 /* initalize mii_dev struct fields */
164 INIT_LIST_HEAD(&bus->link);
165
166 return bus;
167}
168
169int mdio_register(struct mii_dev *bus)
170{
171 if (!bus || !bus->name || !bus->read || !bus->write)
172 return -1;
173
174 /* check if we have unique name */
175 if (miiphy_get_dev_by_name(bus->name)) {
176 printf("mdio_register: non unique device name '%s'\n",
177 bus->name);
178 return -1;
179 }
180
181 /* add it to the list */
182 list_add_tail(&bus->link, &mii_devs);
183
184 if (!current_mii)
185 current_mii = bus;
186
187 return 0;
188}
189
190void mdio_list_devices(void)
191{
192 struct list_head *entry;
193
194 list_for_each(entry, &mii_devs) {
195 int i;
196 struct mii_dev *bus = list_entry(entry, struct mii_dev, link);
197
198 printf("%s:\n", bus->name);
199
200 for (i = 0; i < PHY_MAX_ADDR; i++) {
201 struct phy_device *phydev = bus->phymap[i];
202
203 if (phydev) {
204 printf("%d - %s", i, phydev->drv->name);
205
206 if (phydev->dev)
207 printf(" <--> %s\n", phydev->dev->name);
208 else
209 printf("\n");
210 }
211 }
212 }
213}
214
5700bb63 215int miiphy_set_current_dev(const char *devname)
63ff004c 216{
63ff004c
MB
217 struct mii_dev *dev;
218
5f184715 219 dev = miiphy_get_dev_by_name(devname);
0daac978
MF
220 if (dev) {
221 current_mii = dev;
222 return 0;
63ff004c
MB
223 }
224
5f184715
AF
225 printf("No such device: %s\n", devname);
226
63ff004c
MB
227 return 1;
228}
229
5f184715
AF
230struct mii_dev *mdio_get_current_dev(void)
231{
232 return current_mii;
233}
234
235struct phy_device *mdio_phydev_for_ethname(const char *ethname)
236{
237 struct list_head *entry;
238 struct mii_dev *bus;
239
240 list_for_each(entry, &mii_devs) {
241 int i;
242 bus = list_entry(entry, struct mii_dev, link);
243
244 for (i = 0; i < PHY_MAX_ADDR; i++) {
245 if (!bus->phymap[i] || !bus->phymap[i]->dev)
246 continue;
247
248 if (strcmp(bus->phymap[i]->dev->name, ethname) == 0)
249 return bus->phymap[i];
250 }
251 }
252
253 printf("%s is not a known ethernet\n", ethname);
254 return NULL;
255}
256
5700bb63 257const char *miiphy_get_current_dev(void)
63ff004c
MB
258{
259 if (current_mii)
260 return current_mii->name;
261
262 return NULL;
263}
264
ede16ea3
MF
265static struct mii_dev *miiphy_get_active_dev(const char *devname)
266{
267 /* If the current mii is the one we want, return it */
268 if (current_mii)
269 if (strcmp(current_mii->name, devname) == 0)
270 return current_mii;
271
272 /* Otherwise, set the active one to the one we want */
273 if (miiphy_set_current_dev(devname))
274 return NULL;
275 else
276 return current_mii;
277}
278
63ff004c
MB
279/*****************************************************************************
280 *
281 * Read to variable <value> from the PHY attached to device <devname>,
282 * use PHY address <addr> and register <reg>.
283 *
284 * Returns:
285 * 0 on success
286 */
5700bb63 287int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
298035df 288 unsigned short *value)
63ff004c 289{
5f184715 290 struct mii_dev *bus;
d67d5d52 291 int ret;
63ff004c 292
5f184715 293 bus = miiphy_get_active_dev(devname);
d67d5d52 294 if (!bus)
5f184715 295 return 1;
63ff004c 296
d67d5d52
AG
297 ret = bus->read(bus, addr, MDIO_DEVAD_NONE, reg);
298 if (ret < 0)
299 return 1;
300
301 *value = (unsigned short)ret;
302 return 0;
63ff004c
MB
303}
304
305/*****************************************************************************
306 *
307 * Write <value> to the PHY attached to device <devname>,
308 * use PHY address <addr> and register <reg>.
309 *
310 * Returns:
311 * 0 on success
312 */
5700bb63 313int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
298035df 314 unsigned short value)
63ff004c 315{
5f184715 316 struct mii_dev *bus;
63ff004c 317
5f184715
AF
318 bus = miiphy_get_active_dev(devname);
319 if (bus)
320 return bus->write(bus, addr, MDIO_DEVAD_NONE, reg, value);
63ff004c 321
0daac978 322 return 1;
63ff004c
MB
323}
324
325/*****************************************************************************
326 *
327 * Print out list of registered MII capable devices.
328 */
16a53238 329void miiphy_listdev(void)
63ff004c
MB
330{
331 struct list_head *entry;
332 struct mii_dev *dev;
333
16a53238
AF
334 puts("MII devices: ");
335 list_for_each(entry, &mii_devs) {
336 dev = list_entry(entry, struct mii_dev, link);
337 printf("'%s' ", dev->name);
63ff004c 338 }
16a53238 339 puts("\n");
63ff004c
MB
340
341 if (current_mii)
16a53238 342 printf("Current device: '%s'\n", current_mii->name);
63ff004c
MB
343}
344
c609719b
WD
345/*****************************************************************************
346 *
347 * Read the OUI, manufacture's model number, and revision number.
348 *
349 * OUI: 22 bits (unsigned int)
350 * Model: 6 bits (unsigned char)
351 * Revision: 4 bits (unsigned char)
352 *
353 * Returns:
354 * 0 on success
355 */
5700bb63 356int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
c609719b
WD
357 unsigned char *model, unsigned char *rev)
358{
359 unsigned int reg = 0;
8bf3b005 360 unsigned short tmp;
c609719b 361
16a53238
AF
362 if (miiphy_read(devname, addr, MII_PHYSID2, &tmp) != 0) {
363 debug("PHY ID register 2 read failed\n");
364 return -1;
c609719b 365 }
8bf3b005 366 reg = tmp;
c609719b 367
16a53238 368 debug("MII_PHYSID2 @ 0x%x = 0x%04x\n", addr, reg);
26c7bab8 369
c609719b
WD
370 if (reg == 0xFFFF) {
371 /* No physical device present at this address */
16a53238 372 return -1;
c609719b
WD
373 }
374
16a53238
AF
375 if (miiphy_read(devname, addr, MII_PHYSID1, &tmp) != 0) {
376 debug("PHY ID register 1 read failed\n");
377 return -1;
c609719b 378 }
8bf3b005 379 reg |= tmp << 16;
16a53238 380 debug("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
26c7bab8 381
298035df
LJ
382 *oui = (reg >> 10);
383 *model = (unsigned char)((reg >> 4) & 0x0000003F);
384 *rev = (unsigned char)(reg & 0x0000000F);
16a53238 385 return 0;
c609719b
WD
386}
387
5f184715 388#ifndef CONFIG_PHYLIB
c609719b
WD
389/*****************************************************************************
390 *
391 * Reset the PHY.
392 * Returns:
393 * 0 on success
394 */
5700bb63 395int miiphy_reset(const char *devname, unsigned char addr)
c609719b
WD
396{
397 unsigned short reg;
ab5a0dcb 398 int timeout = 500;
c609719b 399
16a53238
AF
400 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
401 debug("PHY status read failed\n");
402 return -1;
f89920c3 403 }
16a53238
AF
404 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) {
405 debug("PHY reset failed\n");
406 return -1;
c609719b 407 }
5653fc33 408#ifdef CONFIG_PHY_RESET_DELAY
16a53238 409 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
5653fc33 410#endif
c609719b
WD
411 /*
412 * Poll the control register for the reset bit to go to 0 (it is
413 * auto-clearing). This should happen within 0.5 seconds per the
414 * IEEE spec.
415 */
c609719b 416 reg = 0x8000;
ab5a0dcb 417 while (((reg & 0x8000) != 0) && timeout--) {
8ef583a0 418 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) {
ab5a0dcb
SR
419 debug("PHY status read failed\n");
420 return -1;
c609719b 421 }
ab5a0dcb 422 udelay(1000);
c609719b
WD
423 }
424 if ((reg & 0x8000) == 0) {
16a53238 425 return 0;
c609719b 426 } else {
16a53238
AF
427 puts("PHY reset timed out\n");
428 return -1;
c609719b 429 }
16a53238 430 return 0;
c609719b 431}
5f184715 432#endif /* !PHYLIB */
c609719b 433
c609719b
WD
434/*****************************************************************************
435 *
71bc6e64 436 * Determine the ethernet speed (10/100/1000). Return 10 on error.
c609719b 437 */
5700bb63 438int miiphy_speed(const char *devname, unsigned char addr)
c609719b 439{
71bc6e64 440 u16 bmcr, anlpar;
c609719b 441
6fb6af6d 442#if defined(CONFIG_PHY_GIGE)
71bc6e64
LJ
443 u16 btsr;
444
445 /*
446 * Check for 1000BASE-X. If it is supported, then assume that the speed
447 * is 1000.
448 */
16a53238 449 if (miiphy_is_1000base_x(devname, addr))
71bc6e64 450 return _1000BASET;
16a53238 451
71bc6e64
LJ
452 /*
453 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
454 */
455 /* Check for 1000BASE-T. */
16a53238
AF
456 if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
457 printf("PHY 1000BT status");
71bc6e64
LJ
458 goto miiphy_read_failed;
459 }
460 if (btsr != 0xFFFF &&
16a53238 461 (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
71bc6e64 462 return _1000BASET;
6fb6af6d 463#endif /* CONFIG_PHY_GIGE */
855a496f 464
a56bd922 465 /* Check Basic Management Control Register first. */
16a53238
AF
466 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
467 printf("PHY speed");
71bc6e64 468 goto miiphy_read_failed;
c609719b 469 }
a56bd922 470 /* Check if auto-negotiation is on. */
8ef583a0 471 if (bmcr & BMCR_ANENABLE) {
a56bd922 472 /* Get auto-negotiation results. */
16a53238
AF
473 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
474 printf("PHY AN speed");
71bc6e64 475 goto miiphy_read_failed;
a56bd922 476 }
8ef583a0 477 return (anlpar & LPA_100) ? _100BASET : _10BASET;
a56bd922
WD
478 }
479 /* Get speed from basic control settings. */
8ef583a0 480 return (bmcr & BMCR_SPEED100) ? _100BASET : _10BASET;
a56bd922 481
5f841959 482miiphy_read_failed:
16a53238 483 printf(" read failed, assuming 10BASE-T\n");
71bc6e64 484 return _10BASET;
c609719b
WD
485}
486
c609719b
WD
487/*****************************************************************************
488 *
71bc6e64 489 * Determine full/half duplex. Return half on error.
c609719b 490 */
5700bb63 491int miiphy_duplex(const char *devname, unsigned char addr)
c609719b 492{
71bc6e64 493 u16 bmcr, anlpar;
c609719b 494
6fb6af6d 495#if defined(CONFIG_PHY_GIGE)
71bc6e64
LJ
496 u16 btsr;
497
498 /* Check for 1000BASE-X. */
16a53238 499 if (miiphy_is_1000base_x(devname, addr)) {
71bc6e64 500 /* 1000BASE-X */
16a53238
AF
501 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
502 printf("1000BASE-X PHY AN duplex");
71bc6e64
LJ
503 goto miiphy_read_failed;
504 }
505 }
506 /*
507 * No 1000BASE-X, so assume 1000BASE-T/100BASE-TX/10BASE-T register set.
508 */
509 /* Check for 1000BASE-T. */
16a53238
AF
510 if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) {
511 printf("PHY 1000BT status");
71bc6e64
LJ
512 goto miiphy_read_failed;
513 }
514 if (btsr != 0xFFFF) {
515 if (btsr & PHY_1000BTSR_1000FD) {
516 return FULL;
517 } else if (btsr & PHY_1000BTSR_1000HD) {
518 return HALF;
855a496f
WD
519 }
520 }
6fb6af6d 521#endif /* CONFIG_PHY_GIGE */
855a496f 522
a56bd922 523 /* Check Basic Management Control Register first. */
16a53238
AF
524 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
525 puts("PHY duplex");
71bc6e64 526 goto miiphy_read_failed;
c609719b 527 }
a56bd922 528 /* Check if auto-negotiation is on. */
8ef583a0 529 if (bmcr & BMCR_ANENABLE) {
a56bd922 530 /* Get auto-negotiation results. */
16a53238
AF
531 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) {
532 puts("PHY AN duplex");
71bc6e64 533 goto miiphy_read_failed;
a56bd922 534 }
8ef583a0 535 return (anlpar & (LPA_10FULL | LPA_100FULL)) ?
71bc6e64 536 FULL : HALF;
a56bd922
WD
537 }
538 /* Get speed from basic control settings. */
8ef583a0 539 return (bmcr & BMCR_FULLDPLX) ? FULL : HALF;
71bc6e64 540
5f841959 541miiphy_read_failed:
16a53238 542 printf(" read failed, assuming half duplex\n");
71bc6e64
LJ
543 return HALF;
544}
a56bd922 545
71bc6e64
LJ
546/*****************************************************************************
547 *
548 * Return 1 if PHY supports 1000BASE-X, 0 if PHY supports 10BASE-T/100BASE-TX/
549 * 1000BASE-T, or on error.
550 */
5700bb63 551int miiphy_is_1000base_x(const char *devname, unsigned char addr)
71bc6e64
LJ
552{
553#if defined(CONFIG_PHY_GIGE)
554 u16 exsr;
555
16a53238
AF
556 if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) {
557 printf("PHY extended status read failed, assuming no "
71bc6e64
LJ
558 "1000BASE-X\n");
559 return 0;
560 }
8ef583a0 561 return 0 != (exsr & (ESTATUS_1000XF | ESTATUS_1000XH));
71bc6e64
LJ
562#else
563 return 0;
564#endif
c609719b
WD
565}
566
6d0f6bcf 567#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
fc3e2165
WD
568/*****************************************************************************
569 *
570 * Determine link status
571 */
5700bb63 572int miiphy_link(const char *devname, unsigned char addr)
fc3e2165
WD
573{
574 unsigned short reg;
575
a3d991bd 576 /* dummy read; needed to latch some phys */
16a53238
AF
577 (void)miiphy_read(devname, addr, MII_BMSR, &reg);
578 if (miiphy_read(devname, addr, MII_BMSR, &reg)) {
579 puts("MII_BMSR read failed, assuming no link\n");
580 return 0;
fc3e2165
WD
581 }
582
583 /* Determine if a link is active */
8ef583a0 584 if ((reg & BMSR_LSTATUS) != 0) {
16a53238 585 return 1;
fc3e2165 586 } else {
16a53238 587 return 0;
fc3e2165
WD
588 }
589}
590#endif
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