[J-u-boot.git] / common / miiphyutil.c

/*
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, [email protected].
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * This provides a bit-banged interface to the ethernet MII management
 * channel.
 */

#include <common.h>
#include <miiphy.h>

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
#include <asm/types.h>
#include <linux/list.h>
#include <malloc.h>
#include <net.h>

/* local debug macro */
#define MII_DEBUG
#undef MII_DEBUG

#undef debug
#ifdef MII_DEBUG
#define debug(fmt,args...)	printf (fmt ,##args)
#else
#define debug(fmt,args...)
#endif /* MII_DEBUG */

struct mii_dev {
	struct list_head link;
	char *name;
	int (*read) (char *devname, unsigned char addr,
		     unsigned char reg, unsigned short *value);
	int (*write) (char *devname, unsigned char addr,
		      unsigned char reg, unsigned short value);
};

static struct list_head mii_devs;
static struct mii_dev *current_mii;

/*****************************************************************************
 *
 * Initialize global data. Need to be called before any other miiphy routine.
 */
void miiphy_init ()
{
	INIT_LIST_HEAD (&mii_devs);
	current_mii = NULL;
}

/*****************************************************************************
 *
 * Register read and write MII access routines for the device <name>.
 */
void miiphy_register (char *name,
		      int (*read) (char *devname, unsigned char addr,
				   unsigned char reg, unsigned short *value),
		      int (*write) (char *devname, unsigned char addr,
				    unsigned char reg, unsigned short value))
{
	struct list_head *entry;
	struct mii_dev *new_dev;
	struct mii_dev *miidev;
	unsigned int name_len;

	/* check if we have unique name */
	list_for_each (entry, &mii_devs) {
		miidev = list_entry (entry, struct mii_dev, link);
		if (strcmp (miidev->name, name) == 0) {
			printf ("miiphy_register: non unique device name "
				"'%s'\n", name);
			return;
		}
	}

	/* allocate memory */
	name_len = strlen (name);
	new_dev =
	    (struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);

	if (new_dev == NULL) {
		printf ("miiphy_register: cannot allocate memory for '%s'\n",
			name);
		return;
	}
	memset (new_dev, 0, sizeof (struct mii_dev) + name_len);

	/* initalize mii_dev struct fields */
	INIT_LIST_HEAD (&new_dev->link);
	new_dev->read = read;
	new_dev->write = write;
	new_dev->name = (char *)(new_dev + 1);
	strncpy (new_dev->name, name, name_len);
	new_dev->name[name_len] = '\0';

	debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
	       new_dev->name, new_dev->read, new_dev->write);

	/* add it to the list */
	list_add_tail (&new_dev->link, &mii_devs);

	if (!current_mii)
		current_mii = new_dev;
}

int miiphy_set_current_dev (char *devname)
{
	struct list_head *entry;
	struct mii_dev *dev;

	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);

		if (strcmp (devname, dev->name) == 0) {
			current_mii = dev;
			return 0;
		}
	}

	printf ("No such device: %s\n", devname);
	return 1;
}

char *miiphy_get_current_dev ()
{
	if (current_mii)
		return current_mii->name;

	return NULL;
}

/*****************************************************************************
 *
 * Read to variable <value> from the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * Returns:
 *   0 on success
 */
int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
		 unsigned short *value)
{
	struct list_head *entry;
	struct mii_dev *dev;
	int found_dev = 0;
	int read_ret = 0;

	if (!devname) {
		printf ("NULL device name!\n");
		return 1;
	}

	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);

		if (strcmp (devname, dev->name) == 0) {
			found_dev = 1;
			read_ret = dev->read (devname, addr, reg, value);
			break;
		}
	}

	if (found_dev == 0)
		printf ("No such device: %s\n", devname);

	return ((found_dev) ? read_ret : 1);
}

/*****************************************************************************
 *
 * Write <value> to the PHY attached to device <devname>,
 * use PHY address <addr> and register <reg>.
 *
 * Returns:
 *   0 on success
 */
int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
		  unsigned short value)
{
	struct list_head *entry;
	struct mii_dev *dev;
	int found_dev = 0;
	int write_ret = 0;

	if (!devname) {
		printf ("NULL device name!\n");
		return 1;
	}

	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);

		if (strcmp (devname, dev->name) == 0) {
			found_dev = 1;
			write_ret = dev->write (devname, addr, reg, value);
			break;
		}
	}

	if (found_dev == 0)
		printf ("No such device: %s\n", devname);

	return ((found_dev) ? write_ret : 1);
}

/*****************************************************************************
 *
 * Print out list of registered MII capable devices.
 */
void miiphy_listdev (void)
{
	struct list_head *entry;
	struct mii_dev *dev;

	puts ("MII devices: ");
	list_for_each (entry, &mii_devs) {
		dev = list_entry (entry, struct mii_dev, link);
		printf ("'%s' ", dev->name);
	}
	puts ("\n");

	if (current_mii)
		printf ("Current device: '%s'\n", current_mii->name);
}

/*****************************************************************************
 *
 * Read the OUI, manufacture's model number, and revision number.
 *
 * OUI:     22 bits (unsigned int)
 * Model:    6 bits (unsigned char)
 * Revision: 4 bits (unsigned char)
 *
 * Returns:
 *   0 on success
 */
int miiphy_info (char *devname, unsigned char addr, unsigned int *oui,
		 unsigned char *model, unsigned char *rev)
{
	unsigned int reg = 0;
	unsigned short tmp;

	if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
#ifdef DEBUG
		puts ("PHY ID register 2 read failed\n");
#endif
		return (-1);
	}
	reg = tmp;

#ifdef DEBUG
	printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
#endif
	if (reg == 0xFFFF) {
		/* No physical device present at this address */
		return (-1);
	}

	if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
#ifdef DEBUG
		puts ("PHY ID register 1 read failed\n");
#endif
		return (-1);
	}
	reg |= tmp << 16;
#ifdef DEBUG
	printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
#endif
	*oui = (reg >> 10);
	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	*rev = (unsigned char)(reg & 0x0000000F);
	return (0);
}

/*****************************************************************************
 *
 * Reset the PHY.
 * Returns:
 *   0 on success
 */
int miiphy_reset (char *devname, unsigned char addr)
{
	unsigned short reg;
	int loop_cnt;

	if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
#ifdef DEBUG
		printf ("PHY status read failed\n");
#endif
		return (-1);
	}
	if (miiphy_write (devname, addr, PHY_BMCR, reg | 0x8000) != 0) {
#ifdef DEBUG
		puts ("PHY reset failed\n");
#endif
		return (-1);
	}
#ifdef CONFIG_PHY_RESET_DELAY
	udelay (CONFIG_PHY_RESET_DELAY);	/* Intel LXT971A needs this */
#endif
	/*
	 * Poll the control register for the reset bit to go to 0 (it is
	 * auto-clearing).  This should happen within 0.5 seconds per the
	 * IEEE spec.
	 */
	loop_cnt = 0;
	reg = 0x8000;
	while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
		if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
#     ifdef DEBUG
			puts ("PHY status read failed\n");
#     endif
			return (-1);
		}
	}
	if ((reg & 0x8000) == 0) {
		return (0);
	} else {
		puts ("PHY reset timed out\n");
		return (-1);
	}
	return (0);
}

/*****************************************************************************
 *
 * Determine the ethernet speed (10/100).
 */
int miiphy_speed (char *devname, unsigned char addr)
{
	unsigned short reg;

#if defined(CONFIG_PHY_GIGE)
	if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
		printf ("PHY 1000BT Status read failed\n");
	} else {
		if (reg != 0xFFFF) {
			if ((reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))
			    != 0) {
				return (_1000BASET);
			}
		}
	}
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
		puts ("PHY speed read failed, assuming 10bT\n");
		return (_10BASET);
	}
	/* Check if auto-negotiation is on. */
	if ((reg & PHY_BMCR_AUTON) != 0) {
		/* Get auto-negotiation results. */
		if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
			puts ("PHY AN speed read failed, assuming 10bT\n");
			return (_10BASET);
		}
		if ((reg & PHY_ANLPAR_100) != 0) {
			return (_100BASET);
		} else {
			return (_10BASET);
		}
	}
	/* Get speed from basic control settings. */
	else if (reg & PHY_BMCR_100MB) {
		return (_100BASET);
	} else {
		return (_10BASET);
	}

}

/*****************************************************************************
 *
 * Determine full/half duplex.
 */
int miiphy_duplex (char *devname, unsigned char addr)
{
	unsigned short reg;

#if defined(CONFIG_PHY_GIGE)
	if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
		printf ("PHY 1000BT Status read failed\n");
	} else {
		if ((reg != 0xFFFF) &&
		    (reg & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD))) {
			if ((reg & PHY_1000BTSR_1000FD) != 0) {
				return (FULL);
			} else {
				return (HALF);
			}
		}
	}
#endif /* CONFIG_PHY_GIGE */

	/* Check Basic Management Control Register first. */
	if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
		puts ("PHY duplex read failed, assuming half duplex\n");
		return (HALF);
	}
	/* Check if auto-negotiation is on. */
	if ((reg & PHY_BMCR_AUTON) != 0) {
		/* Get auto-negotiation results. */
		if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
			puts ("PHY AN duplex read failed, assuming half duplex\n");
			return (HALF);
		}

		if ((reg & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD)) != 0) {
			return (FULL);
		} else {
			return (HALF);
		}
	}
	/* Get speed from basic control settings. */
	else if (reg & PHY_BMCR_DPLX) {
		return (FULL);
	} else {
		return (HALF);
	}

}

#ifdef CFG_FAULT_ECHO_LINK_DOWN
/*****************************************************************************
 *
 * Determine link status
 */
int miiphy_link (char *devname, unsigned char addr)
{
	unsigned short reg;

	/* dummy read; needed to latch some phys */
	(void)miiphy_read (devname, addr, PHY_BMSR, &reg);
	if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
		puts ("PHY_BMSR read failed, assuming no link\n");
		return (0);
	}

	/* Determine if a link is active */
	if ((reg & PHY_BMSR_LS) != 0) {
		return (1);
	} else {
		return (0);
	}
}
#endif
#endif /* CONFIG_MII */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Gerald Van Baren, Custom IDEAS, [email protected].
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* This provides a bit-banged interface to the ethernet MII management
	26	* channel.
	27	*/
	28
	29	#include <common.h>
	30	#include <miiphy.h>
	31
c3517f91	32	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
63ff004c MB	33	#include <asm/types.h>
	34	#include <linux/list.h>
	35	#include <malloc.h>
	36	#include <net.h>
	37
	38	/* local debug macro */
	39	#define MII_DEBUG
	40	#undef MII_DEBUG
	41
	42	#undef debug
	43	#ifdef MII_DEBUG
	44	#define debug(fmt,args...) printf (fmt ,##args)
	45	#else
	46	#define debug(fmt,args...)
	47	#endif /* MII_DEBUG */
	48
	49	struct mii_dev {
	50	struct list_head link;
	51	char *name;
298035df LJ	52	int (read) (char devname, unsigned char addr,
	53	unsigned char reg, unsigned short *value);
	54	int (write) (char devname, unsigned char addr,
	55	unsigned char reg, unsigned short value);
63ff004c MB	56	};
	57
	58	static struct list_head mii_devs;
	59	static struct mii_dev *current_mii;
	60
d9785c14 MB	61	/*****************************************************************************
	62	*
	63	* Initialize global data. Need to be called before any other miiphy routine.
	64	*/
298035df	65	void miiphy_init ()
d9785c14	66	{
298035df LJ	67	INIT_LIST_HEAD (&mii_devs);
298035df LJ	68	current_mii = NULL;
d9785c14 MB	69	}
d9785c14 MB	70
63ff004c MB	71	/*****************************************************************************
	72	*
	73	* Register read and write MII access routines for the device <name>.
	74	*/
298035df LJ	75	void miiphy_register (char *name,
	76	int (read) (char devname, unsigned char addr,
	77	unsigned char reg, unsigned short *value),
	78	int (write) (char devname, unsigned char addr,
	79	unsigned char reg, unsigned short value))
63ff004c MB	80	{
	81	struct list_head *entry;
	82	struct mii_dev *new_dev;
	83	struct mii_dev *miidev;
63ff004c MB	84	unsigned int name_len;
63ff004c MB	85
63ff004c	86	/* check if we have unique name */
298035df LJ	87	list_for_each (entry, &mii_devs) {
	88	miidev = list_entry (entry, struct mii_dev, link);
	89	if (strcmp (miidev->name, name) == 0) {
	90	printf ("miiphy_register: non unique device name "
	91	"'%s'\n", name);
63ff004c MB	92	return;
	93	}
	94	}
	95
	96	/* allocate memory */
298035df LJ	97	name_len = strlen (name);
	98	new_dev =
	99	(struct mii_dev *)malloc (sizeof (struct mii_dev) + name_len + 1);
63ff004c	100
298035df LJ	101	if (new_dev == NULL) {
	102	printf ("miiphy_register: cannot allocate memory for '%s'\n",
	103	name);
63ff004c MB	104	return;
63ff004c MB	105	}
298035df	106	memset (new_dev, 0, sizeof (struct mii_dev) + name_len);
63ff004c MB	107
63ff004c MB	108	/* initalize mii_dev struct fields */
298035df	109	INIT_LIST_HEAD (&new_dev->link);
63ff004c MB	110	new_dev->read = read;
	111	new_dev->write = write;
	112	new_dev->name = (char *)(new_dev + 1);
298035df	113	strncpy (new_dev->name, name, name_len);
63ff004c MB	114	new_dev->name[name_len] = '\0';
63ff004c MB	115
298035df LJ	116	debug ("miiphy_register: added '%s', read=0x%08lx, write=0x%08lx\n",
298035df LJ	117	new_dev->name, new_dev->read, new_dev->write);
63ff004c MB	118
63ff004c MB	119	/* add it to the list */
298035df	120	list_add_tail (&new_dev->link, &mii_devs);
63ff004c MB	121
	122	if (!current_mii)
	123	current_mii = new_dev;
	124	}
	125
298035df	126	int miiphy_set_current_dev (char *devname)
63ff004c MB	127	{
	128	struct list_head *entry;
	129	struct mii_dev *dev;
	130
298035df LJ	131	list_for_each (entry, &mii_devs) {
298035df LJ	132	dev = list_entry (entry, struct mii_dev, link);
63ff004c	133
298035df	134	if (strcmp (devname, dev->name) == 0) {
63ff004c MB	135	current_mii = dev;
	136	return 0;
	137	}
	138	}
	139
298035df	140	printf ("No such device: %s\n", devname);
63ff004c MB	141	return 1;
	142	}
	143
298035df	144	char *miiphy_get_current_dev ()
63ff004c MB	145	{
	146	if (current_mii)
	147	return current_mii->name;
	148
	149	return NULL;
	150	}
	151
	152	/*****************************************************************************
	153	*
	154	* Read to variable <value> from the PHY attached to device <devname>,
	155	* use PHY address <addr> and register <reg>.
	156	*
	157	* Returns:
	158	* 0 on success
	159	*/
298035df LJ	160	int miiphy_read (char *devname, unsigned char addr, unsigned char reg,
298035df LJ	161	unsigned short *value)
63ff004c MB	162	{
	163	struct list_head *entry;
	164	struct mii_dev *dev;
	165	int found_dev = 0;
	166	int read_ret = 0;
	167
	168	if (!devname) {
298035df	169	printf ("NULL device name!\n");
63ff004c MB	170	return 1;
	171	}
	172
298035df LJ	173	list_for_each (entry, &mii_devs) {
298035df LJ	174	dev = list_entry (entry, struct mii_dev, link);
63ff004c	175
298035df	176	if (strcmp (devname, dev->name) == 0) {
63ff004c	177	found_dev = 1;
298035df	178	read_ret = dev->read (devname, addr, reg, value);
63ff004c MB	179	break;
	180	}
	181	}
	182
	183	if (found_dev == 0)
298035df	184	printf ("No such device: %s\n", devname);
63ff004c MB	185
	186	return ((found_dev) ? read_ret : 1);
	187	}
	188
	189	/*****************************************************************************
	190	*
	191	* Write <value> to the PHY attached to device <devname>,
	192	* use PHY address <addr> and register <reg>.
	193	*
	194	* Returns:
	195	* 0 on success
	196	*/
298035df LJ	197	int miiphy_write (char *devname, unsigned char addr, unsigned char reg,
298035df LJ	198	unsigned short value)
63ff004c MB	199	{
	200	struct list_head *entry;
	201	struct mii_dev *dev;
	202	int found_dev = 0;
	203	int write_ret = 0;
	204
	205	if (!devname) {
298035df	206	printf ("NULL device name!\n");
63ff004c MB	207	return 1;
	208	}
	209
298035df LJ	210	list_for_each (entry, &mii_devs) {
298035df LJ	211	dev = list_entry (entry, struct mii_dev, link);
63ff004c	212
298035df	213	if (strcmp (devname, dev->name) == 0) {
63ff004c	214	found_dev = 1;
298035df	215	write_ret = dev->write (devname, addr, reg, value);
63ff004c MB	216	break;
	217	}
	218	}
	219
	220	if (found_dev == 0)
298035df	221	printf ("No such device: %s\n", devname);
63ff004c MB	222
	223	return ((found_dev) ? write_ret : 1);
	224	}
	225
	226	/*****************************************************************************
	227	*
	228	* Print out list of registered MII capable devices.
	229	*/
298035df	230	void miiphy_listdev (void)
63ff004c MB	231	{
	232	struct list_head *entry;
	233	struct mii_dev *dev;
	234
298035df LJ	235	puts ("MII devices: ");
	236	list_for_each (entry, &mii_devs) {
	237	dev = list_entry (entry, struct mii_dev, link);
	238	printf ("'%s' ", dev->name);
63ff004c	239	}
298035df	240	puts ("\n");
63ff004c MB	241
63ff004c MB	242	if (current_mii)
298035df	243	printf ("Current device: '%s'\n", current_mii->name);
63ff004c MB	244	}
63ff004c MB	245
c609719b WD	246	/*****************************************************************************
	247	*
	248	* Read the OUI, manufacture's model number, and revision number.
	249	*
	250	* OUI: 22 bits (unsigned int)
	251	* Model: 6 bits (unsigned char)
	252	* Revision: 4 bits (unsigned char)
	253	*
	254	* Returns:
	255	* 0 on success
	256	*/
298035df	257	int miiphy_info (char devname, unsigned char addr, unsigned int oui,
c609719b WD	258	unsigned char model, unsigned char rev)
	259	{
	260	unsigned int reg = 0;
8bf3b005	261	unsigned short tmp;
c609719b	262
63ff004c	263	if (miiphy_read (devname, addr, PHY_PHYIDR2, &tmp) != 0) {
c609719b	264	#ifdef DEBUG
4b9206ed	265	puts ("PHY ID register 2 read failed\n");
c609719b WD	266	#endif
	267	return (-1);
	268	}
8bf3b005	269	reg = tmp;
c609719b WD	270
	271	#ifdef DEBUG
	272	printf ("PHY_PHYIDR2 @ 0x%x = 0x%04x\n", addr, reg);
	273	#endif
	274	if (reg == 0xFFFF) {
	275	/* No physical device present at this address */
	276	return (-1);
	277	}
	278
63ff004c	279	if (miiphy_read (devname, addr, PHY_PHYIDR1, &tmp) != 0) {
c609719b	280	#ifdef DEBUG
4b9206ed	281	puts ("PHY ID register 1 read failed\n");
c609719b WD	282	#endif
	283	return (-1);
	284	}
8bf3b005	285	reg \|= tmp << 16;
c609719b WD	286	#ifdef DEBUG
	287	printf ("PHY_PHYIDR[1,2] @ 0x%x = 0x%08x\n", addr, reg);
	288	#endif
298035df LJ	289	*oui = (reg >> 10);
	290	*model = (unsigned char)((reg >> 4) & 0x0000003F);
	291	*rev = (unsigned char)(reg & 0x0000000F);
c609719b WD	292	return (0);
	293	}
	294
c609719b WD	295	/*****************************************************************************
	296	*
	297	* Reset the PHY.
	298	* Returns:
	299	* 0 on success
	300	*/
63ff004c	301	int miiphy_reset (char *devname, unsigned char addr)
c609719b WD	302	{
	303	unsigned short reg;
	304	int loop_cnt;
	305
63ff004c	306	if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
f89920c3 WD	307	#ifdef DEBUG
	308	printf ("PHY status read failed\n");
	309	#endif
	310	return (-1);
	311	}
63ff004c	312	if (miiphy_write (devname, addr, PHY_BMCR, reg \| 0x8000) != 0) {
c609719b	313	#ifdef DEBUG
4b9206ed	314	puts ("PHY reset failed\n");
c609719b WD	315	#endif
	316	return (-1);
	317	}
5653fc33 WD	318	#ifdef CONFIG_PHY_RESET_DELAY
	319	udelay (CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
	320	#endif
c609719b WD	321	/*
	322	* Poll the control register for the reset bit to go to 0 (it is
	323	* auto-clearing). This should happen within 0.5 seconds per the
	324	* IEEE spec.
	325	*/
	326	loop_cnt = 0;
	327	reg = 0x8000;
	328	while (((reg & 0x8000) != 0) && (loop_cnt++ < 1000000)) {
63ff004c	329	if (miiphy_read (devname, addr, PHY_BMCR, &reg) != 0) {
c609719b	330	# ifdef DEBUG
4b9206ed	331	puts ("PHY status read failed\n");
c609719b WD	332	# endif
	333	return (-1);
	334	}
	335	}
	336	if ((reg & 0x8000) == 0) {
	337	return (0);
	338	} else {
4b9206ed	339	puts ("PHY reset timed out\n");
c609719b WD	340	return (-1);
	341	}
	342	return (0);
	343	}
	344
c609719b WD	345	/*****************************************************************************
	346	*
	347	* Determine the ethernet speed (10/100).
	348	*/
63ff004c	349	int miiphy_speed (char *devname, unsigned char addr)
c609719b WD	350	{
	351	unsigned short reg;
	352
6fb6af6d	353	#if defined(CONFIG_PHY_GIGE)
63ff004c	354	if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
855a496f WD	355	printf ("PHY 1000BT Status read failed\n");
	356	} else {
	357	if (reg != 0xFFFF) {
298035df LJ	358	if ((reg & (PHY_1000BTSR_1000FD \| PHY_1000BTSR_1000HD))
298035df LJ	359	!= 0) {
855a496f WD	360	return (_1000BASET);
	361	}
	362	}
	363	}
6fb6af6d	364	#endif /* CONFIG_PHY_GIGE */
855a496f	365
a56bd922	366	/* Check Basic Management Control Register first. */
63ff004c	367	if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
a56bd922	368	puts ("PHY speed read failed, assuming 10bT\n");
c609719b WD	369	return (_10BASET);
c609719b WD	370	}
a56bd922 WD	371	/* Check if auto-negotiation is on. */
	372	if ((reg & PHY_BMCR_AUTON) != 0) {
	373	/* Get auto-negotiation results. */
63ff004c	374	if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
a56bd922 WD	375	puts ("PHY AN speed read failed, assuming 10bT\n");
	376	return (_10BASET);
	377	}
	378	if ((reg & PHY_ANLPAR_100) != 0) {
	379	return (_100BASET);
	380	} else {
	381	return (_10BASET);
	382	}
	383	}
	384	/* Get speed from basic control settings. */
	385	else if (reg & PHY_BMCR_100MB) {
c609719b WD	386	return (_100BASET);
	387	} else {
	388	return (_10BASET);
	389	}
a56bd922	390
c609719b WD	391	}
c609719b WD	392
c609719b WD	393	/*****************************************************************************
	394	*
	395	* Determine full/half duplex.
	396	*/
63ff004c	397	int miiphy_duplex (char *devname, unsigned char addr)
c609719b WD	398	{
	399	unsigned short reg;
	400
6fb6af6d	401	#if defined(CONFIG_PHY_GIGE)
63ff004c	402	if (miiphy_read (devname, addr, PHY_1000BTSR, &reg)) {
855a496f WD	403	printf ("PHY 1000BT Status read failed\n");
855a496f WD	404	} else {
298035df LJ	405	if ((reg != 0xFFFF) &&
	406	(reg & (PHY_1000BTSR_1000FD \| PHY_1000BTSR_1000HD))) {
	407	if ((reg & PHY_1000BTSR_1000FD) != 0) {
855a496f WD	408	return (FULL);
	409	} else {
	410	return (HALF);
	411	}
	412	}
	413	}
6fb6af6d	414	#endif /* CONFIG_PHY_GIGE */
855a496f	415
a56bd922	416	/* Check Basic Management Control Register first. */
63ff004c	417	if (miiphy_read (devname, addr, PHY_BMCR, &reg)) {
4b9206ed	418	puts ("PHY duplex read failed, assuming half duplex\n");
c609719b WD	419	return (HALF);
c609719b WD	420	}
a56bd922 WD	421	/* Check if auto-negotiation is on. */
	422	if ((reg & PHY_BMCR_AUTON) != 0) {
	423	/* Get auto-negotiation results. */
63ff004c	424	if (miiphy_read (devname, addr, PHY_ANLPAR, &reg)) {
a56bd922 WD	425	puts ("PHY AN duplex read failed, assuming half duplex\n");
	426	return (HALF);
	427	}
c609719b	428
a56bd922 WD	429	if ((reg & (PHY_ANLPAR_10FD \| PHY_ANLPAR_TXFD)) != 0) {
	430	return (FULL);
	431	} else {
	432	return (HALF);
	433	}
	434	}
	435	/* Get speed from basic control settings. */
	436	else if (reg & PHY_BMCR_DPLX) {
c609719b WD	437	return (FULL);
	438	} else {
	439	return (HALF);
	440	}
a56bd922	441
c609719b WD	442	}
c609719b WD	443
fc3e2165 WD	444	#ifdef CFG_FAULT_ECHO_LINK_DOWN
	445	/*****************************************************************************
	446	*
	447	* Determine link status
	448	*/
63ff004c	449	int miiphy_link (char *devname, unsigned char addr)
fc3e2165 WD	450	{
	451	unsigned short reg;
	452
a3d991bd	453	/* dummy read; needed to latch some phys */
298035df	454	(void)miiphy_read (devname, addr, PHY_BMSR, &reg);
63ff004c	455	if (miiphy_read (devname, addr, PHY_BMSR, &reg)) {
4b9206ed	456	puts ("PHY_BMSR read failed, assuming no link\n");
fc3e2165 WD	457	return (0);
	458	}
	459
	460	/* Determine if a link is active */
	461	if ((reg & PHY_BMSR_LS) != 0) {
	462	return (1);
	463	} else {
	464	return (0);
	465	}
	466	}
	467	#endif
c3517f91	468	#endif /* CONFIG_MII */