[J-u-boot.git] / drivers / misc / imx8ulp / imx8ulp_mu.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright 2020 NXP
 */

#include <common.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/lists.h>
#include <dm/root.h>
#include <dm/device-internal.h>
#include <asm/arch/s400_api.h>
#include <linux/iopoll.h>
#include <misc.h>

DECLARE_GLOBAL_DATA_PTR;

struct mu_type {
	u32 ver;
	u32 par;
	u32 cr;
	u32 sr;
	u32 reserved0[68];
	u32 tcr;
	u32 tsr;
	u32 rcr;
	u32 rsr;
	u32 reserved1[52];
	u32 tr[16];
	u32 reserved2[16];
	u32 rr[16];
	u32 reserved4[14];
	u32 mu_attr;
};

struct imx8ulp_mu {
	struct mu_type *base;
};

#define MU_SR_TE0_MASK		BIT(0)
#define MU_SR_RF0_MASK		BIT(0)
#define MU_TR_COUNT		4
#define MU_RR_COUNT		4

static inline void mu_hal_init(struct mu_type *base)
{
	writel(0, &base->tcr);
	writel(0, &base->rcr);
}

static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
{
	u32 mask = MU_SR_TE0_MASK << reg_index;
	u32 val;
	int ret;

	assert(reg_index < MU_TR_COUNT);

	debug("sendmsg sr 0x%x\n", readl(&base->sr));

	/* Wait TX register to be empty. */
	ret = readl_poll_timeout(&base->tsr, val, val & mask, 10000);
	if (ret < 0) {
		debug("%s timeout\n", __func__);
		return -ETIMEDOUT;
	}

	debug("tr[%d] 0x%x\n", reg_index, msg);

	writel(msg, &base->tr[reg_index]);

	return 0;
}

static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg)
{
	u32 mask = MU_SR_RF0_MASK << reg_index;
	u32 val;
	int ret;

	assert(reg_index < MU_TR_COUNT);

	debug("receivemsg sr 0x%x\n", readl(&base->sr));

	/* Wait RX register to be full. */
	ret = readl_poll_timeout(&base->rsr, val, val & mask, 10000);
	if (ret < 0) {
		debug("%s timeout\n", __func__);
		return -ETIMEDOUT;
	}

	*msg = readl(&base->rr[reg_index]);

	debug("rr[%d] 0x%x\n", reg_index, *msg);

	return 0;
}

static int imx8ulp_mu_read(struct mu_type *base, void *data)
{
	struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
	int ret;
	u8 count = 0;

	if (!msg)
		return -EINVAL;

	/* Read first word */
	ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
	if (ret)
		return ret;
	count++;

	/* Check size */
	if (msg->size > S400_MAX_MSG) {
		*((u32 *)msg) = 0;
		return -EINVAL;
	}

	/* Read remaining words */
	while (count < msg->size) {
		ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
					&msg->data[count - 1]);
		if (ret)
			return ret;
		count++;
	}

	return 0;
}

static int imx8ulp_mu_write(struct mu_type *base, void *data)
{
	struct imx8ulp_s400_msg *msg = (struct imx8ulp_s400_msg *)data;
	int ret;
	u8 count = 0;

	if (!msg)
		return -EINVAL;

	/* Check size */
	if (msg->size > S400_MAX_MSG)
		return -EINVAL;

	/* Write first word */
	ret = mu_hal_sendmsg(base, 0, *((u32 *)msg));
	if (ret)
		return ret;
	count++;

	/* Write remaining words */
	while (count < msg->size) {
		ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
				     msg->data[count - 1]);
		if (ret)
			return ret;
		count++;
	}

	return 0;
}

/*
 * Note the function prototype use msgid as the 2nd parameter, here
 * we take it as no_resp.
 */
static int imx8ulp_mu_call(struct udevice *dev, int no_resp, void *tx_msg,
			   int tx_size, void *rx_msg, int rx_size)
{
	struct imx8ulp_mu *priv = dev_get_priv(dev);
	u32 result;
	int ret;

	/* Expect tx_msg, rx_msg are the same value */
	if (rx_msg && tx_msg != rx_msg)
		printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);

	ret = imx8ulp_mu_write(priv->base, tx_msg);
	if (ret)
		return ret;
	if (!no_resp) {
		ret = imx8ulp_mu_read(priv->base, rx_msg);
		if (ret)
			return ret;
	}

	result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0];
	if ((result & 0xff) == 0)
		return 0;

	return -EIO;
}

static int imx8ulp_mu_probe(struct udevice *dev)
{
	struct imx8ulp_mu *priv = dev_get_priv(dev);
	fdt_addr_t addr;

	debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->base = (struct mu_type *)addr;

	debug("mu base 0x%lx\n", (ulong)priv->base);

	/* U-Boot not enable interrupts, so need to enable RX interrupts */
	mu_hal_init(priv->base);

	gd->arch.s400_dev = dev;

	return 0;
}

static int imx8ulp_mu_remove(struct udevice *dev)
{
	return 0;
}

static int imx8ulp_mu_bind(struct udevice *dev)
{
	debug("%s(dev=%p)\n", __func__, dev);

	return 0;
}

static struct misc_ops imx8ulp_mu_ops = {
	.call = imx8ulp_mu_call,
};

static const struct udevice_id imx8ulp_mu_ids[] = {
	{ .compatible = "fsl,imx8ulp-mu" },
	{ }
};

U_BOOT_DRIVER(imx8ulp_mu) = {
	.name		= "imx8ulp_mu",
	.id		= UCLASS_MISC,
	.of_match	= imx8ulp_mu_ids,
	.probe		= imx8ulp_mu_probe,
	.bind		= imx8ulp_mu_bind,
	.remove		= imx8ulp_mu_remove,
	.ops		= &imx8ulp_mu_ops,
	.priv_auto	= sizeof(struct imx8ulp_mu),
};
Commit	Line	Data
0c00d03a YL	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright 2020 NXP
	4	*/
	5
	6	#include <common.h>
	7	#include <asm/io.h>
	8	#include <dm.h>
	9	#include <dm/lists.h>
	10	#include <dm/root.h>
	11	#include <dm/device-internal.h>
	12	#include <asm/arch/s400_api.h>
	13	#include <linux/iopoll.h>
	14	#include <misc.h>
	15
	16	DECLARE_GLOBAL_DATA_PTR;
	17
	18	struct mu_type {
	19	u32 ver;
	20	u32 par;
	21	u32 cr;
	22	u32 sr;
	23	u32 reserved0[68];
	24	u32 tcr;
	25	u32 tsr;
	26	u32 rcr;
	27	u32 rsr;
	28	u32 reserved1[52];
	29	u32 tr[16];
	30	u32 reserved2[16];
	31	u32 rr[16];
	32	u32 reserved4[14];
	33	u32 mu_attr;
	34	};
	35
	36	struct imx8ulp_mu {
	37	struct mu_type *base;
	38	};
	39
	40	#define MU_SR_TE0_MASK BIT(0)
	41	#define MU_SR_RF0_MASK BIT(0)
	42	#define MU_TR_COUNT 4
	43	#define MU_RR_COUNT 4
	44
	45	static inline void mu_hal_init(struct mu_type *base)
	46	{
	47	writel(0, &base->tcr);
	48	writel(0, &base->rcr);
	49	}
	50
	51	static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg)
	52	{
	53	u32 mask = MU_SR_TE0_MASK << reg_index;
	54	u32 val;
	55	int ret;
	56
	57	assert(reg_index < MU_TR_COUNT);
	58
	59	debug("sendmsg sr 0x%x\n", readl(&base->sr));
	60
	61	/* Wait TX register to be empty. */
	62	ret = readl_poll_timeout(&base->tsr, val, val & mask, 10000);
	63	if (ret < 0) {
	64	debug("%s timeout\n", __func__);
65	return -ETIMEDOUT;
66	}
67
68	debug("tr[%d] 0x%x\n", reg_index, msg);
69
70	writel(msg, &base->tr[reg_index]);
71
72	return 0;
73	}
74
75	static int mu_hal_receivemsg(struct mu_type base, u32 reg_index, u32 msg)
76	{
77	u32 mask = MU_SR_RF0_MASK << reg_index;
78	u32 val;
79	int ret;
80
81	assert(reg_index < MU_TR_COUNT);
82
83	debug("receivemsg sr 0x%x\n", readl(&base->sr));
84
85	/* Wait RX register to be full. */
86	ret = readl_poll_timeout(&base->rsr, val, val & mask, 10000);
87	if (ret < 0) {
88	debug("%s timeout\n", __func__);
89	return -ETIMEDOUT;
90	}
91
92	*msg = readl(&base->rr[reg_index]);
93
94	debug("rr[%d] 0x%x\n", reg_index, *msg);
95
96	return 0;
97	}
98
99	static int imx8ulp_mu_read(struct mu_type base, void data)
100	{
101	struct imx8ulp_s400_msg msg = (struct imx8ulp_s400_msg )data;
102	int ret;
103	u8 count = 0;
104
105	if (!msg)
106	return -EINVAL;
107
108	/* Read first word */
109	ret = mu_hal_receivemsg(base, 0, (u32 *)msg);
110	if (ret)
111	return ret;
112	count++;
113
114	/* Check size */
115	if (msg->size > S400_MAX_MSG) {
116	((u32 )msg) = 0;
117	return -EINVAL;
118	}
119
120	/* Read remaining words */
121	while (count < msg->size) {
122	ret = mu_hal_receivemsg(base, count % MU_RR_COUNT,
123	&msg->data[count - 1]);
124	if (ret)
125	return ret;
126	count++;
127	}
128
129	return 0;
130	}
131
132	static int imx8ulp_mu_write(struct mu_type base, void data)
133	{
134	struct imx8ulp_s400_msg msg = (struct imx8ulp_s400_msg )data;
135	int ret;
136	u8 count = 0;
137
138	if (!msg)
139	return -EINVAL;
140
141	/* Check size */
142	if (msg->size > S400_MAX_MSG)
143	return -EINVAL;
144
145	/* Write first word */
146	ret = mu_hal_sendmsg(base, 0, ((u32 )msg));
147	if (ret)
148	return ret;
149	count++;
150
151	/* Write remaining words */
152	while (count < msg->size) {
153	ret = mu_hal_sendmsg(base, count % MU_TR_COUNT,
154	msg->data[count - 1]);
155	if (ret)
156	return ret;
157	count++;
158	}
159
160	return 0;
161	}
162
163	/*
164	* Note the function prototype use msgid as the 2nd parameter, here
165	* we take it as no_resp.
166	*/
167	static int imx8ulp_mu_call(struct udevice dev, int no_resp, void tx_msg,
168	int tx_size, void *rx_msg, int rx_size)
169	{
170	struct imx8ulp_mu *priv = dev_get_priv(dev);
171	u32 result;
172	int ret;
173
174	/* Expect tx_msg, rx_msg are the same value */
175	if (rx_msg && tx_msg != rx_msg)
176	printf("tx_msg %p, rx_msg %p\n", tx_msg, rx_msg);
177
178	ret = imx8ulp_mu_write(priv->base, tx_msg);
179	if (ret)
180	return ret;
181	if (!no_resp) {
182	ret = imx8ulp_mu_read(priv->base, rx_msg);
183	if (ret)
184	return ret;
185	}
186
187	result = ((struct imx8ulp_s400_msg *)rx_msg)->data[0];
188	if ((result & 0xff) == 0)
189	return 0;
190
191	return -EIO;
192	}
193
194	static int imx8ulp_mu_probe(struct udevice *dev)
195	{
196	struct imx8ulp_mu *priv = dev_get_priv(dev);
197	fdt_addr_t addr;
198
199	debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv);
200
201	addr = devfdt_get_addr(dev);
202	if (addr == FDT_ADDR_T_NONE)
203	return -EINVAL;
204
205	priv->base = (struct mu_type *)addr;
206
207	debug("mu base 0x%lx\n", (ulong)priv->base);
208
209	/* U-Boot not enable interrupts, so need to enable RX interrupts */
210	mu_hal_init(priv->base);
211
212	gd->arch.s400_dev = dev;
213
214	return 0;
215	}
216
217	static int imx8ulp_mu_remove(struct udevice *dev)
218	{
219	return 0;
220	}
221
222	static int imx8ulp_mu_bind(struct udevice *dev)
223	{
224	debug("%s(dev=%p)\n", __func__, dev);
225
226	return 0;
227	}
228
229	static struct misc_ops imx8ulp_mu_ops = {
230	.call = imx8ulp_mu_call,
231	};
232
233	static const struct udevice_id imx8ulp_mu_ids[] = {
234	{ .compatible = "fsl,imx8ulp-mu" },
235	{ }
236	};
237
238	U_BOOT_DRIVER(imx8ulp_mu) = {
239	.name = "imx8ulp_mu",
240	.id = UCLASS_MISC,
241	.of_match = imx8ulp_mu_ids,
242	.probe = imx8ulp_mu_probe,
243	.bind = imx8ulp_mu_bind,
244	.remove = imx8ulp_mu_remove,
245	.ops = &imx8ulp_mu_ops,
246	.priv_auto = sizeof(struct imx8ulp_mu),
247	};