[J-u-boot.git] / drivers / net / fec_mxc.h

/*
 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <[email protected]>
 * (C) Copyright 2008 Armadeus Systems, nc
 * (C) Copyright 2008 Eric Jarrige <[email protected]>
 * (C) Copyright 2007 Pengutronix, Sascha Hauer <[email protected]>
 * (C) Copyright 2007 Pengutronix, Juergen Beisert <[email protected]>
 *
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, [email protected].
 *
 * This file is based on mpc4200fec.h
 * (C) Copyright Motorola, Inc., 2000
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */


#ifndef __FEC_MXC_H
#define __FEC_MXC_H

/**
 * Layout description of the FEC
 */
struct ethernet_regs {

/* [10:2]addr = 00 */

/*  Control and status Registers (offset 000-1FF) */

	uint32_t res0[1];		/* MBAR_ETH + 0x000 */
	uint32_t ievent;		/* MBAR_ETH + 0x004 */
	uint32_t imask;			/* MBAR_ETH + 0x008 */

	uint32_t res1[1];		/* MBAR_ETH + 0x00C */
	uint32_t r_des_active;		/* MBAR_ETH + 0x010 */
	uint32_t x_des_active;		/* MBAR_ETH + 0x014 */
	uint32_t res2[3];		/* MBAR_ETH + 0x018-20 */
	uint32_t ecntrl;		/* MBAR_ETH + 0x024 */

	uint32_t res3[6];		/* MBAR_ETH + 0x028-03C */
	uint32_t mii_data;		/* MBAR_ETH + 0x040 */
	uint32_t mii_speed;		/* MBAR_ETH + 0x044 */
	uint32_t res4[7];		/* MBAR_ETH + 0x048-60 */
	uint32_t mib_control;		/* MBAR_ETH + 0x064 */

	uint32_t res5[7];		/* MBAR_ETH + 0x068-80 */
	uint32_t r_cntrl;		/* MBAR_ETH + 0x084 */
	uint32_t res6[15];		/* MBAR_ETH + 0x088-C0 */
	uint32_t x_cntrl;		/* MBAR_ETH + 0x0C4 */
	uint32_t res7[7];		/* MBAR_ETH + 0x0C8-E0 */
	uint32_t paddr1;		/* MBAR_ETH + 0x0E4 */
	uint32_t paddr2;		/* MBAR_ETH + 0x0E8 */
	uint32_t op_pause;		/* MBAR_ETH + 0x0EC */

	uint32_t res8[10];		/* MBAR_ETH + 0x0F0-114 */
	uint32_t iaddr1;		/* MBAR_ETH + 0x118 */
	uint32_t iaddr2;		/* MBAR_ETH + 0x11C */
	uint32_t gaddr1;		/* MBAR_ETH + 0x120 */
	uint32_t gaddr2;		/* MBAR_ETH + 0x124 */
	uint32_t res9[7];		/* MBAR_ETH + 0x128-140 */

	uint32_t x_wmrk;		/* MBAR_ETH + 0x144 */
	uint32_t res10[1];		/* MBAR_ETH + 0x148 */
	uint32_t r_bound;		/* MBAR_ETH + 0x14C */
	uint32_t r_fstart;		/* MBAR_ETH + 0x150 */
	uint32_t res11[11];		/* MBAR_ETH + 0x154-17C */
	uint32_t erdsr;			/* MBAR_ETH + 0x180 */
	uint32_t etdsr;			/* MBAR_ETH + 0x184 */
	uint32_t emrbr;			/* MBAR_ETH + 0x188 */
	uint32_t res12[29];		/* MBAR_ETH + 0x18C-1FC */

/*  MIB COUNTERS (Offset 200-2FF) */

	uint32_t rmon_t_drop;		/* MBAR_ETH + 0x200 */
	uint32_t rmon_t_packets;	/* MBAR_ETH + 0x204 */
	uint32_t rmon_t_bc_pkt;		/* MBAR_ETH + 0x208 */
	uint32_t rmon_t_mc_pkt;		/* MBAR_ETH + 0x20C */
	uint32_t rmon_t_crc_align;	/* MBAR_ETH + 0x210 */
	uint32_t rmon_t_undersize;	/* MBAR_ETH + 0x214 */
	uint32_t rmon_t_oversize;	/* MBAR_ETH + 0x218 */
	uint32_t rmon_t_frag;		/* MBAR_ETH + 0x21C */
	uint32_t rmon_t_jab;		/* MBAR_ETH + 0x220 */
	uint32_t rmon_t_col;		/* MBAR_ETH + 0x224 */
	uint32_t rmon_t_p64;		/* MBAR_ETH + 0x228 */
	uint32_t rmon_t_p65to127;	/* MBAR_ETH + 0x22C */
	uint32_t rmon_t_p128to255;	/* MBAR_ETH + 0x230 */
	uint32_t rmon_t_p256to511;	/* MBAR_ETH + 0x234 */
	uint32_t rmon_t_p512to1023;	/* MBAR_ETH + 0x238 */
	uint32_t rmon_t_p1024to2047;	/* MBAR_ETH + 0x23C */
	uint32_t rmon_t_p_gte2048;	/* MBAR_ETH + 0x240 */
	uint32_t rmon_t_octets;		/* MBAR_ETH + 0x244 */
	uint32_t ieee_t_drop;		/* MBAR_ETH + 0x248 */
	uint32_t ieee_t_frame_ok;	/* MBAR_ETH + 0x24C */
	uint32_t ieee_t_1col;		/* MBAR_ETH + 0x250 */
	uint32_t ieee_t_mcol;		/* MBAR_ETH + 0x254 */
	uint32_t ieee_t_def;		/* MBAR_ETH + 0x258 */
	uint32_t ieee_t_lcol;		/* MBAR_ETH + 0x25C */
	uint32_t ieee_t_excol;		/* MBAR_ETH + 0x260 */
	uint32_t ieee_t_macerr;		/* MBAR_ETH + 0x264 */
	uint32_t ieee_t_cserr;		/* MBAR_ETH + 0x268 */
	uint32_t ieee_t_sqe;		/* MBAR_ETH + 0x26C */
	uint32_t t_fdxfc;		/* MBAR_ETH + 0x270 */
	uint32_t ieee_t_octets_ok;	/* MBAR_ETH + 0x274 */

	uint32_t res13[2];		/* MBAR_ETH + 0x278-27C */
	uint32_t rmon_r_drop;		/* MBAR_ETH + 0x280 */
	uint32_t rmon_r_packets;	/* MBAR_ETH + 0x284 */
	uint32_t rmon_r_bc_pkt;		/* MBAR_ETH + 0x288 */
	uint32_t rmon_r_mc_pkt;		/* MBAR_ETH + 0x28C */
	uint32_t rmon_r_crc_align;	/* MBAR_ETH + 0x290 */
	uint32_t rmon_r_undersize;	/* MBAR_ETH + 0x294 */
	uint32_t rmon_r_oversize;	/* MBAR_ETH + 0x298 */
	uint32_t rmon_r_frag;		/* MBAR_ETH + 0x29C */
	uint32_t rmon_r_jab;		/* MBAR_ETH + 0x2A0 */

	uint32_t rmon_r_resvd_0;	/* MBAR_ETH + 0x2A4 */

	uint32_t rmon_r_p64;		/* MBAR_ETH + 0x2A8 */
	uint32_t rmon_r_p65to127;	/* MBAR_ETH + 0x2AC */
	uint32_t rmon_r_p128to255;	/* MBAR_ETH + 0x2B0 */
	uint32_t rmon_r_p256to511;	/* MBAR_ETH + 0x2B4 */
	uint32_t rmon_r_p512to1023;	/* MBAR_ETH + 0x2B8 */
	uint32_t rmon_r_p1024to2047;	/* MBAR_ETH + 0x2BC */
	uint32_t rmon_r_p_gte2048;	/* MBAR_ETH + 0x2C0 */
	uint32_t rmon_r_octets;		/* MBAR_ETH + 0x2C4 */
	uint32_t ieee_r_drop;		/* MBAR_ETH + 0x2C8 */
	uint32_t ieee_r_frame_ok;	/* MBAR_ETH + 0x2CC */
	uint32_t ieee_r_crc;		/* MBAR_ETH + 0x2D0 */
	uint32_t ieee_r_align;		/* MBAR_ETH + 0x2D4 */
	uint32_t r_macerr;		/* MBAR_ETH + 0x2D8 */
	uint32_t r_fdxfc;		/* MBAR_ETH + 0x2DC */
	uint32_t ieee_r_octets_ok;	/* MBAR_ETH + 0x2E0 */

	uint32_t res14[6];		/* MBAR_ETH + 0x2E4-2FC */

	uint32_t res15[64];		/* MBAR_ETH + 0x300-3FF */
};

#define FEC_IEVENT_HBERR		0x80000000
#define FEC_IEVENT_BABR			0x40000000
#define FEC_IEVENT_BABT			0x20000000
#define FEC_IEVENT_GRA			0x10000000
#define FEC_IEVENT_TXF			0x08000000
#define FEC_IEVENT_TXB			0x04000000
#define FEC_IEVENT_RXF			0x02000000
#define FEC_IEVENT_RXB			0x01000000
#define FEC_IEVENT_MII			0x00800000
#define FEC_IEVENT_EBERR		0x00400000
#define FEC_IEVENT_LC			0x00200000
#define FEC_IEVENT_RL			0x00100000
#define FEC_IEVENT_UN			0x00080000

#define FEC_IMASK_HBERR			0x80000000
#define FEC_IMASK_BABR			0x40000000
#define FEC_IMASKT_BABT			0x20000000
#define FEC_IMASK_GRA			0x10000000
#define FEC_IMASKT_TXF			0x08000000
#define FEC_IMASK_TXB			0x04000000
#define FEC_IMASKT_RXF			0x02000000
#define FEC_IMASK_RXB			0x01000000
#define FEC_IMASK_MII			0x00800000
#define FEC_IMASK_EBERR			0x00400000
#define FEC_IMASK_LC			0x00200000
#define FEC_IMASKT_RL			0x00100000
#define FEC_IMASK_UN			0x00080000


#define FEC_RCNTRL_MAX_FL_SHIFT		16
#define FEC_RCNTRL_LOOP			0x00000001
#define FEC_RCNTRL_DRT			0x00000002
#define FEC_RCNTRL_MII_MODE		0x00000004
#define FEC_RCNTRL_PROM			0x00000008
#define FEC_RCNTRL_BC_REJ		0x00000010
#define FEC_RCNTRL_FCE			0x00000020

#define FEC_TCNTRL_GTS			0x00000001
#define FEC_TCNTRL_HBC			0x00000002
#define FEC_TCNTRL_FDEN			0x00000004
#define FEC_TCNTRL_TFC_PAUSE		0x00000008
#define FEC_TCNTRL_RFC_PAUSE		0x00000010

#define FEC_ECNTRL_RESET		0x00000001	/* reset the FEC */
#define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */

/**
 * @brief Descriptor buffer alignment
 *
 * i.MX27 requires a 16 byte alignment (but for the first element only)
 */
#define DB_ALIGNMENT		16

/**
 * @brief Data buffer alignment
 *
 * i.MX27 requires a four byte alignment for transmit and 16 bits
 * alignment for receive so take 16
 * Note: Valid for member data_pointer in struct buffer_descriptor
 */
#define DB_DATA_ALIGNMENT	16

/**
 * @brief Receive & Transmit Buffer Descriptor definitions
 *
 * Note: The first BD must be aligned (see DB_ALIGNMENT)
 */
struct fec_bd {
	uint16_t data_length;		/* payload's length in bytes */
	uint16_t status;		/* BD's staus (see datasheet) */
	uint32_t data_pointer;		/* payload's buffer address */
};

/**
 * Supported phy types on this platform
 */
enum xceiver_type {
	SEVENWIRE,	/* 7-wire       */
	MII10,		/* MII 10Mbps   */
	MII100		/* MII 100Mbps  */
};

/**
 * @brief i.MX27-FEC private structure
 */
struct fec_priv {
	struct ethernet_regs *eth;	/* pointer to register'S base */
	enum xceiver_type xcv_type;	/* transceiver type */
	struct fec_bd *rbd_base;	/* RBD ring */
	int rbd_index;			/* next receive BD to read */
	struct fec_bd *tbd_base;	/* TBD ring */
	int tbd_index;			/* next transmit BD to write */
	bd_t *bd;
	void *rdb_ptr;
	void *base_ptr;
};

/**
 * @brief Numbers of buffer descriptors for receiving
 *
 * The number defines the stocked memory buffers for the receiving task.
 * Larger values makes no sense in this limited environment.
 */
#define FEC_RBD_NUM		64

/**
 * @brief Define the ethernet packet size limit in memory
 *
 * Note: Do not shrink this number. This will force the FEC to spread larger
 * frames in more than one BD. This is nothing to worry about, but the current
 * driver can't handle it.
 */
#define FEC_MAX_PKT_SIZE	1536

/* Receive BD status bits */
#define FEC_RBD_EMPTY	0x8000	/* Receive BD status: Buffer is empty */
#define FEC_RBD_WRAP	0x2000	/* Receive BD status: Last BD in ring */
/* Receive BD status: Buffer is last in frame (useless here!) */
#define FEC_RBD_LAST	0x0800
#define FEC_RBD_MISS	0x0100	/* Receive BD status: Miss bit for prom mode */
/* Receive BD status: The received frame is broadcast frame */
#define FEC_RBD_BC	0x0080
/* Receive BD status: The received frame is multicast frame */
#define FEC_RBD_MC	0x0040
#define FEC_RBD_LG	0x0020	/* Receive BD status: Frame length violation */
#define FEC_RBD_NO	0x0010	/* Receive BD status: Nonoctet align frame */
#define FEC_RBD_CR	0x0004	/* Receive BD status: CRC error */
#define FEC_RBD_OV	0x0002	/* Receive BD status: Receive FIFO overrun */
#define FEC_RBD_TR	0x0001	/* Receive BD status: Frame is truncated */
#define FEC_RBD_ERR	(FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \
			FEC_RBD_OV | FEC_RBD_TR)

/* Transmit BD status bits */
#define FEC_TBD_READY	0x8000	/* Tansmit BD status: Buffer is ready */
#define FEC_TBD_WRAP	0x2000	/* Tansmit BD status: Mark as last BD in ring */
#define FEC_TBD_LAST	0x0800	/* Tansmit BD status: Buffer is last in frame */
#define FEC_TBD_TC	0x0400	/* Tansmit BD status: Transmit the CRC */
#define FEC_TBD_ABC	0x0200	/* Tansmit BD status: Append bad CRC */

/* MII-related definitios */
#define FEC_MII_DATA_ST		0x40000000	/* Start of frame delimiter */
#define FEC_MII_DATA_OP_RD	0x20000000	/* Perform a read operation */
#define FEC_MII_DATA_OP_WR	0x10000000	/* Perform a write operation */
#define FEC_MII_DATA_PA_MSK	0x0f800000	/* PHY Address field mask */
#define FEC_MII_DATA_RA_MSK	0x007c0000	/* PHY Register field mask */
#define FEC_MII_DATA_TA		0x00020000	/* Turnaround */
#define FEC_MII_DATA_DATAMSK	0x0000ffff	/* PHY data field */

#define FEC_MII_DATA_RA_SHIFT	18	/* MII Register address bits */
#define FEC_MII_DATA_PA_SHIFT	23	/* MII PHY address bits */

#endif	/* __FEC_MXC_H */
Commit	Line	Data
0b23fb36 IY	1	/*
	2	* (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <[email protected]>
	3	* (C) Copyright 2008 Armadeus Systems, nc
	4	* (C) Copyright 2008 Eric Jarrige <[email protected]>
	5	* (C) Copyright 2007 Pengutronix, Sascha Hauer <[email protected]>
	6	* (C) Copyright 2007 Pengutronix, Juergen Beisert <[email protected]>
	7	*
	8	* (C) Copyright 2003
	9	* Wolfgang Denk, DENX Software Engineering, [email protected].
	10	*
	11	* This file is based on mpc4200fec.h
	12	* (C) Copyright Motorola, Inc., 2000
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*
	29	*/
	30
	31
	32	#ifndef __FEC_MXC_H
	33	#define __FEC_MXC_H
	34
	35	/**
	36	* Layout description of the FEC
	37	*/
	38	struct ethernet_regs {
	39
	40	/* [10:2]addr = 00 */
	41
	42	/* Control and status Registers (offset 000-1FF) */
	43
	44	uint32_t res0[1]; /* MBAR_ETH + 0x000 */
	45	uint32_t ievent; /* MBAR_ETH + 0x004 */
	46	uint32_t imask; /* MBAR_ETH + 0x008 */
	47
	48	uint32_t res1[1]; /* MBAR_ETH + 0x00C */
	49	uint32_t r_des_active; /* MBAR_ETH + 0x010 */
	50	uint32_t x_des_active; /* MBAR_ETH + 0x014 */
	51	uint32_t res2[3]; /* MBAR_ETH + 0x018-20 */
	52	uint32_t ecntrl; /* MBAR_ETH + 0x024 */
	53
	54	uint32_t res3[6]; /* MBAR_ETH + 0x028-03C */
	55	uint32_t mii_data; /* MBAR_ETH + 0x040 */
	56	uint32_t mii_speed; /* MBAR_ETH + 0x044 */
	57	uint32_t res4[7]; /* MBAR_ETH + 0x048-60 */
	58	uint32_t mib_control; /* MBAR_ETH + 0x064 */
	59
	60	uint32_t res5[7]; /* MBAR_ETH + 0x068-80 */
	61	uint32_t r_cntrl; /* MBAR_ETH + 0x084 */
	62	uint32_t res6[15]; /* MBAR_ETH + 0x088-C0 */
	63	uint32_t x_cntrl; /* MBAR_ETH + 0x0C4 */
	64	uint32_t res7[7]; /* MBAR_ETH + 0x0C8-E0 */
65	uint32_t paddr1; /* MBAR_ETH + 0x0E4 */
66	uint32_t paddr2; /* MBAR_ETH + 0x0E8 */
67	uint32_t op_pause; /* MBAR_ETH + 0x0EC */
68
69	uint32_t res8[10]; /* MBAR_ETH + 0x0F0-114 */
70	uint32_t iaddr1; /* MBAR_ETH + 0x118 */
71	uint32_t iaddr2; /* MBAR_ETH + 0x11C */
72	uint32_t gaddr1; /* MBAR_ETH + 0x120 */
73	uint32_t gaddr2; /* MBAR_ETH + 0x124 */
74	uint32_t res9[7]; /* MBAR_ETH + 0x128-140 */
75
76	uint32_t x_wmrk; /* MBAR_ETH + 0x144 */
77	uint32_t res10[1]; /* MBAR_ETH + 0x148 */
78	uint32_t r_bound; /* MBAR_ETH + 0x14C */
79	uint32_t r_fstart; /* MBAR_ETH + 0x150 */
80	uint32_t res11[11]; /* MBAR_ETH + 0x154-17C */
81	uint32_t erdsr; /* MBAR_ETH + 0x180 */
82	uint32_t etdsr; /* MBAR_ETH + 0x184 */
83	uint32_t emrbr; /* MBAR_ETH + 0x188 */
84	uint32_t res12[29]; /* MBAR_ETH + 0x18C-1FC */
85
86	/* MIB COUNTERS (Offset 200-2FF) */
87
88	uint32_t rmon_t_drop; /* MBAR_ETH + 0x200 */
89	uint32_t rmon_t_packets; /* MBAR_ETH + 0x204 */
90	uint32_t rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */
91	uint32_t rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */
92	uint32_t rmon_t_crc_align; /* MBAR_ETH + 0x210 */
93	uint32_t rmon_t_undersize; /* MBAR_ETH + 0x214 */
94	uint32_t rmon_t_oversize; /* MBAR_ETH + 0x218 */
95	uint32_t rmon_t_frag; /* MBAR_ETH + 0x21C */
96	uint32_t rmon_t_jab; /* MBAR_ETH + 0x220 */
97	uint32_t rmon_t_col; /* MBAR_ETH + 0x224 */
98	uint32_t rmon_t_p64; /* MBAR_ETH + 0x228 */
99	uint32_t rmon_t_p65to127; /* MBAR_ETH + 0x22C */
100	uint32_t rmon_t_p128to255; /* MBAR_ETH + 0x230 */
101	uint32_t rmon_t_p256to511; /* MBAR_ETH + 0x234 */
102	uint32_t rmon_t_p512to1023; /* MBAR_ETH + 0x238 */
103	uint32_t rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */
104	uint32_t rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */
105	uint32_t rmon_t_octets; /* MBAR_ETH + 0x244 */
106	uint32_t ieee_t_drop; /* MBAR_ETH + 0x248 */
107	uint32_t ieee_t_frame_ok; /* MBAR_ETH + 0x24C */
108	uint32_t ieee_t_1col; /* MBAR_ETH + 0x250 */
109	uint32_t ieee_t_mcol; /* MBAR_ETH + 0x254 */
110	uint32_t ieee_t_def; /* MBAR_ETH + 0x258 */
111	uint32_t ieee_t_lcol; /* MBAR_ETH + 0x25C */
112	uint32_t ieee_t_excol; /* MBAR_ETH + 0x260 */
113	uint32_t ieee_t_macerr; /* MBAR_ETH + 0x264 */
114	uint32_t ieee_t_cserr; /* MBAR_ETH + 0x268 */
115	uint32_t ieee_t_sqe; /* MBAR_ETH + 0x26C */
116	uint32_t t_fdxfc; /* MBAR_ETH + 0x270 */
117	uint32_t ieee_t_octets_ok; /* MBAR_ETH + 0x274 */
118
119	uint32_t res13[2]; /* MBAR_ETH + 0x278-27C */
120	uint32_t rmon_r_drop; /* MBAR_ETH + 0x280 */
121	uint32_t rmon_r_packets; /* MBAR_ETH + 0x284 */
122	uint32_t rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */
123	uint32_t rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */
124	uint32_t rmon_r_crc_align; /* MBAR_ETH + 0x290 */
125	uint32_t rmon_r_undersize; /* MBAR_ETH + 0x294 */
126	uint32_t rmon_r_oversize; /* MBAR_ETH + 0x298 */
127	uint32_t rmon_r_frag; /* MBAR_ETH + 0x29C */
128	uint32_t rmon_r_jab; /* MBAR_ETH + 0x2A0 */
129
130	uint32_t rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */
131
132	uint32_t rmon_r_p64; /* MBAR_ETH + 0x2A8 */
133	uint32_t rmon_r_p65to127; /* MBAR_ETH + 0x2AC */
134	uint32_t rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */
135	uint32_t rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */
136	uint32_t rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */
137	uint32_t rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */
138	uint32_t rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */
139	uint32_t rmon_r_octets; /* MBAR_ETH + 0x2C4 */
140	uint32_t ieee_r_drop; /* MBAR_ETH + 0x2C8 */
141	uint32_t ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */
142	uint32_t ieee_r_crc; /* MBAR_ETH + 0x2D0 */
143	uint32_t ieee_r_align; /* MBAR_ETH + 0x2D4 */
144	uint32_t r_macerr; /* MBAR_ETH + 0x2D8 */
145	uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
146	uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
147
148	uint32_t res14[6]; /* MBAR_ETH + 0x2E4-2FC */
149
150	uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
151	};
152
153	#define FEC_IEVENT_HBERR 0x80000000
154	#define FEC_IEVENT_BABR 0x40000000
155	#define FEC_IEVENT_BABT 0x20000000
156	#define FEC_IEVENT_GRA 0x10000000
157	#define FEC_IEVENT_TXF 0x08000000
158	#define FEC_IEVENT_TXB 0x04000000
159	#define FEC_IEVENT_RXF 0x02000000
160	#define FEC_IEVENT_RXB 0x01000000
161	#define FEC_IEVENT_MII 0x00800000
162	#define FEC_IEVENT_EBERR 0x00400000
163	#define FEC_IEVENT_LC 0x00200000
164	#define FEC_IEVENT_RL 0x00100000
165	#define FEC_IEVENT_UN 0x00080000
166
167	#define FEC_IMASK_HBERR 0x80000000
168	#define FEC_IMASK_BABR 0x40000000
169	#define FEC_IMASKT_BABT 0x20000000
170	#define FEC_IMASK_GRA 0x10000000
171	#define FEC_IMASKT_TXF 0x08000000
172	#define FEC_IMASK_TXB 0x04000000
173	#define FEC_IMASKT_RXF 0x02000000
174	#define FEC_IMASK_RXB 0x01000000
175	#define FEC_IMASK_MII 0x00800000
176	#define FEC_IMASK_EBERR 0x00400000
177	#define FEC_IMASK_LC 0x00200000
178	#define FEC_IMASKT_RL 0x00100000
179	#define FEC_IMASK_UN 0x00080000
180
181
182	#define FEC_RCNTRL_MAX_FL_SHIFT 16
183	#define FEC_RCNTRL_LOOP 0x00000001
184	#define FEC_RCNTRL_DRT 0x00000002
185	#define FEC_RCNTRL_MII_MODE 0x00000004
186	#define FEC_RCNTRL_PROM 0x00000008
187	#define FEC_RCNTRL_BC_REJ 0x00000010
188	#define FEC_RCNTRL_FCE 0x00000020
189
190	#define FEC_TCNTRL_GTS 0x00000001
191	#define FEC_TCNTRL_HBC 0x00000002
192	#define FEC_TCNTRL_FDEN 0x00000004
193	#define FEC_TCNTRL_TFC_PAUSE 0x00000008
194	#define FEC_TCNTRL_RFC_PAUSE 0x00000010
195
196	#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
197	#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
198
199	/**
200	* @brief Descriptor buffer alignment
201	*
202	* i.MX27 requires a 16 byte alignment (but for the first element only)
203	*/
204	#define DB_ALIGNMENT 16
205
206	/**
207	* @brief Data buffer alignment
208	*
209	* i.MX27 requires a four byte alignment for transmit and 16 bits
210	* alignment for receive so take 16
211	* Note: Valid for member data_pointer in struct buffer_descriptor
212	*/
213	#define DB_DATA_ALIGNMENT 16
214
215	/**
216	* @brief Receive & Transmit Buffer Descriptor definitions
217	*
218	* Note: The first BD must be aligned (see DB_ALIGNMENT)
219	*/
220	struct fec_bd {
221	uint16_t data_length; /* payload's length in bytes */
222	uint16_t status; /* BD's staus (see datasheet) */
223	uint32_t data_pointer; /* payload's buffer address */
224	};
225
226	/**
227	* Supported phy types on this platform
228	*/
229	enum xceiver_type {
230	SEVENWIRE, /* 7-wire */
231	MII10, /* MII 10Mbps */
232	MII100 /* MII 100Mbps */
233	};
234
235	/**
236	* @brief i.MX27-FEC private structure
237	*/
238	struct fec_priv {
239	struct ethernet_regs eth; / pointer to register'S base */
240	enum xceiver_type xcv_type; /* transceiver type */
241	struct fec_bd rbd_base; / RBD ring */
242	int rbd_index; /* next receive BD to read */
243	struct fec_bd tbd_base; / TBD ring */
244	int tbd_index; /* next transmit BD to write */
245	bd_t *bd;
246	void *rdb_ptr;
247	void *base_ptr;
248	};
249
250	/**
251	* @brief Numbers of buffer descriptors for receiving
252	*
253	* The number defines the stocked memory buffers for the receiving task.
254	* Larger values makes no sense in this limited environment.
255	*/
256	#define FEC_RBD_NUM 64
257
258	/**
259	* @brief Define the ethernet packet size limit in memory
260	*
261	* Note: Do not shrink this number. This will force the FEC to spread larger
262	* frames in more than one BD. This is nothing to worry about, but the current
263	* driver can't handle it.
264	*/
265	#define FEC_MAX_PKT_SIZE 1536
266
267	/* Receive BD status bits */
268	#define FEC_RBD_EMPTY 0x8000 /* Receive BD status: Buffer is empty */
269	#define FEC_RBD_WRAP 0x2000 /* Receive BD status: Last BD in ring */
270	/* Receive BD status: Buffer is last in frame (useless here!) */
271	#define FEC_RBD_LAST 0x0800
272	#define FEC_RBD_MISS 0x0100 /* Receive BD status: Miss bit for prom mode */
273	/* Receive BD status: The received frame is broadcast frame */
274	#define FEC_RBD_BC 0x0080
275	/* Receive BD status: The received frame is multicast frame */
276	#define FEC_RBD_MC 0x0040
277	#define FEC_RBD_LG 0x0020 /* Receive BD status: Frame length violation */
278	#define FEC_RBD_NO 0x0010 /* Receive BD status: Nonoctet align frame */
279	#define FEC_RBD_CR 0x0004 /* Receive BD status: CRC error */
280	#define FEC_RBD_OV 0x0002 /* Receive BD status: Receive FIFO overrun */
281	#define FEC_RBD_TR 0x0001 /* Receive BD status: Frame is truncated */
282	#define FEC_RBD_ERR (FEC_RBD_LG \| FEC_RBD_NO \| FEC_RBD_CR \| \
283	FEC_RBD_OV \| FEC_RBD_TR)
284
285	/* Transmit BD status bits */
286	#define FEC_TBD_READY 0x8000 /* Tansmit BD status: Buffer is ready */
287	#define FEC_TBD_WRAP 0x2000 /* Tansmit BD status: Mark as last BD in ring */
288	#define FEC_TBD_LAST 0x0800 /* Tansmit BD status: Buffer is last in frame */
289	#define FEC_TBD_TC 0x0400 /* Tansmit BD status: Transmit the CRC */
290	#define FEC_TBD_ABC 0x0200 /* Tansmit BD status: Append bad CRC */
291
292	/* MII-related definitios */
293	#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
294	#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
295	#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
296	#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
297	#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
298	#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */
299	#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
300
301	#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
302	#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
303
304	#endif /* __FEC_MXC_H */