[J-u-boot.git] / cmd / mii.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2001
 * Gerald Van Baren, Custom IDEAS, [email protected]
 */

/*
 * MII Utilities
 */

#include <common.h>
#include <command.h>
#include <miiphy.h>

typedef struct _MII_field_desc_t {
	ushort hi;
	ushort lo;
	ushort mask;
	const char *name;
} MII_field_desc_t;

static const MII_field_desc_t reg_0_desc_tbl[] = {
	{ 15, 15, 0x01, "reset"                        },
	{ 14, 14, 0x01, "loopback"                     },
	{ 13,  6, 0x81, "speed selection"              }, /* special */
	{ 12, 12, 0x01, "A/N enable"                   },
	{ 11, 11, 0x01, "power-down"                   },
	{ 10, 10, 0x01, "isolate"                      },
	{  9,  9, 0x01, "restart A/N"                  },
	{  8,  8, 0x01, "duplex"                       }, /* special */
	{  7,  7, 0x01, "collision test enable"        },
	{  5,  0, 0x3f, "(reserved)"                   }
};

static const MII_field_desc_t reg_1_desc_tbl[] = {
	{ 15, 15, 0x01, "100BASE-T4 able"              },
	{ 14, 14, 0x01, "100BASE-X  full duplex able"  },
	{ 13, 13, 0x01, "100BASE-X  half duplex able"  },
	{ 12, 12, 0x01, "10 Mbps    full duplex able"  },
	{ 11, 11, 0x01, "10 Mbps    half duplex able"  },
	{ 10, 10, 0x01, "100BASE-T2 full duplex able"  },
	{  9,  9, 0x01, "100BASE-T2 half duplex able"  },
	{  8,  8, 0x01, "extended status"              },
	{  7,  7, 0x01, "(reserved)"                   },
	{  6,  6, 0x01, "MF preamble suppression"      },
	{  5,  5, 0x01, "A/N complete"                 },
	{  4,  4, 0x01, "remote fault"                 },
	{  3,  3, 0x01, "A/N able"                     },
	{  2,  2, 0x01, "link status"                  },
	{  1,  1, 0x01, "jabber detect"                },
	{  0,  0, 0x01, "extended capabilities"        },
};

static const MII_field_desc_t reg_2_desc_tbl[] = {
	{ 15,  0, 0xffff, "OUI portion"                },
};

static const MII_field_desc_t reg_3_desc_tbl[] = {
	{ 15, 10, 0x3f, "OUI portion"                },
	{  9,  4, 0x3f, "manufacturer part number"   },
	{  3,  0, 0x0f, "manufacturer rev. number"   },
};

static const MII_field_desc_t reg_4_desc_tbl[] = {
	{ 15, 15, 0x01, "next page able"               },
	{ 14, 14, 0x01, "(reserved)"                   },
	{ 13, 13, 0x01, "remote fault"                 },
	{ 12, 12, 0x01, "(reserved)"                   },
	{ 11, 11, 0x01, "asymmetric pause"             },
	{ 10, 10, 0x01, "pause enable"                 },
	{  9,  9, 0x01, "100BASE-T4 able"              },
	{  8,  8, 0x01, "100BASE-TX full duplex able"  },
	{  7,  7, 0x01, "100BASE-TX able"              },
	{  6,  6, 0x01, "10BASE-T   full duplex able"  },
	{  5,  5, 0x01, "10BASE-T   able"              },
	{  4,  0, 0x1f, "selector"                     },
};

static const MII_field_desc_t reg_5_desc_tbl[] = {
	{ 15, 15, 0x01, "next page able"               },
	{ 14, 14, 0x01, "acknowledge"                  },
	{ 13, 13, 0x01, "remote fault"                 },
	{ 12, 12, 0x01, "(reserved)"                   },
	{ 11, 11, 0x01, "asymmetric pause able"        },
	{ 10, 10, 0x01, "pause able"                   },
	{  9,  9, 0x01, "100BASE-T4 able"              },
	{  8,  8, 0x01, "100BASE-X full duplex able"   },
	{  7,  7, 0x01, "100BASE-TX able"              },
	{  6,  6, 0x01, "10BASE-T full duplex able"    },
	{  5,  5, 0x01, "10BASE-T able"                },
	{  4,  0, 0x1f, "partner selector"             },
};

static const MII_field_desc_t reg_9_desc_tbl[] = {
	{ 15, 13, 0x07, "test mode"		       },
	{ 12, 12, 0x01, "manual master/slave enable"   },
	{ 11, 11, 0x01, "manual master/slave value"    },
	{ 10, 10, 0x01, "multi/single port"            },
	{  9,  9, 0x01, "1000BASE-T full duplex able"  },
	{  8,  8, 0x01, "1000BASE-T half duplex able"  },
	{  7,  7, 0x01, "automatic TDR on link down"   },
	{  6,  6, 0x7f, "(reserved)"                   },
};

static const MII_field_desc_t reg_10_desc_tbl[] = {
	{ 15, 15, 0x01, "master/slave config fault"    },
	{ 14, 14, 0x01, "master/slave config result"   },
	{ 13, 13, 0x01, "local receiver status OK"     },
	{ 12, 12, 0x01, "remote receiver status OK"    },
	{ 11, 11, 0x01, "1000BASE-T full duplex able"  },
	{ 10, 10, 0x01, "1000BASE-T half duplex able"  },
	{  9,  8, 0x03, "(reserved)"                   },
	{  7,  0, 0xff, "1000BASE-T idle error counter"},
};

typedef struct _MII_reg_desc_t {
	ushort regno;
	const MII_field_desc_t *pdesc;
	ushort len;
	const char *name;
} MII_reg_desc_t;

static const MII_reg_desc_t mii_reg_desc_tbl[] = {
	{ MII_BMCR,      reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
		"PHY control register" },
	{ MII_BMSR,      reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl),
		"PHY status register" },
	{ MII_PHYSID1,   reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl),
		"PHY ID 1 register" },
	{ MII_PHYSID2,   reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl),
		"PHY ID 2 register" },
	{ MII_ADVERTISE, reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl),
		"Autonegotiation advertisement register" },
	{ MII_LPA,       reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl),
		"Autonegotiation partner abilities register" },
	{ MII_CTRL1000,	 reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
		"1000BASE-T control register" },
	{ MII_STAT1000,	 reg_10_desc_tbl, ARRAY_SIZE(reg_10_desc_tbl),
		"1000BASE-T status register" },
};

static void dump_reg(
	ushort             regval,
	const MII_reg_desc_t *prd);

static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
			  ushort regval);

static void MII_dump(const ushort *regvals, uchar reglo, uchar reghi)
{
	ulong i;

	for (i = 0; i < ARRAY_SIZE(mii_reg_desc_tbl); i++) {
		const uchar reg = mii_reg_desc_tbl[i].regno;

		if (reg >= reglo && reg <= reghi)
			dump_reg(regvals[reg - reglo], &mii_reg_desc_tbl[i]);
	}
}

/* Print out field position, value, name */
static void dump_field(const MII_field_desc_t *pdesc, ushort regval)
{
	if (pdesc->hi == pdesc->lo)
		printf("%2u   ", pdesc->lo);
	else
		printf("%2u-%2u", pdesc->hi, pdesc->lo);

	printf(" = %5u	  %s", (regval >> pdesc->lo) & pdesc->mask,
	       pdesc->name);
}

static void dump_reg(
	ushort             regval,
	const MII_reg_desc_t *prd)
{
	ulong i;
	ushort mask_in_place;
	const MII_field_desc_t *pdesc;

	printf("%u.     (%04hx)                 -- %s --\n",
		prd->regno, regval, prd->name);

	for (i = 0; i < prd->len; i++) {
		pdesc = &prd->pdesc[i];

		mask_in_place = pdesc->mask << pdesc->lo;

		printf("  (%04hx:%04x) %u.",
		       mask_in_place,
		       regval & mask_in_place,
		       prd->regno);

		if (!special_field(prd->regno, pdesc, regval))
			dump_field(pdesc, regval);
		printf("\n");

	}
	printf("\n");
}

/* Special fields:
** 0.6,13
** 0.8
** 2.15-0
** 3.15-0
** 4.4-0
** 5.4-0
*/

static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
			  ushort regval)
{
	const ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;

	if ((regno == MII_BMCR) && (pdesc->lo == 6)) {
		ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100);
		printf("%2u,%2u =   b%u%u    speed selection = %s Mbps",
			6, 13,
			(regval >>  6) & 1,
			(regval >> 13) & 1,
			speed_bits == BMCR_SPEED1000 ? "1000" :
			speed_bits == BMCR_SPEED100  ? "100" :
			"10");
		return 1;
	}

	else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
		dump_field(pdesc, regval);
		printf(" = %s", ((regval >> pdesc->lo) & 1) ? "full" : "half");
		return 1;
	}

	else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) {
		dump_field(pdesc, regval);
		printf(" = %s",
		       sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
		       sel_bits == PHY_ANLPAR_PSB_802_9 ?
		       "IEEE 802.9 ISLAN-16T" : "???");
		return 1;
	}

	else if ((regno == MII_LPA) && (pdesc->lo == 0)) {
		dump_field(pdesc, regval);
		printf(" = %s",
		       sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
		       sel_bits == PHY_ANLPAR_PSB_802_9 ?
		       "IEEE 802.9 ISLAN-16T" : "???");
		return 1;
	}

	return 0;
}

static char last_op[2];
static uint last_data;
static uint last_addr_lo;
static uint last_addr_hi;
static uint last_reg_lo;
static uint last_reg_hi;
static uint last_mask;

static void extract_range(
	char * input,
	unsigned char * plo,
	unsigned char * phi)
{
	char * end;
	*plo = simple_strtoul(input, &end, 16);
	if (*end == '-') {
		end++;
		*phi = simple_strtoul(end, NULL, 16);
	}
	else {
		*phi = *plo;
	}
}

/* ---------------------------------------------------------------- */
static int do_mii(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	char		op[2];
	unsigned char	addrlo, addrhi, reglo, reghi;
	unsigned char	addr, reg;
	unsigned short	data, mask;
	int		rcode = 0;
	const char	*devname;

	if (argc < 2)
		return CMD_RET_USAGE;

#if defined(CONFIG_MII_INIT)
	mii_init ();
#endif

	/*
	 * We use the last specified parameters, unless new ones are
	 * entered.
	 */
	op[0] = last_op[0];
	op[1] = last_op[1];
	addrlo = last_addr_lo;
	addrhi = last_addr_hi;
	reglo  = last_reg_lo;
	reghi  = last_reg_hi;
	data   = last_data;
	mask   = last_mask;

	if ((flag & CMD_FLAG_REPEAT) == 0) {
		op[0] = argv[1][0];
		if (strlen(argv[1]) > 1)
			op[1] = argv[1][1];
		else
			op[1] = '\0';

		if (argc >= 3)
			extract_range(argv[2], &addrlo, &addrhi);
		if (argc >= 4)
			extract_range(argv[3], &reglo, &reghi);
		if (argc >= 5)
			data = simple_strtoul(argv[4], NULL, 16);
		if (argc >= 6)
			mask = simple_strtoul(argv[5], NULL, 16);
	}

	if (addrhi > 31 && strncmp(op, "de", 2)) {
		printf("Incorrect PHY address. Range should be 0-31\n");
		return CMD_RET_USAGE;
	}

	/* use current device */
	devname = miiphy_get_current_dev();

	/*
	 * check info/read/write.
	 */
	if (op[0] == 'i') {
		unsigned char j, start, end;
		unsigned int oui;
		unsigned char model;
		unsigned char rev;

		/*
		 * Look for any and all PHYs.  Valid addresses are 0..31.
		 */
		if (argc >= 3) {
			start = addrlo; end = addrhi;
		} else {
			start = 0; end = 31;
		}

		for (j = start; j <= end; j++) {
			if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
				printf("PHY 0x%02X: "
					"OUI = 0x%04X, "
					"Model = 0x%02X, "
					"Rev = 0x%02X, "
					"%3dbase%s, %s\n",
					j, oui, model, rev,
					miiphy_speed (devname, j),
					miiphy_is_1000base_x (devname, j)
						? "X" : "T",
					(miiphy_duplex (devname, j) == FULL)
						? "FDX" : "HDX");
			}
		}
	} else if (op[0] == 'r') {
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				data = 0xffff;
				if (miiphy_read (devname, addr, reg, &data) != 0) {
					printf(
					"Error reading from the PHY addr=%02x reg=%02x\n",
						addr, reg);
					rcode = 1;
				} else {
					if ((addrlo != addrhi) || (reglo != reghi))
						printf("addr=%02x reg=%02x data=",
							(uint)addr, (uint)reg);
					printf("%04X\n", data & 0x0000FFFF);
				}
			}
			if ((addrlo != addrhi) && (reglo != reghi))
				printf("\n");
		}
	} else if (op[0] == 'w') {
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				if (miiphy_write (devname, addr, reg, data) != 0) {
					printf("Error writing to the PHY addr=%02x reg=%02x\n",
						addr, reg);
					rcode = 1;
				}
			}
		}
	} else if (op[0] == 'm') {
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				unsigned short val = 0;
				if (miiphy_read(devname, addr,
						reg, &val)) {
					printf("Error reading from the PHY");
					printf(" addr=%02x", addr);
					printf(" reg=%02x\n", reg);
					rcode = 1;
				} else {
					val = (val & ~mask) | (data & mask);
					if (miiphy_write(devname, addr,
							 reg, val)) {
						printf("Error writing to the PHY");
						printf(" addr=%02x", addr);
						printf(" reg=%02x\n", reg);
						rcode = 1;
					}
				}
			}
		}
	} else if (strncmp(op, "du", 2) == 0) {
		ushort regs[MII_STAT1000 + 1];  /* Last reg is 0x0a */
		int ok = 1;
		if (reglo > MII_STAT1000 || reghi > MII_STAT1000) {
			printf("The MII dump command only formats the standard MII registers, 0-5, 9-a.\n");
			return 1;
		}
		for (addr = addrlo; addr <= addrhi; addr++) {
			for (reg = reglo; reg <= reghi; reg++) {
				if (miiphy_read(devname, addr, reg,
						&regs[reg - reglo]) != 0) {
					ok = 0;
					printf(
					"Error reading from the PHY addr=%02x reg=%02x\n",
						addr, reg);
					rcode = 1;
				}
			}
			if (ok)
				MII_dump(regs, reglo, reghi);
			printf("\n");
		}
	} else if (strncmp(op, "de", 2) == 0) {
		if (argc == 2)
			miiphy_listdev ();
		else
			miiphy_set_current_dev (argv[2]);
	} else {
		return CMD_RET_USAGE;
	}

	/*
	 * Save the parameters for repeats.
	 */
	last_op[0] = op[0];
	last_op[1] = op[1];
	last_addr_lo = addrlo;
	last_addr_hi = addrhi;
	last_reg_lo  = reglo;
	last_reg_hi  = reghi;
	last_data    = data;
	last_mask    = mask;

	return rcode;
}

/***************************************************/

U_BOOT_CMD(
	mii, 6, 1, do_mii,
	"MII utility commands",
	"device                            - list available devices\n"
	"mii device <devname>                  - set current device\n"
	"mii info   <addr>                     - display MII PHY info\n"
	"mii read   <addr> <reg>               - read  MII PHY <addr> register <reg>\n"
	"mii write  <addr> <reg> <data>        - write MII PHY <addr> register <reg>\n"
	"mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
	"                                        updating bits identified in <mask>\n"
	"mii dump   <addr> <reg>               - pretty-print <addr> <reg> (0-5 only)\n"
	"Addr and/or reg may be ranges, e.g. 2-7."
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
dd7d41f0 WD	2	/*
	3	* (C) Copyright 2001
	4	* Gerald Van Baren, Custom IDEAS, [email protected]
dd7d41f0 WD	5	*/
	6
	7	/*
	8	* MII Utilities
	9	*/
	10
	11	#include <common.h>
	12	#include <command.h>
e35745bb WD	13	#include <miiphy.h>
e35745bb WD	14
2471111d WD	15	typedef struct _MII_field_desc_t {
	16	ushort hi;
	17	ushort lo;
	18	ushort mask;
4ef3231b	19	const char *name;
2471111d WD	20	} MII_field_desc_t;
2471111d WD	21
3a5ee0b1	22	static const MII_field_desc_t reg_0_desc_tbl[] = {
2471111d WD	23	{ 15, 15, 0x01, "reset" },
	24	{ 14, 14, 0x01, "loopback" },
	25	{ 13, 6, 0x81, "speed selection" }, /* special */
	26	{ 12, 12, 0x01, "A/N enable" },
	27	{ 11, 11, 0x01, "power-down" },
	28	{ 10, 10, 0x01, "isolate" },
	29	{ 9, 9, 0x01, "restart A/N" },
	30	{ 8, 8, 0x01, "duplex" }, /* special */
	31	{ 7, 7, 0x01, "collision test enable" },
	32	{ 5, 0, 0x3f, "(reserved)" }
	33	};
	34
3a5ee0b1	35	static const MII_field_desc_t reg_1_desc_tbl[] = {
2471111d WD	36	{ 15, 15, 0x01, "100BASE-T4 able" },
	37	{ 14, 14, 0x01, "100BASE-X full duplex able" },
	38	{ 13, 13, 0x01, "100BASE-X half duplex able" },
	39	{ 12, 12, 0x01, "10 Mbps full duplex able" },
	40	{ 11, 11, 0x01, "10 Mbps half duplex able" },
	41	{ 10, 10, 0x01, "100BASE-T2 full duplex able" },
	42	{ 9, 9, 0x01, "100BASE-T2 half duplex able" },
	43	{ 8, 8, 0x01, "extended status" },
	44	{ 7, 7, 0x01, "(reserved)" },
	45	{ 6, 6, 0x01, "MF preamble suppression" },
	46	{ 5, 5, 0x01, "A/N complete" },
	47	{ 4, 4, 0x01, "remote fault" },
	48	{ 3, 3, 0x01, "A/N able" },
	49	{ 2, 2, 0x01, "link status" },
	50	{ 1, 1, 0x01, "jabber detect" },
	51	{ 0, 0, 0x01, "extended capabilities" },
	52	};
	53
3a5ee0b1	54	static const MII_field_desc_t reg_2_desc_tbl[] = {
2471111d WD	55	{ 15, 0, 0xffff, "OUI portion" },
	56	};
	57
3a5ee0b1	58	static const MII_field_desc_t reg_3_desc_tbl[] = {
2471111d WD	59	{ 15, 10, 0x3f, "OUI portion" },
	60	{ 9, 4, 0x3f, "manufacturer part number" },
	61	{ 3, 0, 0x0f, "manufacturer rev. number" },
	62	};
	63
3a5ee0b1	64	static const MII_field_desc_t reg_4_desc_tbl[] = {
2471111d	65	{ 15, 15, 0x01, "next page able" },
57d33d4b	66	{ 14, 14, 0x01, "(reserved)" },
2471111d	67	{ 13, 13, 0x01, "remote fault" },
57d33d4b	68	{ 12, 12, 0x01, "(reserved)" },
2471111d WD	69	{ 11, 11, 0x01, "asymmetric pause" },
	70	{ 10, 10, 0x01, "pause enable" },
	71	{ 9, 9, 0x01, "100BASE-T4 able" },
	72	{ 8, 8, 0x01, "100BASE-TX full duplex able" },
	73	{ 7, 7, 0x01, "100BASE-TX able" },
	74	{ 6, 6, 0x01, "10BASE-T full duplex able" },
	75	{ 5, 5, 0x01, "10BASE-T able" },
4ef3231b	76	{ 4, 0, 0x1f, "selector" },
2471111d WD	77	};
2471111d WD	78
3a5ee0b1	79	static const MII_field_desc_t reg_5_desc_tbl[] = {
2471111d WD	80	{ 15, 15, 0x01, "next page able" },
	81	{ 14, 14, 0x01, "acknowledge" },
	82	{ 13, 13, 0x01, "remote fault" },
	83	{ 12, 12, 0x01, "(reserved)" },
	84	{ 11, 11, 0x01, "asymmetric pause able" },
	85	{ 10, 10, 0x01, "pause able" },
	86	{ 9, 9, 0x01, "100BASE-T4 able" },
	87	{ 8, 8, 0x01, "100BASE-X full duplex able" },
	88	{ 7, 7, 0x01, "100BASE-TX able" },
	89	{ 6, 6, 0x01, "10BASE-T full duplex able" },
	90	{ 5, 5, 0x01, "10BASE-T able" },
4ef3231b	91	{ 4, 0, 0x1f, "partner selector" },
2471111d	92	};
4ef3231b	93
95637868 TP	94	static const MII_field_desc_t reg_9_desc_tbl[] = {
	95	{ 15, 13, 0x07, "test mode" },
	96	{ 12, 12, 0x01, "manual master/slave enable" },
	97	{ 11, 11, 0x01, "manual master/slave value" },
	98	{ 10, 10, 0x01, "multi/single port" },
	99	{ 9, 9, 0x01, "1000BASE-T full duplex able" },
	100	{ 8, 8, 0x01, "1000BASE-T half duplex able" },
	101	{ 7, 7, 0x01, "automatic TDR on link down" },
	102	{ 6, 6, 0x7f, "(reserved)" },
	103	};
	104
	105	static const MII_field_desc_t reg_10_desc_tbl[] = {
	106	{ 15, 15, 0x01, "master/slave config fault" },
	107	{ 14, 14, 0x01, "master/slave config result" },
	108	{ 13, 13, 0x01, "local receiver status OK" },
	109	{ 12, 12, 0x01, "remote receiver status OK" },
	110	{ 11, 11, 0x01, "1000BASE-T full duplex able" },
	111	{ 10, 10, 0x01, "1000BASE-T half duplex able" },
	112	{ 9, 8, 0x03, "(reserved)" },
	113	{ 7, 0, 0xff, "1000BASE-T idle error counter"},
	114	};
	115
4ef3231b TP	116	typedef struct _MII_reg_desc_t {
4ef3231b TP	117	ushort regno;
3a5ee0b1	118	const MII_field_desc_t *pdesc;
2471111d	119	ushort len;
4ef3231b TP	120	const char *name;
	121	} MII_reg_desc_t;
	122
	123	static const MII_reg_desc_t mii_reg_desc_tbl[] = {
	124	{ MII_BMCR, reg_0_desc_tbl, ARRAY_SIZE(reg_0_desc_tbl),
	125	"PHY control register" },
	126	{ MII_BMSR, reg_1_desc_tbl, ARRAY_SIZE(reg_1_desc_tbl),
	127	"PHY status register" },
	128	{ MII_PHYSID1, reg_2_desc_tbl, ARRAY_SIZE(reg_2_desc_tbl),
	129	"PHY ID 1 register" },
	130	{ MII_PHYSID2, reg_3_desc_tbl, ARRAY_SIZE(reg_3_desc_tbl),
	131	"PHY ID 2 register" },
	132	{ MII_ADVERTISE, reg_4_desc_tbl, ARRAY_SIZE(reg_4_desc_tbl),
	133	"Autonegotiation advertisement register" },
	134	{ MII_LPA, reg_5_desc_tbl, ARRAY_SIZE(reg_5_desc_tbl),
	135	"Autonegotiation partner abilities register" },
95637868 TP	136	{ MII_CTRL1000, reg_9_desc_tbl, ARRAY_SIZE(reg_9_desc_tbl),
	137	"1000BASE-T control register" },
	138	{ MII_STAT1000, reg_10_desc_tbl, ARRAY_SIZE(reg_10_desc_tbl),
	139	"1000BASE-T status register" },
2471111d WD	140	};
	141
	142	static void dump_reg(
	143	ushort regval,
4ef3231b TP	144	const MII_reg_desc_t *prd);
	145
	146	static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
	147	ushort regval);
	148
	149	static void MII_dump(const ushort *regvals, uchar reglo, uchar reghi)
2471111d WD	150	{
	151	ulong i;
	152
4ef3231b TP	153	for (i = 0; i < ARRAY_SIZE(mii_reg_desc_tbl); i++) {
	154	const uchar reg = mii_reg_desc_tbl[i].regno;
	155
	156	if (reg >= reglo && reg <= reghi)
	157	dump_reg(regvals[reg - reglo], &mii_reg_desc_tbl[i]);
2471111d WD	158	}
	159	}
	160
4ef3231b TP	161	/* Print out field position, value, name */
	162	static void dump_field(const MII_field_desc_t *pdesc, ushort regval)
	163	{
	164	if (pdesc->hi == pdesc->lo)
	165	printf("%2u ", pdesc->lo);
	166	else
	167	printf("%2u-%2u", pdesc->hi, pdesc->lo);
	168
	169	printf(" = %5u %s", (regval >> pdesc->lo) & pdesc->mask,
	170	pdesc->name);
	171	}
	172
2471111d WD	173	static void dump_reg(
2471111d WD	174	ushort regval,
4ef3231b	175	const MII_reg_desc_t *prd)
2471111d WD	176	{
	177	ulong i;
	178	ushort mask_in_place;
3a5ee0b1	179	const MII_field_desc_t *pdesc;
2471111d WD	180
	181	printf("%u. (%04hx) -- %s --\n",
	182	prd->regno, regval, prd->name);
	183
4ef3231b TP	184	for (i = 0; i < prd->len; i++) {
4ef3231b TP	185	pdesc = &prd->pdesc[i];
2471111d WD	186
	187	mask_in_place = pdesc->mask << pdesc->lo;
	188
c68112f3 JH	189	printf(" (%04hx:%04x) %u.",
	190	mask_in_place,
	191	regval & mask_in_place,
	192	prd->regno);
2471111d	193
4ef3231b TP	194	if (!special_field(prd->regno, pdesc, regval))
4ef3231b TP	195	dump_field(pdesc, regval);
2471111d WD	196	printf("\n");
	197
	198	}
	199	printf("\n");
	200	}
	201
	202	/* Special fields:
	203	** 0.6,13
	204	** 0.8
	205	** 2.15-0
	206	** 3.15-0
	207	** 4.4-0
	208	** 5.4-0
	209	*/
	210
4ef3231b TP	211	static bool special_field(ushort regno, const MII_field_desc_t *pdesc,
4ef3231b TP	212	ushort regval)
2471111d	213	{
4ef3231b TP	214	const ushort sel_bits = (regval >> pdesc->lo) & pdesc->mask;
4ef3231b TP	215
8ef583a0 MF	216	if ((regno == MII_BMCR) && (pdesc->lo == 6)) {
8ef583a0 MF	217	ushort speed_bits = regval & (BMCR_SPEED1000 \| BMCR_SPEED100);
2471111d WD	218	printf("%2u,%2u = b%u%u speed selection = %s Mbps",
	219	6, 13,
	220	(regval >> 6) & 1,
	221	(regval >> 13) & 1,
8ef583a0 MF	222	speed_bits == BMCR_SPEED1000 ? "1000" :
	223	speed_bits == BMCR_SPEED100 ? "100" :
	224	"10");
2471111d WD	225	return 1;
	226	}
	227
8ef583a0	228	else if ((regno == MII_BMCR) && (pdesc->lo == 8)) {
4ef3231b TP	229	dump_field(pdesc, regval);
4ef3231b TP	230	printf(" = %s", ((regval >> pdesc->lo) & 1) ? "full" : "half");
2471111d WD	231	return 1;
	232	}
	233
8ef583a0	234	else if ((regno == MII_ADVERTISE) && (pdesc->lo == 0)) {
4ef3231b TP	235	dump_field(pdesc, regval);
	236	printf(" = %s",
	237	sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
	238	sel_bits == PHY_ANLPAR_PSB_802_9 ?
	239	"IEEE 802.9 ISLAN-16T" : "???");
2471111d WD	240	return 1;
	241	}
	242
8ef583a0	243	else if ((regno == MII_LPA) && (pdesc->lo == 0)) {
4ef3231b TP	244	dump_field(pdesc, regval);
	245	printf(" = %s",
	246	sel_bits == PHY_ANLPAR_PSB_802_3 ? "IEEE 802.3 CSMA/CD" :
	247	sel_bits == PHY_ANLPAR_PSB_802_9 ?
	248	"IEEE 802.9 ISLAN-16T" : "???");
2471111d WD	249	return 1;
	250	}
	251
	252	return 0;
	253	}
	254
3a5ee0b1 MF	255	static char last_op[2];
	256	static uint last_data;
	257	static uint last_addr_lo;
	258	static uint last_addr_hi;
	259	static uint last_reg_lo;
	260	static uint last_reg_hi;
a095f047	261	static uint last_mask;
2471111d WD	262
	263	static void extract_range(
	264	char * input,
	265	unsigned char * plo,
	266	unsigned char * phi)
	267	{
	268	char * end;
	269	*plo = simple_strtoul(input, &end, 16);
	270	if (*end == '-') {
	271	end++;
	272	*phi = simple_strtoul(end, NULL, 16);
	273	}
	274	else {
	275	phi = plo;
	276	}
	277	}
	278
5cf91d6b	279	/* ---------------------------------------------------------------- */
09140113	280	static int do_mii(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
2471111d	281	{
63ff004c	282	char op[2];
2471111d	283	unsigned char addrlo, addrhi, reglo, reghi;
2b792afc	284	unsigned char addr, reg;
a095f047	285	unsigned short data, mask;
2471111d	286	int rcode = 0;
5700bb63	287	const char *devname;
2471111d	288
47e26b1b	289	if (argc < 2)
4c12eeb8	290	return CMD_RET_USAGE;
b9173af7	291
0f3ba7e9	292	#if defined(CONFIG_MII_INIT)
2471111d WD	293	mii_init ();
	294	#endif
	295
	296	/*
	297	* We use the last specified parameters, unless new ones are
	298	* entered.
	299	*/
63ff004c MB	300	op[0] = last_op[0];
63ff004c MB	301	op[1] = last_op[1];
2471111d WD	302	addrlo = last_addr_lo;
	303	addrhi = last_addr_hi;
	304	reglo = last_reg_lo;
	305	reghi = last_reg_hi;
	306	data = last_data;
a095f047	307	mask = last_mask;
2471111d WD	308
2471111d WD	309	if ((flag & CMD_FLAG_REPEAT) == 0) {
63ff004c MB	310	op[0] = argv[1][0];
	311	if (strlen(argv[1]) > 1)
	312	op[1] = argv[1][1];
	313	else
	314	op[1] = '\0';
	315
2471111d WD	316	if (argc >= 3)
	317	extract_range(argv[2], &addrlo, &addrhi);
	318	if (argc >= 4)
	319	extract_range(argv[3], &reglo, &reghi);
	320	if (argc >= 5)
a095f047 TJ	321	data = simple_strtoul(argv[4], NULL, 16);
	322	if (argc >= 6)
	323	mask = simple_strtoul(argv[5], NULL, 16);
2471111d WD	324	}
2471111d WD	325
fb265a74	326	if (addrhi > 31 && strncmp(op, "de", 2)) {
bdaeb8f2 MS	327	printf("Incorrect PHY address. Range should be 0-31\n");
	328	return CMD_RET_USAGE;
	329	}
	330
63ff004c MB	331	/* use current device */
	332	devname = miiphy_get_current_dev();
	333
2471111d WD	334	/*
	335	* check info/read/write.
	336	*/
63ff004c	337	if (op[0] == 'i') {
2471111d WD	338	unsigned char j, start, end;
	339	unsigned int oui;
	340	unsigned char model;
	341	unsigned char rev;
	342
	343	/*
	344	* Look for any and all PHYs. Valid addresses are 0..31.
	345	*/
	346	if (argc >= 3) {
2b792afc	347	start = addrlo; end = addrhi;
2471111d	348	} else {
2b792afc	349	start = 0; end = 31;
2471111d WD	350	}
2471111d WD	351
2b792afc	352	for (j = start; j <= end; j++) {
63ff004c	353	if (miiphy_info (devname, j, &oui, &model, &rev) == 0) {
2471111d WD	354	printf("PHY 0x%02X: "
	355	"OUI = 0x%04X, "
	356	"Model = 0x%02X, "
	357	"Rev = 0x%02X, "
71bc6e64	358	"%3dbase%s, %s\n",
2471111d	359	j, oui, model, rev,
63ff004c	360	miiphy_speed (devname, j),
71bc6e64 LJ	361	miiphy_is_1000base_x (devname, j)
71bc6e64 LJ	362	? "X" : "T",
63ff004c MB	363	(miiphy_duplex (devname, j) == FULL)
63ff004c MB	364	? "FDX" : "HDX");
2471111d WD	365	}
2471111d WD	366	}
63ff004c	367	} else if (op[0] == 'r') {
2471111d WD	368	for (addr = addrlo; addr <= addrhi; addr++) {
	369	for (reg = reglo; reg <= reghi; reg++) {
	370	data = 0xffff;
63ff004c	371	if (miiphy_read (devname, addr, reg, &data) != 0) {
2471111d WD	372	printf(
	373	"Error reading from the PHY addr=%02x reg=%02x\n",
	374	addr, reg);
	375	rcode = 1;
2b792afc	376	} else {
2471111d WD	377	if ((addrlo != addrhi) \|\| (reglo != reghi))
	378	printf("addr=%02x reg=%02x data=",
	379	(uint)addr, (uint)reg);
	380	printf("%04X\n", data & 0x0000FFFF);
	381	}
	382	}
	383	if ((addrlo != addrhi) && (reglo != reghi))
	384	printf("\n");
	385	}
63ff004c	386	} else if (op[0] == 'w') {
2471111d WD	387	for (addr = addrlo; addr <= addrhi; addr++) {
2471111d WD	388	for (reg = reglo; reg <= reghi; reg++) {
63ff004c	389	if (miiphy_write (devname, addr, reg, data) != 0) {
2471111d WD	390	printf("Error writing to the PHY addr=%02x reg=%02x\n",
	391	addr, reg);
	392	rcode = 1;
	393	}
	394	}
	395	}
a095f047 TJ	396	} else if (op[0] == 'm') {
	397	for (addr = addrlo; addr <= addrhi; addr++) {
	398	for (reg = reglo; reg <= reghi; reg++) {
	399	unsigned short val = 0;
	400	if (miiphy_read(devname, addr,
	401	reg, &val)) {
	402	printf("Error reading from the PHY");
	403	printf(" addr=%02x", addr);
	404	printf(" reg=%02x\n", reg);
	405	rcode = 1;
	406	} else {
	407	val = (val & ~mask) \| (data & mask);
	408	if (miiphy_write(devname, addr,
	409	reg, val)) {
	410	printf("Error writing to the PHY");
	411	printf(" addr=%02x", addr);
	412	printf(" reg=%02x\n", reg);
	413	rcode = 1;
	414	}
	415	}
	416	}
	417	}
63ff004c	418	} else if (strncmp(op, "du", 2) == 0) {
95637868	419	ushort regs[MII_STAT1000 + 1]; /* Last reg is 0x0a */
2471111d	420	int ok = 1;
95637868 TP	421	if (reglo > MII_STAT1000 \|\| reghi > MII_STAT1000) {
95637868 TP	422	printf("The MII dump command only formats the standard MII registers, 0-5, 9-a.\n");
2471111d WD	423	return 1;
	424	}
	425	for (addr = addrlo; addr <= addrhi; addr++) {
4ef3231b TP	426	for (reg = reglo; reg <= reghi; reg++) {
	427	if (miiphy_read(devname, addr, reg,
	428	&regs[reg - reglo]) != 0) {
2471111d WD	429	ok = 0;
	430	printf(
	431	"Error reading from the PHY addr=%02x reg=%02x\n",
	432	addr, reg);
	433	rcode = 1;
	434	}
	435	}
	436	if (ok)
4ef3231b	437	MII_dump(regs, reglo, reghi);
2471111d WD	438	printf("\n");
2471111d WD	439	}
63ff004c MB	440	} else if (strncmp(op, "de", 2) == 0) {
	441	if (argc == 2)
	442	miiphy_listdev ();
	443	else
	444	miiphy_set_current_dev (argv[2]);
2471111d	445	} else {
4c12eeb8	446	return CMD_RET_USAGE;
2471111d WD	447	}
	448
	449	/*
	450	* Save the parameters for repeats.
	451	*/
63ff004c MB	452	last_op[0] = op[0];
63ff004c MB	453	last_op[1] = op[1];
2471111d WD	454	last_addr_lo = addrlo;
	455	last_addr_hi = addrhi;
	456	last_reg_lo = reglo;
	457	last_reg_hi = reghi;
	458	last_data = data;
a095f047	459	last_mask = mask;
2471111d WD	460
	461	return rcode;
	462	}
	463
	464	/***************************************************/
	465
	466	U_BOOT_CMD(
a095f047	467	mii, 6, 1, do_mii,
2fb2604d	468	"MII utility commands",
a095f047 TJ	469	"device - list available devices\n"
	470	"mii device <devname> - set current device\n"
	471	"mii info <addr> - display MII PHY info\n"
	472	"mii read <addr> <reg> - read MII PHY <addr> register <reg>\n"
	473	"mii write <addr> <reg> <data> - write MII PHY <addr> register <reg>\n"
	474	"mii modify <addr> <reg> <data> <mask> - modify MII PHY <addr> register <reg>\n"
	475	" updating bits identified in <mask>\n"
	476	"mii dump <addr> <reg> - pretty-print <addr> <reg> (0-5 only)\n"
a89c33db	477	"Addr and/or reg may be ranges, e.g. 2-7."
2471111d	478	);