[J-u-boot.git] / board / xilinx / versal / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2018 Xilinx, Inc.
 * Michal Simek <[email protected]>
 */

#include <common.h>
#include <cpu_func.h>
#include <env.h>
#include <fdtdec.h>
#include <init.h>
#include <malloc.h>
#include <time.h>
#include <asm/cache.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include "../common/board.h"

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA_VERSALPL)
static xilinx_desc versalpl = XILINX_VERSAL_DESC;
#endif

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA_VERSALPL)
	fpga_init();
	fpga_add(fpga_xilinx, &versalpl);
#endif

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	debug("iou_switch ctrl div0 %x\n",
	      readl(&crlapb_base->iou_switch_ctrl));

	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
	       &crlapb_base->iou_switch_ctrl);

	/* Global timer init - Program time stamp reference clk */
	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	writel(val, &crlapb_base->timestamp_ref_ctrl);

	debug("ref ctrl 0x%x\n",
	      readl(&crlapb_base->timestamp_ref_ctrl));

	/* Clear reset of timestamp reg */
	writel(0, &crlapb_base->rst_timestamp);

	/*
	 * Program freq register in System counter and
	 * enable system counter.
	 */
	writel(COUNTER_FREQUENCY,
	       &iou_scntr_secure->base_frequency_id_register);

	debug("counter val 0x%x\n",
	      readl(&iou_scntr_secure->base_frequency_id_register));

	writel(IOU_SCNTRS_CONTROL_EN,
	       &iou_scntr_secure->counter_control_register);

	debug("scntrs control 0x%x\n",
	      readl(&iou_scntr_secure->counter_control_register));
	debug("timer 0x%llx\n", get_ticks());
	debug("timer 0x%llx\n", get_ticks());

	return 0;
}

static u8 versal_get_bootmode(void)
{
	u8 bootmode;
	u32 reg = 0;

	reg = readl(&crp_base->boot_mode_usr);

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	return bootmode;
}

int board_late_init(void)
{
	u8 bootmode;
	struct udevice *dev;
	int bootseq = -1;
	int bootseq_len = 0;
	int env_targets_len = 0;
	const char *mode;
	char *new_targets;
	char *env_targets;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	bootmode = versal_get_bootmode();

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "dfu_usb";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "jtag pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
		puts("QSPI_MODE_24\n");
		mode = "xspi0";
		break;
	case QSPI_MODE_32BIT:
		puts("QSPI_MODE_32\n");
		mode = "xspi0";
		break;
	case OSPI_MODE:
		puts("OSPI_MODE\n");
		mode = "xspi0";
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from EMMC but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
		mode = "mmc";
		bootseq = dev->seq;
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1040000", &dev)) {
			puts("Boot from SD0 but without SD0 enabled!\n");
			return -1;
		}
		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from SD1 but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	if (bootseq >= 0) {
		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
		debug("Bootseq len: %x\n", bootseq_len);
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets)
		env_targets_len = strlen(env_targets);

	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
			     bootseq_len);
	if (!new_targets)
		return -ENOMEM;

	if (bootseq >= 0)
		sprintf(new_targets, "%s%x %s", mode, bootseq,
			env_targets ? env_targets : "");
	else
		sprintf(new_targets, "%s %s", mode,
			env_targets ? env_targets : "");

	env_set("boot_targets", new_targets);

	return board_late_init_xilinx();
}

int dram_init_banksize(void)
{
	int ret;

	ret = fdtdec_setup_memory_banksize();
	if (ret)
		return ret;

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

void reset_cpu(ulong addr)
{
}
Commit	Line	Data
ec48b6c9 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2014 - 2018 Xilinx, Inc.
	4	* Michal Simek <[email protected]>
	5	*/
	6
	7	#include <common.h>
9a3b4ceb	8	#include <cpu_func.h>
09140113	9	#include <env.h>
ec48b6c9	10	#include <fdtdec.h>
5255932f	11	#include <init.h>
ec48b6c9	12	#include <malloc.h>
1045315d	13	#include <time.h>
90526e9f	14	#include <asm/cache.h>
ec48b6c9 MS	15	#include <asm/io.h>
ec48b6c9 MS	16	#include <asm/arch/hardware.h>
aef149e9	17	#include <asm/arch/sys_proto.h>
bfd092f9 SDPP	18	#include <dm/device.h>
bfd092f9 SDPP	19	#include <dm/uclass.h>
26e054c9	20	#include <versalpl.h>
80fdef12	21	#include "../common/board.h"
ec48b6c9 MS	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
26e054c9 SDPP	25	#if defined(CONFIG_FPGA_VERSALPL)
	26	static xilinx_desc versalpl = XILINX_VERSAL_DESC;
	27	#endif
	28
ec48b6c9 MS	29	int board_init(void)
	30	{
	31	printf("EL Level:\tEL%d\n", current_el());
	32
26e054c9 SDPP	33	#if defined(CONFIG_FPGA_VERSALPL)
	34	fpga_init();
	35	fpga_add(fpga_xilinx, &versalpl);
	36	#endif
	37
ec48b6c9 MS	38	return 0;
	39	}
	40
	41	int board_early_init_r(void)
	42	{
fb771793 MS	43	u32 val;
	44
	45	if (current_el() != 3)
	46	return 0;
	47
47a766f9 MS	48	debug("iou_switch ctrl div0 %x\n",
	49	readl(&crlapb_base->iou_switch_ctrl));
	50
fb771793	51	writel(IOU_SWITCH_CTRL_CLKACT_BIT \|
47a766f9	52	(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
fb771793 MS	53	&crlapb_base->iou_switch_ctrl);
	54
	55	/* Global timer init - Program time stamp reference clk */
	56	val = readl(&crlapb_base->timestamp_ref_ctrl);
	57	val \|= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	58	writel(val, &crlapb_base->timestamp_ref_ctrl);
	59
	60	debug("ref ctrl 0x%x\n",
	61	readl(&crlapb_base->timestamp_ref_ctrl));
	62
	63	/* Clear reset of timestamp reg */
	64	writel(0, &crlapb_base->rst_timestamp);
	65
	66	/*
	67	* Program freq register in System counter and
	68	* enable system counter.
	69	*/
	70	writel(COUNTER_FREQUENCY,
	71	&iou_scntr_secure->base_frequency_id_register);
	72
	73	debug("counter val 0x%x\n",
	74	readl(&iou_scntr_secure->base_frequency_id_register));
	75
	76	writel(IOU_SCNTRS_CONTROL_EN,
	77	&iou_scntr_secure->counter_control_register);
	78
	79	debug("scntrs control 0x%x\n",
	80	readl(&iou_scntr_secure->counter_control_register));
	81	debug("timer 0x%llx\n", get_ticks());
	82	debug("timer 0x%llx\n", get_ticks());
ec48b6c9 MS	83
	84	return 0;
	85	}
	86
51f6c52e	87	static u8 versal_get_bootmode(void)
bfd092f9	88	{
51f6c52e	89	u8 bootmode;
bfd092f9	90	u32 reg = 0;
51f6c52e MS	91
	92	reg = readl(&crp_base->boot_mode_usr);
	93
	94	if (reg >> BOOT_MODE_ALT_SHIFT)
	95	reg >>= BOOT_MODE_ALT_SHIFT;
	96
	97	bootmode = reg & BOOT_MODES_MASK;
	98
	99	return bootmode;
	100	}
	101
	102	int board_late_init(void)
	103	{
bfd092f9 SDPP	104	u8 bootmode;
	105	struct udevice *dev;
	106	int bootseq = -1;
	107	int bootseq_len = 0;
	108	int env_targets_len = 0;
	109	const char *mode;
	110	char *new_targets;
	111	char *env_targets;
	112
	113	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	114	debug("Saved variables - Skipping\n");
	115	return 0;
	116	}
	117
51f6c52e	118	bootmode = versal_get_bootmode();
bfd092f9 SDPP	119
	120	puts("Bootmode: ");
	121	switch (bootmode) {
f0c16cd6 KR	122	case USB_MODE:
	123	puts("USB_MODE\n");
	124	mode = "dfu_usb";
	125	break;
bfd092f9 SDPP	126	case JTAG_MODE:
bfd092f9 SDPP	127	puts("JTAG_MODE\n");
3d865acb	128	mode = "jtag pxe dhcp";
bfd092f9 SDPP	129	break;
	130	case QSPI_MODE_24BIT:
	131	puts("QSPI_MODE_24\n");
	132	mode = "xspi0";
	133	break;
	134	case QSPI_MODE_32BIT:
	135	puts("QSPI_MODE_32\n");
	136	mode = "xspi0";
	137	break;
	138	case OSPI_MODE:
	139	puts("OSPI_MODE\n");
	140	mode = "xspi0";
	141	break;
	142	case EMMC_MODE:
	143	puts("EMMC_MODE\n");
7c5b7bb1 KR	144	if (uclass_get_device_by_name(UCLASS_MMC,
	145	"sdhci@f1050000", &dev)) {
	146	puts("Boot from EMMC but without SD1 enabled!\n");
	147	return -1;
	148	}
	149	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	150	mode = "mmc";
	151	bootseq = dev->seq;
bfd092f9 SDPP	152	break;
	153	case SD_MODE:
	154	puts("SD_MODE\n");
	155	if (uclass_get_device_by_name(UCLASS_MMC,
	156	"sdhci@f1040000", &dev)) {
	157	puts("Boot from SD0 but without SD0 enabled!\n");
	158	return -1;
	159	}
	160	debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
	161
	162	mode = "mmc";
	163	bootseq = dev->seq;
	164	break;
	165	case SD1_LSHFT_MODE:
	166	puts("LVL_SHFT_");
	167	/* fall through */
	168	case SD_MODE1:
	169	puts("SD_MODE1\n");
	170	if (uclass_get_device_by_name(UCLASS_MMC,
	171	"sdhci@f1050000", &dev)) {
	172	puts("Boot from SD1 but without SD1 enabled!\n");
	173	return -1;
	174	}
	175	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	176
	177	mode = "mmc";
	178	bootseq = dev->seq;
	179	break;
	180	default:
	181	mode = "";
	182	printf("Invalid Boot Mode:0x%x\n", bootmode);
	183	break;
	184	}
	185
	186	if (bootseq >= 0) {
	187	bootseq_len = snprintf(NULL, 0, "%i", bootseq);
	188	debug("Bootseq len: %x\n", bootseq_len);
	189	}
	190
	191	/*
	192	* One terminating char + one byte for space between mode
	193	* and default boot_targets
	194	*/
	195	env_targets = env_get("boot_targets");
	196	if (env_targets)
	197	env_targets_len = strlen(env_targets);
	198
	199	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
	200	bootseq_len);
	201	if (!new_targets)
	202	return -ENOMEM;
	203
	204	if (bootseq >= 0)
	205	sprintf(new_targets, "%s%x %s", mode, bootseq,
	206	env_targets ? env_targets : "");
	207	else
	208	sprintf(new_targets, "%s %s", mode,
	209	env_targets ? env_targets : "");
	210
	211	env_set("boot_targets", new_targets);
	212
80fdef12	213	return board_late_init_xilinx();
bfd092f9 SDPP	214	}
bfd092f9 SDPP	215
ec48b6c9 MS	216	int dram_init_banksize(void)
ec48b6c9 MS	217	{
aef149e9 MS	218	int ret;
	219
	220	ret = fdtdec_setup_memory_banksize();
	221	if (ret)
	222	return ret;
	223
	224	mem_map_fill();
ec48b6c9 MS	225
	226	return 0;
	227	}
	228
	229	int dram_init(void)
	230	{
	231	if (fdtdec_setup_mem_size_base() != 0)
	232	return -EINVAL;
	233
	234	return 0;
	235	}
	236
	237	void reset_cpu(ulong addr)
	238	{
	239	}