[J-u-boot.git] / board / xilinx / versal / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2018 Xilinx, Inc.
 * Michal Simek <[email protected]>
 */

#include <common.h>
#include <cpu_func.h>
#include <fdtdec.h>
#include <init.h>
#include <malloc.h>
#include <time.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <dm/device.h>
#include <dm/uclass.h>
#include <versalpl.h>
#include <linux/sizes.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA_VERSALPL)
static xilinx_desc versalpl = XILINX_VERSAL_DESC;
#endif

int board_init(void)
{
	printf("EL Level:\tEL%d\n", current_el());

#if defined(CONFIG_FPGA_VERSALPL)
	fpga_init();
	fpga_add(fpga_xilinx, &versalpl);
#endif

	return 0;
}

int board_early_init_r(void)
{
	u32 val;

	if (current_el() != 3)
		return 0;

	debug("iou_switch ctrl div0 %x\n",
	      readl(&crlapb_base->iou_switch_ctrl));

	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
	       &crlapb_base->iou_switch_ctrl);

	/* Global timer init - Program time stamp reference clk */
	val = readl(&crlapb_base->timestamp_ref_ctrl);
	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	writel(val, &crlapb_base->timestamp_ref_ctrl);

	debug("ref ctrl 0x%x\n",
	      readl(&crlapb_base->timestamp_ref_ctrl));

	/* Clear reset of timestamp reg */
	writel(0, &crlapb_base->rst_timestamp);

	/*
	 * Program freq register in System counter and
	 * enable system counter.
	 */
	writel(COUNTER_FREQUENCY,
	       &iou_scntr_secure->base_frequency_id_register);

	debug("counter val 0x%x\n",
	      readl(&iou_scntr_secure->base_frequency_id_register));

	writel(IOU_SCNTRS_CONTROL_EN,
	       &iou_scntr_secure->counter_control_register);

	debug("scntrs control 0x%x\n",
	      readl(&iou_scntr_secure->counter_control_register));
	debug("timer 0x%llx\n", get_ticks());
	debug("timer 0x%llx\n", get_ticks());

	return 0;
}

int board_late_init(void)
{
	u32 reg = 0;
	u8 bootmode;
	struct udevice *dev;
	int bootseq = -1;
	int bootseq_len = 0;
	int env_targets_len = 0;
	const char *mode;
	char *new_targets;
	char *env_targets;
	ulong initrd_hi;

	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
		debug("Saved variables - Skipping\n");
		return 0;
	}

	reg = readl(&crp_base->boot_mode_usr);

	if (reg >> BOOT_MODE_ALT_SHIFT)
		reg >>= BOOT_MODE_ALT_SHIFT;

	bootmode = reg & BOOT_MODES_MASK;

	puts("Bootmode: ");
	switch (bootmode) {
	case USB_MODE:
		puts("USB_MODE\n");
		mode = "dfu_usb";
		break;
	case JTAG_MODE:
		puts("JTAG_MODE\n");
		mode = "jtag pxe dhcp";
		break;
	case QSPI_MODE_24BIT:
		puts("QSPI_MODE_24\n");
		mode = "xspi0";
		break;
	case QSPI_MODE_32BIT:
		puts("QSPI_MODE_32\n");
		mode = "xspi0";
		break;
	case OSPI_MODE:
		puts("OSPI_MODE\n");
		mode = "xspi0";
		break;
	case EMMC_MODE:
		puts("EMMC_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from EMMC but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
		mode = "mmc";
		bootseq = dev->seq;
		break;
	case SD_MODE:
		puts("SD_MODE\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1040000", &dev)) {
			puts("Boot from SD0 but without SD0 enabled!\n");
			return -1;
		}
		debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		break;
	case SD1_LSHFT_MODE:
		puts("LVL_SHFT_");
		/* fall through */
	case SD_MODE1:
		puts("SD_MODE1\n");
		if (uclass_get_device_by_name(UCLASS_MMC,
					      "sdhci@f1050000", &dev)) {
			puts("Boot from SD1 but without SD1 enabled!\n");
			return -1;
		}
		debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);

		mode = "mmc";
		bootseq = dev->seq;
		break;
	default:
		mode = "";
		printf("Invalid Boot Mode:0x%x\n", bootmode);
		break;
	}

	if (bootseq >= 0) {
		bootseq_len = snprintf(NULL, 0, "%i", bootseq);
		debug("Bootseq len: %x\n", bootseq_len);
	}

	/*
	 * One terminating char + one byte for space between mode
	 * and default boot_targets
	 */
	env_targets = env_get("boot_targets");
	if (env_targets)
		env_targets_len = strlen(env_targets);

	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
			     bootseq_len);
	if (!new_targets)
		return -ENOMEM;

	if (bootseq >= 0)
		sprintf(new_targets, "%s%x %s", mode, bootseq,
			env_targets ? env_targets : "");
	else
		sprintf(new_targets, "%s %s", mode,
			env_targets ? env_targets : "");

	env_set("boot_targets", new_targets);

	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
	initrd_hi = round_down(initrd_hi, SZ_16M);
	env_set_addr("initrd_high", (void *)initrd_hi);

	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);

	return 0;
}

int dram_init_banksize(void)
{
	int ret;

	ret = fdtdec_setup_memory_banksize();
	if (ret)
		return ret;

	mem_map_fill();

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

void reset_cpu(ulong addr)
{
}
Commit	Line	Data
ec48b6c9 MS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* (C) Copyright 2014 - 2018 Xilinx, Inc.
	4	* Michal Simek <[email protected]>
	5	*/
	6
	7	#include <common.h>
9a3b4ceb	8	#include <cpu_func.h>
ec48b6c9	9	#include <fdtdec.h>
5255932f	10	#include <init.h>
ec48b6c9	11	#include <malloc.h>
1045315d	12	#include <time.h>
ec48b6c9 MS	13	#include <asm/io.h>
ec48b6c9 MS	14	#include <asm/arch/hardware.h>
aef149e9	15	#include <asm/arch/sys_proto.h>
bfd092f9 SDPP	16	#include <dm/device.h>
bfd092f9 SDPP	17	#include <dm/uclass.h>
26e054c9	18	#include <versalpl.h>
085201c2	19	#include <linux/sizes.h>
ec48b6c9 MS	20
	21	DECLARE_GLOBAL_DATA_PTR;
	22
26e054c9 SDPP	23	#if defined(CONFIG_FPGA_VERSALPL)
	24	static xilinx_desc versalpl = XILINX_VERSAL_DESC;
	25	#endif
	26
ec48b6c9 MS	27	int board_init(void)
	28	{
	29	printf("EL Level:\tEL%d\n", current_el());
	30
26e054c9 SDPP	31	#if defined(CONFIG_FPGA_VERSALPL)
	32	fpga_init();
	33	fpga_add(fpga_xilinx, &versalpl);
	34	#endif
	35
ec48b6c9 MS	36	return 0;
	37	}
	38
	39	int board_early_init_r(void)
	40	{
fb771793 MS	41	u32 val;
	42
	43	if (current_el() != 3)
	44	return 0;
	45
47a766f9 MS	46	debug("iou_switch ctrl div0 %x\n",
	47	readl(&crlapb_base->iou_switch_ctrl));
	48
fb771793	49	writel(IOU_SWITCH_CTRL_CLKACT_BIT \|
47a766f9	50	(CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
fb771793 MS	51	&crlapb_base->iou_switch_ctrl);
	52
	53	/* Global timer init - Program time stamp reference clk */
	54	val = readl(&crlapb_base->timestamp_ref_ctrl);
	55	val \|= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
	56	writel(val, &crlapb_base->timestamp_ref_ctrl);
	57
	58	debug("ref ctrl 0x%x\n",
	59	readl(&crlapb_base->timestamp_ref_ctrl));
	60
	61	/* Clear reset of timestamp reg */
	62	writel(0, &crlapb_base->rst_timestamp);
	63
	64	/*
	65	* Program freq register in System counter and
	66	* enable system counter.
	67	*/
	68	writel(COUNTER_FREQUENCY,
	69	&iou_scntr_secure->base_frequency_id_register);
	70
	71	debug("counter val 0x%x\n",
	72	readl(&iou_scntr_secure->base_frequency_id_register));
	73
	74	writel(IOU_SCNTRS_CONTROL_EN,
	75	&iou_scntr_secure->counter_control_register);
	76
	77	debug("scntrs control 0x%x\n",
	78	readl(&iou_scntr_secure->counter_control_register));
	79	debug("timer 0x%llx\n", get_ticks());
	80	debug("timer 0x%llx\n", get_ticks());
ec48b6c9 MS	81
	82	return 0;
	83	}
	84
bfd092f9 SDPP	85	int board_late_init(void)
	86	{
	87	u32 reg = 0;
	88	u8 bootmode;
	89	struct udevice *dev;
	90	int bootseq = -1;
	91	int bootseq_len = 0;
	92	int env_targets_len = 0;
	93	const char *mode;
	94	char *new_targets;
	95	char *env_targets;
085201c2	96	ulong initrd_hi;
bfd092f9 SDPP	97
	98	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
	99	debug("Saved variables - Skipping\n");
	100	return 0;
	101	}
	102
	103	reg = readl(&crp_base->boot_mode_usr);
	104
	105	if (reg >> BOOT_MODE_ALT_SHIFT)
	106	reg >>= BOOT_MODE_ALT_SHIFT;
	107
	108	bootmode = reg & BOOT_MODES_MASK;
	109
	110	puts("Bootmode: ");
	111	switch (bootmode) {
f0c16cd6 KR	112	case USB_MODE:
	113	puts("USB_MODE\n");
	114	mode = "dfu_usb";
	115	break;
bfd092f9 SDPP	116	case JTAG_MODE:
bfd092f9 SDPP	117	puts("JTAG_MODE\n");
3d865acb	118	mode = "jtag pxe dhcp";
bfd092f9 SDPP	119	break;
	120	case QSPI_MODE_24BIT:
	121	puts("QSPI_MODE_24\n");
	122	mode = "xspi0";
	123	break;
	124	case QSPI_MODE_32BIT:
	125	puts("QSPI_MODE_32\n");
	126	mode = "xspi0";
	127	break;
	128	case OSPI_MODE:
	129	puts("OSPI_MODE\n");
	130	mode = "xspi0";
	131	break;
	132	case EMMC_MODE:
	133	puts("EMMC_MODE\n");
7c5b7bb1 KR	134	if (uclass_get_device_by_name(UCLASS_MMC,
	135	"sdhci@f1050000", &dev)) {
	136	puts("Boot from EMMC but without SD1 enabled!\n");
	137	return -1;
	138	}
	139	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	140	mode = "mmc";
	141	bootseq = dev->seq;
bfd092f9 SDPP	142	break;
	143	case SD_MODE:
	144	puts("SD_MODE\n");
	145	if (uclass_get_device_by_name(UCLASS_MMC,
	146	"sdhci@f1040000", &dev)) {
	147	puts("Boot from SD0 but without SD0 enabled!\n");
	148	return -1;
	149	}
	150	debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
	151
	152	mode = "mmc";
	153	bootseq = dev->seq;
	154	break;
	155	case SD1_LSHFT_MODE:
	156	puts("LVL_SHFT_");
	157	/* fall through */
	158	case SD_MODE1:
	159	puts("SD_MODE1\n");
	160	if (uclass_get_device_by_name(UCLASS_MMC,
	161	"sdhci@f1050000", &dev)) {
	162	puts("Boot from SD1 but without SD1 enabled!\n");
	163	return -1;
	164	}
	165	debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
	166
	167	mode = "mmc";
	168	bootseq = dev->seq;
	169	break;
	170	default:
	171	mode = "";
	172	printf("Invalid Boot Mode:0x%x\n", bootmode);
	173	break;
	174	}
	175
	176	if (bootseq >= 0) {
	177	bootseq_len = snprintf(NULL, 0, "%i", bootseq);
	178	debug("Bootseq len: %x\n", bootseq_len);
	179	}
	180
	181	/*
	182	* One terminating char + one byte for space between mode
	183	* and default boot_targets
	184	*/
	185	env_targets = env_get("boot_targets");
	186	if (env_targets)
	187	env_targets_len = strlen(env_targets);
	188
	189	new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
	190	bootseq_len);
	191	if (!new_targets)
	192	return -ENOMEM;
	193
	194	if (bootseq >= 0)
	195	sprintf(new_targets, "%s%x %s", mode, bootseq,
	196	env_targets ? env_targets : "");
	197	else
	198	sprintf(new_targets, "%s %s", mode,
	199	env_targets ? env_targets : "");
	200
	201	env_set("boot_targets", new_targets);
	202
085201c2 SDPP	203	initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
	204	initrd_hi = round_down(initrd_hi, SZ_16M);
	205	env_set_addr("initrd_high", (void *)initrd_hi);
	206
53c69dec KR	207	env_set_hex("script_offset_f", CONFIG_BOOT_SCRIPT_OFFSET);
53c69dec KR	208
bfd092f9 SDPP	209	return 0;
	210	}
	211
ec48b6c9 MS	212	int dram_init_banksize(void)
ec48b6c9 MS	213	{
aef149e9 MS	214	int ret;
	215
	216	ret = fdtdec_setup_memory_banksize();
	217	if (ret)
	218	return ret;
	219
	220	mem_map_fill();
ec48b6c9 MS	221
	222	return 0;
	223	}
	224
	225	int dram_init(void)
	226	{
	227	if (fdtdec_setup_mem_size_base() != 0)
	228	return -EINVAL;
	229
	230	return 0;
	231	}
	232
	233	void reset_cpu(ulong addr)
	234	{
	235	}