[J-u-boot.git] / arch / arm / mach-omap2 / omap3 / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <[email protected]>
 *      Shashi Ranjan <[email protected]>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <[email protected]>
 *      Syed Mohammed Khasim <[email protected]>
 *
 */
#include <common.h>
#include <command.h>
#include <dm.h>
#include <init.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/gpio.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>

/* Declarations */
extern omap3_sysinfo sysinfo;
#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_invalidate_l2_cache_secure(void);
#endif

#if CONFIG_IS_ENABLED(DM_GPIO)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_platdata omap34xx_gpio[] = {
	{ 0, OMAP34XX_GPIO1_BASE },
	{ 1, OMAP34XX_GPIO2_BASE },
	{ 2, OMAP34XX_GPIO3_BASE },
	{ 3, OMAP34XX_GPIO4_BASE },
	{ 4, OMAP34XX_GPIO5_BASE },
	{ 5, OMAP34XX_GPIO6_BASE },
};

U_BOOT_DEVICES(omap34xx_gpios) = {
	{ "gpio_omap", &omap34xx_gpio[0] },
	{ "gpio_omap", &omap34xx_gpio[1] },
	{ "gpio_omap", &omap34xx_gpio[2] },
	{ "gpio_omap", &omap34xx_gpio[3] },
	{ "gpio_omap", &omap34xx_gpio[4] },
	{ "gpio_omap", &omap34xx_gpio[5] },
};
#endif
#else

static const struct gpio_bank gpio_bank_34xx[6] = {
	{ (void *)OMAP34XX_GPIO1_BASE },
	{ (void *)OMAP34XX_GPIO2_BASE },
	{ (void *)OMAP34XX_GPIO3_BASE },
	{ (void *)OMAP34XX_GPIO4_BASE },
	{ (void *)OMAP34XX_GPIO5_BASE },
	{ (void *)OMAP34XX_GPIO6_BASE },
};

const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;

#endif

/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
	struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit(void)
{
	unsigned long i;

	/* configure non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory(void)
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

void early_system_init(void)
{
	hw_data_init();
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	watchdog_init();
	early_system_init();

	try_unlock_memory();

#ifndef CONFIG_SYS_L2CACHE_OFF
	/* Invalidate L2-cache from secure mode */
	omap3_invalidate_l2_cache_secure();
#endif

	set_muxconf_regs();
	sdelay(100);

	prcm_init();

	per_clocks_enable();

#ifdef CONFIG_USB_EHCI_OMAP
	ehci_clocks_enable();
#endif
}

#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
	early_system_init();
	mem_init();
	/*
	* Save the boot parameters passed from romcode.
	* We cannot delay the saving further than this,
	* to prevent overwrites.
	*/
	save_omap_boot_params();
}
#endif

/*
 * Routine: misc_init_r
 * Description: A basic misc_init_r that just displays the die ID
 */
int __weak misc_init_r(void)
{
	omap_die_id_display();

	return 0;
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
static void wait_for_command_complete(struct watchdog *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	setbits_le32(&prcm_base->fclken_wkup, 0x20);
	setbits_le32(&prcm_base->iclken_wkup, 0x20);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
			 char *const argv[])
{
	int hw, strength = 1;

	if (argc < 2 || argc > 3)
		goto usage;

	if (strncmp(argv[1], "hw", 2) == 0) {
		hw = 1;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "bch16", 5) == 0)
				strength = 16;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else if (strncmp(argv[1], "sw", 2) == 0) {
		hw = 0;
		if (argc == 3) {
			if (strncmp(argv[2], "bch8", 4) == 0)
				strength = 8;
			else if (strncmp(argv[2], "hamming", 7) != 0)
				goto usage;
		}
	} else {
		goto usage;
	}

	return -omap_nand_switch_ecc(hw, strength);

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 3, 1,	do_switch_ecc,
	"switch OMAP3 NAND ECC calculation algorithm",
	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
	" and 8-bit/16-bit BCH\n"
	"                           ecc calculation (second parameter may"
	" be omitted).\n"
	"nandecc sw               - Switch to NAND software ecc algorithm."
);

#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */

#ifdef CONFIG_DISPLAY_BOARDINFO
/**
 * Print board information
 */
int checkboard (void)
{
	char *mem_s ;

	if (is_mem_sdr())
		mem_s = "mSDR";
	else
		mem_s = "LPDDR";

	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
			sysinfo.nand_string);

	return 0;
}
#endif	/* CONFIG_DISPLAY_BOARDINFO */

static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
{
	u32 i, num_params = *parameters;
	u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;

	/*
	 * copy the parameters to an un-cached area to avoid coherency
	 * issues
	 */
	for (i = 0; i < num_params; i++) {
		__raw_writel(*parameters, sram_scratch_space);
		parameters++;
		sram_scratch_space++;
	}

	/* Now make the PPA call */
	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
}

void __weak omap3_set_aux_cr_secure(u32 acr)
{
	struct emu_hal_params emu_romcode_params;

	emu_romcode_params.num_params = 1;
	emu_romcode_params.param1 = acr;
	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
			       (u32 *)&emu_romcode_params);
}

void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
				 u32 cpu_rev_comb, u32 cpu_variant,
				 u32 cpu_rev)
{
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);

	/* L2 Cache Auxiliary Control Register is not banked */
}

void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
			  u32 cpu_variant, u32 cpu_rev)
{
	/* Write ACR - affects secure banked bits */
	if (get_device_type() == GP_DEVICE)
		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	else
		omap3_set_aux_cr_secure(acr);

	/* Write ACR - affects non-secure banked bits - some erratas need it */
	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
}


#ifndef CONFIG_SYS_L2CACHE_OFF
static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
{
	u32 acr;

	/* Read ACR */
	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	acr &= ~clear_bits;
	acr |= set_bits;
	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);

}

/* Invalidate the entire L2 cache from secure mode */
static void omap3_invalidate_l2_cache_secure(void)
{
	if (get_device_type() == GP_DEVICE) {
		omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
	} else {
		struct emu_hal_params emu_romcode_params;
		emu_romcode_params.num_params = 1;
		emu_romcode_params.param1 = 0;
		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
				       (u32 *)&emu_romcode_params);
	}
}

void v7_outer_cache_enable(void)
{

	/*
	 * Set L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in setting both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0x2, 0);
}

void omap3_outer_cache_disable(void)
{
	/*
	 * Clear L2EN
	 * On some revisions L2EN bit is banked on some revisions it's not
	 * No harm in clearing both banked bits(in fact this is required
	 * by an erratum)
	 */
	omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
91eee546 DB	2	/*
	3	*
	4	* Common board functions for OMAP3 based boards.
	5	*
	6	* (C) Copyright 2004-2008
	7	* Texas Instruments, <www.ti.com>
	8	*
	9	* Author :
	10	* Sunil Kumar <[email protected]>
	11	* Shashi Ranjan <[email protected]>
	12	*
	13	* Derived from Beagle Board and 3430 SDP code by
	14	* Richard Woodruff <[email protected]>
	15	* Syed Mohammed Khasim <[email protected]>
	16	*
91eee546 DB	17	*/
91eee546 DB	18	#include <common.h>
09140113	19	#include <command.h>
b3f4ca11	20	#include <dm.h>
691d719d	21	#include <init.h>
47f7bcae	22	#include <spl.h>
91eee546 DB	23	#include <asm/io.h>
	24	#include <asm/arch/sys_proto.h>
	25	#include <asm/arch/mem.h>
06e758e7	26	#include <asm/cache.h>
45bf0585	27	#include <asm/armv7.h>
b3f4ca11	28	#include <asm/gpio.h>
bb085b87	29	#include <asm/omap_common.h>
8a87a3d7	30	#include <linux/compiler.h>
91eee546	31
45bf0585	32	/* Declarations */
91eee546	33	extern omap3_sysinfo sysinfo;
57f588be	34	#ifndef CONFIG_SYS_L2CACHE_OFF
45bf0585	35	static void omap3_invalidate_l2_cache_secure(void);
57f588be	36	#endif
91eee546	37
bcee8d67	38	#if CONFIG_IS_ENABLED(DM_GPIO)
33ac2b56 AF	39	#if !CONFIG_IS_ENABLED(OF_CONTROL)
33ac2b56 AF	40	/* Manually initialize GPIO banks when OF_CONTROL doesn't */
b3f4ca11	41	static const struct omap_gpio_platdata omap34xx_gpio[] = {
0a9e3405 TR	42	{ 0, OMAP34XX_GPIO1_BASE },
	43	{ 1, OMAP34XX_GPIO2_BASE },
	44	{ 2, OMAP34XX_GPIO3_BASE },
	45	{ 3, OMAP34XX_GPIO4_BASE },
	46	{ 4, OMAP34XX_GPIO5_BASE },
	47	{ 5, OMAP34XX_GPIO6_BASE },
b3f4ca11 SG	48	};
b3f4ca11 SG	49
44913aa5	50	U_BOOT_DEVICES(omap34xx_gpios) = {
b3f4ca11 SG	51	{ "gpio_omap", &omap34xx_gpio[0] },
	52	{ "gpio_omap", &omap34xx_gpio[1] },
	53	{ "gpio_omap", &omap34xx_gpio[2] },
	54	{ "gpio_omap", &omap34xx_gpio[3] },
	55	{ "gpio_omap", &omap34xx_gpio[4] },
	56	{ "gpio_omap", &omap34xx_gpio[5] },
	57	};
33ac2b56	58	#endif
b3f4ca11 SG	59	#else
b3f4ca11 SG	60
25223a68	61	static const struct gpio_bank gpio_bank_34xx[6] = {
0a9e3405 TR	62	{ (void *)OMAP34XX_GPIO1_BASE },
	63	{ (void *)OMAP34XX_GPIO2_BASE },
	64	{ (void *)OMAP34XX_GPIO3_BASE },
	65	{ (void *)OMAP34XX_GPIO4_BASE },
	66	{ (void *)OMAP34XX_GPIO5_BASE },
	67	{ (void *)OMAP34XX_GPIO6_BASE },
25223a68 A	68	};
	69
	70	const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
	71
b3f4ca11 SG	72	#endif
b3f4ca11 SG	73
91eee546 DB	74	/******************************************************************************
	75	* Routine: secure_unlock
	76	* Description: Setup security registers for access
	77	* (GP Device only)
	78	*****************************************************************************/
	79	void secure_unlock_mem(void)
	80	{
97a099ea DB	81	struct pm pm_rt_ape_base = (struct pm )PM_RT_APE_BASE_ADDR_ARM;
	82	struct pm pm_gpmc_base = (struct pm )PM_GPMC_BASE_ADDR_ARM;
	83	struct pm pm_ocm_ram_base = (struct pm )PM_OCM_RAM_BASE_ADDR_ARM;
	84	struct pm pm_iva2_base = (struct pm )PM_IVA2_BASE_ADDR_ARM;
	85	struct sms sms_base = (struct sms )OMAP34XX_SMS_BASE;
91eee546 DB	86
	87	/* Protection Module Register Target APE (PM_RT) */
	88	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	89	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	90	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	91	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
	92
	93	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	94	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	95	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
	96
	97	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	98	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	99	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	100	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
	101
	102	/* IVA Changes */
	103	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	104	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	105	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
	106
	107	/* SDRC region 0 public */
	108	writel(UNLOCK_1, &sms_base->rg_att0);
	109	}
	110
	111	/******************************************************************************
	112	* Routine: secureworld_exit()
	113	* Description: If chip is EMU and boot type is external
	114	* configure secure registers and exit secure world
	115	* general use.
	116	*****************************************************************************/
fd3f401b	117	void secureworld_exit(void)
91eee546 DB	118	{
	119	unsigned long i;
	120
a4958313	121	/* configure non-secure access control register */
91eee546 DB	122	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	123	/* enabling co-processor CP10 and CP11 accesses in NS world */
	124	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	125	/*
	126	* allow allocation of locked TLBs and L2 lines in NS world
	127	* allow use of PLE registers in NS world also
	128	*/
	129	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	130	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
	131
	132	/* Enable ASA in ACR register */
	133	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	134	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	135	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
	136
	137	/* Exiting secure world */
	138	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	139	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	140	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
	141	}
	142
91eee546 DB	143	/******************************************************************************
	144	* Routine: try_unlock_sram()
	145	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
	146	* general use.
	147	*****************************************************************************/
fd3f401b	148	void try_unlock_memory(void)
91eee546 DB	149	{
	150	int mode;
	151	int in_sdram = is_running_in_sdram();
	152
	153	/*
	154	* if GP device unlock device SRAM for general use
	155	* secure code breaks for Secure/Emulation device - HS/E/T
	156	*/
	157	mode = get_device_type();
	158	if (mode == GP_DEVICE)
	159	secure_unlock_mem();
	160
	161	/*
	162	* If device is EMU and boot is XIP external booting
	163	* Unlock firewalls and disable L2 and put chip
	164	* out of secure world
	165	*
	166	* Assuming memories are unlocked by the demon who put us in SDRAM
	167	*/
	168	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	169	&& (!in_sdram)) {
	170	secure_unlock_mem();
	171	secureworld_exit();
	172	}
	173
	174	return;
	175	}
	176
00bbe96e SP	177	void early_system_init(void)
	178	{
	179	hw_data_init();
	180	}
	181
91eee546 DB	182	/******************************************************************************
	183	* Routine: s_init
	184	* Description: Does early system init of muxing and clocks.
	185	* - Called path is with SRAM stack.
	186	*****************************************************************************/
	187	void s_init(void)
	188	{
91eee546	189	watchdog_init();
00bbe96e	190	early_system_init();
91eee546 DB	191
	192	try_unlock_memory();
	193
45bf0585 A	194	#ifndef CONFIG_SYS_L2CACHE_OFF
	195	/* Invalidate L2-cache from secure mode */
	196	omap3_invalidate_l2_cache_secure();
91eee546	197	#endif
91eee546 DB	198
91eee546 DB	199	set_muxconf_regs();
86623add	200	sdelay(100);
91eee546 DB	201
	202	prcm_init();
	203
	204	per_clocks_enable();
	205
95f87910 G	206	#ifdef CONFIG_USB_EHCI_OMAP
	207	ehci_clocks_enable();
	208	#endif
7ae8350f	209	}
95f87910	210
7ae8350f SG	211	#ifdef CONFIG_SPL_BUILD
	212	void board_init_f(ulong dummy)
	213	{
00bbe96e	214	early_system_init();
7ae8350f	215	mem_init();
c3bec547 AF	216	/*
	217	* Save the boot parameters passed from romcode.
	218	* We cannot delay the saving further than this,
	219	* to prevent overwrites.
	220	*/
	221	save_omap_boot_params();
91eee546	222	}
7ae8350f	223	#endif
91eee546	224
8a87a3d7 TR	225	/*
	226	* Routine: misc_init_r
	227	* Description: A basic misc_init_r that just displays the die ID
	228	*/
	229	int __weak misc_init_r(void)
	230	{
679f82c3	231	omap_die_id_display();
8a87a3d7 TR	232
	233	return 0;
	234	}
	235
91eee546 DB	236	/******************************************************************************
	237	* Routine: wait_for_command_complete
	238	* Description: Wait for posting to finish on watchdog
	239	*****************************************************************************/
98431d58	240	static void wait_for_command_complete(struct watchdog *wd_base)
91eee546 DB	241	{
	242	int pending = 1;
	243	do {
	244	pending = readl(&wd_base->wwps);
	245	} while (pending);
	246	}
	247
	248	/******************************************************************************
	249	* Routine: watchdog_init
	250	* Description: Shut down watch dogs
	251	*****************************************************************************/
	252	void watchdog_init(void)
	253	{
97a099ea DB	254	struct watchdog wd2_base = (struct watchdog )WD2_BASE;
97a099ea DB	255	struct prcm prcm_base = (struct prcm )PRCM_BASE;
91eee546 DB	256
	257	/*
	258	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	259	* either taken care of by ROM (HS/EMU) or not accessible (GP).
	260	* We need to take care of WD2-MPU or take a PRCM reset. WD3
	261	* should not be running and does not generate a PRCM reset.
	262	*/
	263
e7300f46 WD	264	setbits_le32(&prcm_base->fclken_wkup, 0x20);
e7300f46 WD	265	setbits_le32(&prcm_base->iclken_wkup, 0x20);
91eee546 DB	266	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
	267
	268	writel(WD_UNLOCK1, &wd2_base->wspr);
	269	wait_for_command_complete(wd2_base);
	270	writel(WD_UNLOCK2, &wd2_base->wspr);
	271	}
	272
91eee546 DB	273	/******************************************************************************
	274	* Dummy function to handle errors for EABI incompatibility
	275	*****************************************************************************/
	276	void abort(void)
	277	{
	278	}
	279
bb085b87	280	#if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
91eee546 DB	281	/******************************************************************************
	282	* OMAP3 specific command to switch between NAND HW and SW ecc
	283	*****************************************************************************/
09140113 SG	284	static int do_switch_ecc(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	285	char *const argv[])
91eee546	286	{
50075153 LM	287	int hw, strength = 1;
50075153 LM	288
da634ae3	289	if (argc < 2 \|\| argc > 3)
91eee546	290	goto usage;
da634ae3 AB	291
da634ae3 AB	292	if (strncmp(argv[1], "hw", 2) == 0) {
50075153 LM	293	hw = 1;
	294	if (argc == 3) {
	295	if (strncmp(argv[2], "bch8", 4) == 0)
	296	strength = 8;
3a504d96	297	else if (strncmp(argv[2], "bch16", 5) == 0)
50075153 LM	298	strength = 16;
50075153 LM	299	else if (strncmp(argv[2], "hamming", 7) != 0)
da634ae3 AB	300	goto usage;
	301	}
	302	} else if (strncmp(argv[1], "sw", 2) == 0) {
50075153 LM	303	hw = 0;
	304	if (argc == 3) {
	305	if (strncmp(argv[2], "bch8", 4) == 0)
	306	strength = 8;
	307	else if (strncmp(argv[2], "hamming", 7) != 0)
b050898e AC	308	goto usage;
b050898e AC	309	}
da634ae3	310	} else {
91eee546	311	goto usage;
da634ae3	312	}
91eee546	313
50075153	314	return -omap_nand_switch_ecc(hw, strength);
91eee546 DB	315
91eee546 DB	316	usage:
36003268	317	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	318	return 1;
	319	}
	320
	321	U_BOOT_CMD(
da634ae3	322	nandecc, 3, 1, do_switch_ecc,
a93c92cd	323	"switch OMAP3 NAND ECC calculation algorithm",
3a504d96 HS	324	"hw [hamming\|bch8\|bch16] - Switch between NAND hardware 1-bit hamming"
3a504d96 HS	325	" and 8-bit/16-bit BCH\n"
da634ae3 AB	326	" ecc calculation (second parameter may"
	327	" be omitted).\n"
	328	"nandecc sw - Switch to NAND software ecc algorithm."
a89c33db	329	);
91eee546	330
bb085b87	331	#endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
6a6b62e3 SP	332
	333	#ifdef CONFIG_DISPLAY_BOARDINFO
	334	/**
	335	* Print board information
	336	*/
	337	int checkboard (void)
	338	{
	339	char *mem_s ;
	340
	341	if (is_mem_sdr())
	342	mem_s = "mSDR";
	343	else
	344	mem_s = "LPDDR";
	345
	346	printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
	347	sysinfo.nand_string);
	348
	349	return 0;
	350	}
	351	#endif /* CONFIG_DISPLAY_BOARDINFO */
45bf0585 A	352
	353	static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
	354	{
	355	u32 i, num_params = *parameters;
	356	u32 sram_scratch_space = (u32 )OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
	357
	358	/*
	359	* copy the parameters to an un-cached area to avoid coherency
	360	* issues
	361	*/
	362	for (i = 0; i < num_params; i++) {
	363	__raw_writel(*parameters, sram_scratch_space);
	364	parameters++;
	365	sram_scratch_space++;
	366	}
	367
	368	/* Now make the PPA call */
	369	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
	370	}
	371
cdef0b3f	372	void __weak omap3_set_aux_cr_secure(u32 acr)
45bf0585	373	{
cdef0b3f NM	374	struct emu_hal_params emu_romcode_params;
	375
	376	emu_romcode_params.num_params = 1;
	377	emu_romcode_params.param1 = acr;
	378	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	379	(u32 *)&emu_romcode_params);
45bf0585 A	380	}
45bf0585 A	381
19a75b8c SS	382	void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
	383	u32 cpu_rev_comb, u32 cpu_variant,
	384	u32 cpu_rev)
	385	{
	386	if (get_device_type() == GP_DEVICE)
	387	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_L2ACR, l2auxctrl);
	388
	389	/* L2 Cache Auxiliary Control Register is not banked */
	390	}
	391
cdef0b3f NM	392	void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
cdef0b3f NM	393	u32 cpu_variant, u32 cpu_rev)
45bf0585	394	{
cdef0b3f NM	395	/* Write ACR - affects secure banked bits */
	396	if (get_device_type() == GP_DEVICE)
	397	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
	398	else
	399	omap3_set_aux_cr_secure(acr);
c6f90e14	400
cdef0b3f NM	401	/* Write ACR - affects non-secure banked bits - some erratas need it */
cdef0b3f NM	402	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
45bf0585 A	403	}
45bf0585 A	404
cdef0b3f	405
45bf0585	406	#ifndef CONFIG_SYS_L2CACHE_OFF
57f588be TR	407	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
	408	{
	409	u32 acr;
	410
	411	/* Read ACR */
	412	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
	413	acr &= ~clear_bits;
	414	acr \|= set_bits;
cdef0b3f	415	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
57f588be	416
57f588be TR	417	}
57f588be TR	418
45bf0585 A	419	/* Invalidate the entire L2 cache from secure mode */
	420	static void omap3_invalidate_l2_cache_secure(void)
	421	{
	422	if (get_device_type() == GP_DEVICE) {
49ec9490	423	omap_smc1(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
45bf0585 A	424	} else {
	425	struct emu_hal_params emu_romcode_params;
	426	emu_romcode_params.num_params = 1;
	427	emu_romcode_params.param1 = 0;
	428	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
	429	(u32 *)&emu_romcode_params);
	430	}
	431	}
	432
	433	void v7_outer_cache_enable(void)
	434	{
45bf0585 A	435
45bf0585 A	436	/*
cdef0b3f	437	* Set L2EN
45bf0585 A	438	* On some revisions L2EN bit is banked on some revisions it's not
	439	* No harm in setting both banked bits(in fact this is required
	440	* by an erratum)
	441	*/
	442	omap3_update_aux_cr(0x2, 0);
	443	}
	444
f1f2c3ca	445	void omap3_outer_cache_disable(void)
45bf0585	446	{
45bf0585	447	/*
cdef0b3f	448	* Clear L2EN
45bf0585 A	449	* On some revisions L2EN bit is banked on some revisions it's not
	450	* No harm in clearing both banked bits(in fact this is required
	451	* by an erratum)
	452	*/
	453	omap3_update_aux_cr(0, 0x2);
	454	}
e3fe6257	455	#endif /* !CONFIG_SYS_L2CACHE_OFF */