[J-u-boot.git] / cpu / arm_cortexa8 / omap3 / board.c

/*
 *
 * Common board functions for OMAP3 based boards.
 *
 * (C) Copyright 2004-2008
 * Texas Instruments, <www.ti.com>
 *
 * Author :
 *      Sunil Kumar <[email protected]>
 *      Shashi Ranjan <[email protected]>
 *
 * Derived from Beagle Board and 3430 SDP code by
 *      Richard Woodruff <[email protected]>
 *      Syed Mohammed Khasim <[email protected]>
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>

extern omap3_sysinfo sysinfo;

/******************************************************************************
 * Routine: delay
 * Description: spinning delay to use before udelay works
 *****************************************************************************/
static inline void delay(unsigned long loops)
{
	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
			  "bne 1b":"=r" (loops):"0"(loops));
}

/******************************************************************************
 * Routine: secure_unlock
 * Description: Setup security registers for access
 *              (GP Device only)
 *****************************************************************************/
void secure_unlock_mem(void)
{
	pm_t *pm_rt_ape_base = (pm_t *)PM_RT_APE_BASE_ADDR_ARM;
	pm_t *pm_gpmc_base = (pm_t *)PM_GPMC_BASE_ADDR_ARM;
	pm_t *pm_ocm_ram_base = (pm_t *)PM_OCM_RAM_BASE_ADDR_ARM;
	pm_t *pm_iva2_base = (pm_t *)PM_IVA2_BASE_ADDR_ARM;
	sms_t *sms_base = (sms_t *)OMAP34XX_SMS_BASE;

	/* Protection Module Register Target APE (PM_RT) */
	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);

	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);

	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);

	/* IVA Changes */
	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);

	/* SDRC region 0 public */
	writel(UNLOCK_1, &sms_base->rg_att0);
}

/******************************************************************************
 * Routine: secureworld_exit()
 * Description: If chip is EMU and boot type is external
 *		configure secure registers and exit secure world
 *              general use.
 *****************************************************************************/
void secureworld_exit()
{
	unsigned long i;

	/* configrue non-secure access control register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
	/* enabling co-processor CP10 and CP11 accesses in NS world */
	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
	/*
	 * allow allocation of locked TLBs and L2 lines in NS world
	 * allow use of PLE registers in NS world also
	 */
	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));

	/* Enable ASA in ACR register */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));

	/* Exiting secure world */
	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
}

/******************************************************************************
 * Routine: setup_auxcr()
 * Description: Write to AuxCR desired value using SMI.
 *              general use.
 *****************************************************************************/
void setup_auxcr()
{
	unsigned long i;
	volatile unsigned int j;
	/* Save r0, r12 and restore them after usage */
	__asm__ __volatile__("mov %0, r12":"=r"(j));
	__asm__ __volatile__("mov %0, r0":"=r"(i));

	/*
	 * GP Device ROM code API usage here
	 * r12 = AUXCR Write function and r0 value
	 */
	__asm__ __volatile__("mov r12, #0x3");
	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
	/* Enabling ASA */
	__asm__ __volatile__("orr r0, r0, #0x10");
	/* Enable L1NEON */
	__asm__ __volatile__("orr r0, r0, #1 << 5");
	/* SMI instruction to call ROM Code API */
	__asm__ __volatile__(".word 0xE1600070");
	__asm__ __volatile__("mov r0, %0":"=r"(i));
	__asm__ __volatile__("mov r12, %0":"=r"(j));
}

/******************************************************************************
 * Routine: try_unlock_sram()
 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
 *              general use.
 *****************************************************************************/
void try_unlock_memory()
{
	int mode;
	int in_sdram = is_running_in_sdram();

	/*
	 * if GP device unlock device SRAM for general use
	 * secure code breaks for Secure/Emulation device - HS/E/T
	 */
	mode = get_device_type();
	if (mode == GP_DEVICE)
		secure_unlock_mem();

	/*
	 * If device is EMU and boot is XIP external booting
	 * Unlock firewalls and disable L2 and put chip
	 * out of secure world
	 *
	 * Assuming memories are unlocked by the demon who put us in SDRAM
	 */
	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
	    && (!in_sdram)) {
		secure_unlock_mem();
		secureworld_exit();
	}

	return;
}

/******************************************************************************
 * Routine: s_init
 * Description: Does early system init of muxing and clocks.
 *              - Called path is with SRAM stack.
 *****************************************************************************/
void s_init(void)
{
	int in_sdram = is_running_in_sdram();

	watchdog_init();

	try_unlock_memory();

	/*
	 * Right now flushing at low MPU speed.
	 * Need to move after clock init
	 */
	v7_flush_dcache_all(get_device_type());
#ifndef CONFIG_ICACHE_OFF
	icache_enable();
#endif

#ifdef CONFIG_L2_OFF
	l2cache_disable();
#else
	l2cache_enable();
#endif
	/*
	 * Writing to AuxCR in U-boot using SMI for GP DEV
	 * Currently SMI in Kernel on ES2 devices seems to have an issue
	 * Once that is resolved, we can postpone this config to kernel
	 */
	if (get_device_type() == GP_DEVICE)
		setup_auxcr();

	set_muxconf_regs();
	delay(100);

	prcm_init();

	per_clocks_enable();

	if (!in_sdram)
		sdrc_init();
}

/******************************************************************************
 * Routine: wait_for_command_complete
 * Description: Wait for posting to finish on watchdog
 *****************************************************************************/
void wait_for_command_complete(watchdog_t *wd_base)
{
	int pending = 1;
	do {
		pending = readl(&wd_base->wwps);
	} while (pending);
}

/******************************************************************************
 * Routine: watchdog_init
 * Description: Shut down watch dogs
 *****************************************************************************/
void watchdog_init(void)
{
	watchdog_t *wd2_base = (watchdog_t *)WD2_BASE;
	prcm_t *prcm_base = (prcm_t *)PRCM_BASE;

	/*
	 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
	 * either taken care of by ROM (HS/EMU) or not accessible (GP).
	 * We need to take care of WD2-MPU or take a PRCM reset. WD3
	 * should not be running and does not generate a PRCM reset.
	 */

	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);

	writel(WD_UNLOCK1, &wd2_base->wspr);
	wait_for_command_complete(wd2_base);
	writel(WD_UNLOCK2, &wd2_base->wspr);
}

/******************************************************************************
 * Routine: dram_init
 * Description: sets uboots idea of sdram size
 *****************************************************************************/
int dram_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int size0 = 0, size1 = 0;
	u32 btype;

	btype = get_board_type();

	display_board_info(btype);

	/*
	 * If a second bank of DDR is attached to CS1 this is
	 * where it can be started.  Early init code will init
	 * memory on CS0.
	 */
	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
		do_sdrc_init(CS1, NOT_EARLY);
		make_cs1_contiguous();
	}

	size0 = get_sdr_cs_size(CS0);
	size1 = get_sdr_cs_size(CS1);

	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = size0;
	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
	gd->bd->bi_dram[1].size = size1;

	return 0;
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void raise(void)
{
}

/******************************************************************************
 * Dummy function to handle errors for EABI incompatibility
 *****************************************************************************/
void abort(void)
{
}

#ifdef CONFIG_NAND_OMAP_GPMC
/******************************************************************************
 * OMAP3 specific command to switch between NAND HW and SW ecc
 *****************************************************************************/
static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
	if (argc != 2)
		goto usage;
	if (strncmp(argv[1], "hw", 2) == 0)
		omap_nand_switch_ecc(1);
	else if (strncmp(argv[1], "sw", 2) == 0)
		omap_nand_switch_ecc(0);
	else
		goto usage;

	return 0;

usage:
	printf ("Usage: nandecc %s\n", cmdtp->usage);
	return 1;
}

U_BOOT_CMD(
	nandecc, 2, 1,	do_switch_ecc,
	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
	);

#endif /* CONFIG_NAND_OMAP_GPMC */
Commit	Line	Data
91eee546 DB	1	/*
	2	*
	3	* Common board functions for OMAP3 based boards.
	4	*
	5	* (C) Copyright 2004-2008
	6	* Texas Instruments, <www.ti.com>
	7	*
	8	* Author :
	9	* Sunil Kumar <[email protected]>
	10	* Shashi Ranjan <[email protected]>
	11	*
	12	* Derived from Beagle Board and 3430 SDP code by
	13	* Richard Woodruff <[email protected]>
	14	* Syed Mohammed Khasim <[email protected]>
	15	*
	16	*
	17	* See file CREDITS for list of people who contributed to this
	18	* project.
	19	*
	20	* This program is free software; you can redistribute it and/or
	21	* modify it under the terms of the GNU General Public License as
	22	* published by the Free Software Foundation; either version 2 of
	23	* the License, or (at your option) any later version.
	24	*
	25	* This program is distributed in the hope that it will be useful,
	26	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	27	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	28	* GNU General Public License for more details.
	29	*
	30	* You should have received a copy of the GNU General Public License
	31	* along with this program; if not, write to the Free Software
	32	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	33	* MA 02111-1307 USA
	34	*/
	35	#include <common.h>
	36	#include <asm/io.h>
	37	#include <asm/arch/sys_proto.h>
	38	#include <asm/arch/mem.h>
	39
	40	extern omap3_sysinfo sysinfo;
	41
	42	/******************************************************************************
	43	* Routine: delay
	44	* Description: spinning delay to use before udelay works
	45	*****************************************************************************/
	46	static inline void delay(unsigned long loops)
	47	{
	48	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
	49	"bne 1b":"=r" (loops):"0"(loops));
	50	}
	51
	52	/******************************************************************************
	53	* Routine: secure_unlock
	54	* Description: Setup security registers for access
	55	* (GP Device only)
	56	*****************************************************************************/
	57	void secure_unlock_mem(void)
	58	{
	59	pm_t pm_rt_ape_base = (pm_t )PM_RT_APE_BASE_ADDR_ARM;
	60	pm_t pm_gpmc_base = (pm_t )PM_GPMC_BASE_ADDR_ARM;
	61	pm_t pm_ocm_ram_base = (pm_t )PM_OCM_RAM_BASE_ADDR_ARM;
	62	pm_t pm_iva2_base = (pm_t )PM_IVA2_BASE_ADDR_ARM;
	63	sms_t sms_base = (sms_t )OMAP34XX_SMS_BASE;
	64
65	/* Protection Module Register Target APE (PM_RT) */
66	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
67	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
68	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
69	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
70
71	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
72	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
73	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
74
75	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
76	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
77	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
78	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
79
80	/* IVA Changes */
81	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
82	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
83	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
84
85	/* SDRC region 0 public */
86	writel(UNLOCK_1, &sms_base->rg_att0);
87	}
88
89	/******************************************************************************
90	* Routine: secureworld_exit()
91	* Description: If chip is EMU and boot type is external
92	* configure secure registers and exit secure world
93	* general use.
94	*****************************************************************************/
95	void secureworld_exit()
96	{
97	unsigned long i;
98
99	/* configrue non-secure access control register */
100	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
101	/* enabling co-processor CP10 and CP11 accesses in NS world */
102	__asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
103	/*
104	* allow allocation of locked TLBs and L2 lines in NS world
105	* allow use of PLE registers in NS world also
106	*/
107	__asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
108	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
109
110	/* Enable ASA in ACR register */
111	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
112	__asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
113	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
114
115	/* Exiting secure world */
116	__asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
117	__asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
118	__asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
119	}
120
121	/******************************************************************************
122	* Routine: setup_auxcr()
123	* Description: Write to AuxCR desired value using SMI.
124	* general use.
125	*****************************************************************************/
126	void setup_auxcr()
127	{
128	unsigned long i;
129	volatile unsigned int j;
130	/* Save r0, r12 and restore them after usage */
131	__asm__ __volatile__("mov %0, r12":"=r"(j));
132	__asm__ __volatile__("mov %0, r0":"=r"(i));
133
134	/*
135	* GP Device ROM code API usage here
136	* r12 = AUXCR Write function and r0 value
137	*/
138	__asm__ __volatile__("mov r12, #0x3");
139	__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
140	/* Enabling ASA */
141	__asm__ __volatile__("orr r0, r0, #0x10");
142	/* Enable L1NEON */
143	__asm__ __volatile__("orr r0, r0, #1 << 5");
144	/* SMI instruction to call ROM Code API */
145	__asm__ __volatile__(".word 0xE1600070");
146	__asm__ __volatile__("mov r0, %0":"=r"(i));
147	__asm__ __volatile__("mov r12, %0":"=r"(j));
148	}
149
150	/******************************************************************************
151	* Routine: try_unlock_sram()
152	* Description: If chip is GP/EMU(special) type, unlock the SRAM for
153	* general use.
154	*****************************************************************************/
155	void try_unlock_memory()
156	{
157	int mode;
158	int in_sdram = is_running_in_sdram();
159
160	/*
161	* if GP device unlock device SRAM for general use
162	* secure code breaks for Secure/Emulation device - HS/E/T
163	*/
164	mode = get_device_type();
165	if (mode == GP_DEVICE)
166	secure_unlock_mem();
167
168	/*
169	* If device is EMU and boot is XIP external booting
170	* Unlock firewalls and disable L2 and put chip
171	* out of secure world
172	*
173	* Assuming memories are unlocked by the demon who put us in SDRAM
174	*/
175	if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
176	&& (!in_sdram)) {
177	secure_unlock_mem();
178	secureworld_exit();
179	}
180
181	return;
182	}
183
184	/******************************************************************************
185	* Routine: s_init
186	* Description: Does early system init of muxing and clocks.
187	* - Called path is with SRAM stack.
188	*****************************************************************************/
189	void s_init(void)
190	{
191	int in_sdram = is_running_in_sdram();
192
193	watchdog_init();
194
195	try_unlock_memory();
196
197	/*
198	* Right now flushing at low MPU speed.
199	* Need to move after clock init
200	*/
201	v7_flush_dcache_all(get_device_type());
202	#ifndef CONFIG_ICACHE_OFF
203	icache_enable();
204	#endif
205
206	#ifdef CONFIG_L2_OFF
207	l2cache_disable();
208	#else
209	l2cache_enable();
210	#endif
211	/*
212	* Writing to AuxCR in U-boot using SMI for GP DEV
213	* Currently SMI in Kernel on ES2 devices seems to have an issue
214	* Once that is resolved, we can postpone this config to kernel
215	*/
216	if (get_device_type() == GP_DEVICE)
217	setup_auxcr();
218
219	set_muxconf_regs();
220	delay(100);
221
222	prcm_init();
223
224	per_clocks_enable();
225
226	if (!in_sdram)
227	sdrc_init();
228	}
229
230	/******************************************************************************
231	* Routine: wait_for_command_complete
232	* Description: Wait for posting to finish on watchdog
233	*****************************************************************************/
234	void wait_for_command_complete(watchdog_t *wd_base)
235	{
236	int pending = 1;
237	do {
238	pending = readl(&wd_base->wwps);
239	} while (pending);
240	}
241
242	/******************************************************************************
243	* Routine: watchdog_init
244	* Description: Shut down watch dogs
245	*****************************************************************************/
246	void watchdog_init(void)
247	{
248	watchdog_t wd2_base = (watchdog_t )WD2_BASE;
249	prcm_t prcm_base = (prcm_t )PRCM_BASE;
250
251	/*
252	* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
253	* either taken care of by ROM (HS/EMU) or not accessible (GP).
254	* We need to take care of WD2-MPU or take a PRCM reset. WD3
255	* should not be running and does not generate a PRCM reset.
256	*/
257
258	sr32(&prcm_base->fclken_wkup, 5, 1, 1);
259	sr32(&prcm_base->iclken_wkup, 5, 1, 1);
260	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
261
262	writel(WD_UNLOCK1, &wd2_base->wspr);
263	wait_for_command_complete(wd2_base);
264	writel(WD_UNLOCK2, &wd2_base->wspr);
265	}
266
267	/******************************************************************************
268	* Routine: dram_init
269	* Description: sets uboots idea of sdram size
270	*****************************************************************************/
271	int dram_init(void)
272	{
273	DECLARE_GLOBAL_DATA_PTR;
274	unsigned int size0 = 0, size1 = 0;
275	u32 btype;
276
277	btype = get_board_type();
278
279	display_board_info(btype);
280
281	/*
282	* If a second bank of DDR is attached to CS1 this is
283	* where it can be started. Early init code will init
284	* memory on CS0.
285	*/
286	if ((sysinfo.mtype == DDR_COMBO) \|\| (sysinfo.mtype == DDR_STACKED)) {
287	do_sdrc_init(CS1, NOT_EARLY);
288	make_cs1_contiguous();
289	}
290
291	size0 = get_sdr_cs_size(CS0);
292	size1 = get_sdr_cs_size(CS1);
293
294	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
295	gd->bd->bi_dram[0].size = size0;
296	gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
297	gd->bd->bi_dram[1].size = size1;
298
299	return 0;
300	}
301
302	/******************************************************************************
303	* Dummy function to handle errors for EABI incompatibility
304	*****************************************************************************/
305	void raise(void)
306	{
307	}
308
309	/******************************************************************************
310	* Dummy function to handle errors for EABI incompatibility
311	*****************************************************************************/
312	void abort(void)
313	{
314	}
315
316	#ifdef CONFIG_NAND_OMAP_GPMC
317	/******************************************************************************
318	* OMAP3 specific command to switch between NAND HW and SW ecc
319	*****************************************************************************/
320	static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
321	{
322	if (argc != 2)
323	goto usage;
324	if (strncmp(argv[1], "hw", 2) == 0)
325	omap_nand_switch_ecc(1);
326	else if (strncmp(argv[1], "sw", 2) == 0)
327	omap_nand_switch_ecc(0);
328	else
329	goto usage;
330
331	return 0;
332
333	usage:
36003268	334	printf ("Usage: nandecc %s\n", cmdtp->usage);
91eee546 DB	335	return 1;
	336	}
	337
	338	U_BOOT_CMD(
	339	nandecc, 2, 1, do_switch_ecc,
	340	"nandecc - switch OMAP3 NAND ECC calculation algorithm\n",
	341	"[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm\n"
	342	);
	343
	344	#endif /* CONFIG_NAND_OMAP_GPMC */