drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_atomic_uapi.h>
  40 #include <drm/drm_fb_cma_helper.h>
  41 #include <drm/drm_framebuffer.h>
  42 #include <drm/drm_print.h>
  43 #include <drm/drm_probe_helper.h>
  44 #include <drm/drm_vblank.h>
  45
  46 #include "vc4_drv.h"
  47 #include "vc4_hdmi.h"
  48 #include "vc4_regs.h"
  49
  50 #define HVS_FIFO_LATENCY_PIX    6
  51
  52 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  53 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  54
  55 static const struct debugfs_reg32 crtc_regs[] = {
  56         VC4_REG32(PV_CONTROL),
  57         VC4_REG32(PV_V_CONTROL),
  58         VC4_REG32(PV_VSYNCD_EVEN),
  59         VC4_REG32(PV_HORZA),
  60         VC4_REG32(PV_HORZB),
  61         VC4_REG32(PV_VERTA),
  62         VC4_REG32(PV_VERTB),
  63         VC4_REG32(PV_VERTA_EVEN),
  64         VC4_REG32(PV_VERTB_EVEN),
  65         VC4_REG32(PV_INTEN),
  66         VC4_REG32(PV_INTSTAT),
  67         VC4_REG32(PV_STAT),
  68         VC4_REG32(PV_HACT_ACT),
  69 };
  70
  71 static unsigned int
  72 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
  73 {
  74         struct vc4_hvs *hvs = vc4->hvs;
  75         u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  76         /* Top/base are supposed to be 4-pixel aligned, but the
  77          * Raspberry Pi firmware fills the low bits (which are
  78          * presumably ignored).
  79          */
  80         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  81         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  82
  83         return top - base + 4;
  84 }
  85
  86 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
  87                                           bool in_vblank_irq,
  88                                           int *vpos, int *hpos,
  89                                           ktime_t *stime, ktime_t *etime,
  90                                           const struct drm_display_mode *mode)
  91 {
  92         struct drm_device *dev = crtc->dev;
  93         struct vc4_dev *vc4 = to_vc4_dev(dev);
  94         struct vc4_hvs *hvs = vc4->hvs;
  95         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  96         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
  97         unsigned int cob_size;
  98         u32 val;
  99         int fifo_lines;
 100         int vblank_lines;
 101         bool ret = false;
 102
 103         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 104
 105         /* Get optional system timestamp before query. */
 106         if (stime)
 107                 *stime = ktime_get();
 108
 109         /*
 110          * Read vertical scanline which is currently composed for our
 111          * pixelvalve by the HVS, and also the scaler status.
 112          */
 113         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
 114
 115         /* Get optional system timestamp after query. */
 116         if (etime)
 117                 *etime = ktime_get();
 118
 119         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 120
 121         /* Vertical position of hvs composed scanline. */
 122         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 123         *hpos = 0;
 124
 125         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 126                 *vpos /= 2;
 127
 128                 /* Use hpos to correct for field offset in interlaced mode. */
 129                 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2)
 130                         *hpos += mode->crtc_htotal / 2;
 131         }
 132
 133         cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
 134         /* This is the offset we need for translating hvs -> pv scanout pos. */
 135         fifo_lines = cob_size / mode->crtc_hdisplay;
 136
 137         if (fifo_lines > 0)
 138                 ret = true;
 139
 140         /* HVS more than fifo_lines into frame for compositing? */
 141         if (*vpos > fifo_lines) {
 142                 /*
 143                  * We are in active scanout and can get some meaningful results
 144                  * from HVS. The actual PV scanout can not trail behind more
 145                  * than fifo_lines as that is the fifo's capacity. Assume that
 146                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 147                  * refilling the fifo and PV consuming from the fifo, ie.
 148                  * whenever the PV consumes and frees up a scanline in the
 149                  * fifo, the HVS will immediately refill it, therefore
 150                  * incrementing vpos. Therefore we choose HVS read position -
 151                  * fifo size in scanlines as a estimate of the real scanout
 152                  * position of the PV.
 153                  */
 154                 *vpos -= fifo_lines + 1;
 155
 156                 return ret;
 157         }
 158
 159         /*
 160          * Less: This happens when we are in vblank and the HVS, after getting
 161          * the VSTART restart signal from the PV, just started refilling its
 162          * fifo with new lines from the top-most lines of the new framebuffers.
 163          * The PV does not scan out in vblank, so does not remove lines from
 164          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 165          * We can't get meaningful readings wrt. scanline position of the PV
 166          * and need to make things up in a approximative but consistent way.
 167          */
 168         vblank_lines = mode->vtotal - mode->vdisplay;
 169
 170         if (in_vblank_irq) {
 171                 /*
 172                  * Assume the irq handler got called close to first
 173                  * line of vblank, so PV has about a full vblank
 174                  * scanlines to go, and as a base timestamp use the
 175                  * one taken at entry into vblank irq handler, so it
 176                  * is not affected by random delays due to lock
 177                  * contention on event_lock or vblank_time lock in
 178                  * the core.
 179                  */
 180                 *vpos = -vblank_lines;
 181
 182                 if (stime)
 183                         *stime = vc4_crtc->t_vblank;
 184                 if (etime)
 185                         *etime = vc4_crtc->t_vblank;
 186
 187                 /*
 188                  * If the HVS fifo is not yet full then we know for certain
 189                  * we are at the very beginning of vblank, as the hvs just
 190                  * started refilling, and the stime and etime timestamps
 191                  * truly correspond to start of vblank.
 192                  *
 193                  * Unfortunately there's no way to report this to upper levels
 194                  * and make it more useful.
 195                  */
 196         } else {
 197                 /*
 198                  * No clue where we are inside vblank. Return a vpos of zero,
 199                  * which will cause calling code to just return the etime
 200                  * timestamp uncorrected. At least this is no worse than the
 201                  * standard fallback.
 202                  */
 203                 *vpos = 0;
 204         }
 205
 206         return ret;
 207 }
 208
 209 void vc4_crtc_destroy(struct drm_crtc *crtc)
 210 {
 211         drm_crtc_cleanup(crtc);
 212 }
 213
 214 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 215 {
 216         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
 217         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 218         struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
 219         u32 fifo_len_bytes = pv_data->fifo_depth;
 220
 221         /*
 222          * Pixels are pulled from the HVS if the number of bytes is
 223          * lower than the FIFO full level.
 224          *
 225          * The latency of the pixel fetch mechanism is 6 pixels, so we
 226          * need to convert those 6 pixels in bytes, depending on the
 227          * format, and then subtract that from the length of the FIFO
 228          * to make sure we never end up in a situation where the FIFO
 229          * is full.
 230          */
 231         switch (format) {
 232         case PV_CONTROL_FORMAT_DSIV_16:
 233         case PV_CONTROL_FORMAT_DSIC_16:
 234                 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
 235         case PV_CONTROL_FORMAT_DSIV_18:
 236                 return fifo_len_bytes - 14;
 237         case PV_CONTROL_FORMAT_24:
 238         case PV_CONTROL_FORMAT_DSIV_24:
 239         default:
 240                 /*
 241                  * For some reason, the pixelvalve4 doesn't work with
 242                  * the usual formula and will only work with 32.
 243                  */
 244                 if (crtc_data->hvs_output == 5)
 245                         return 32;
 246
 247                 /*
 248                  * It looks like in some situations, we will overflow
 249                  * the PixelValve FIFO (with the bit 10 of PV stat being
 250                  * set) and stall the HVS / PV, eventually resulting in
 251                  * a page flip timeout.
 252                  *
 253                  * Displaying the video overlay during a playback with
 254                  * Kodi on an RPi3 seems to be a great solution with a
 255                  * failure rate around 50%.
 256                  *
 257                  * Removing 1 from the FIFO full level however
 258                  * seems to completely remove that issue.
 259                  */
 260                 if (!vc4->is_vc5)
 261                         return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
 262
 263                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 264         }
 265 }
 266
 267 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
 268                                              u32 format)
 269 {
 270         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
 271         u32 ret = 0;
 272
 273         ret |= VC4_SET_FIELD((level >> 6),
 274                              PV5_CONTROL_FIFO_LEVEL_HIGH);
 275
 276         return ret | VC4_SET_FIELD(level & 0x3f,
 277                                    PV_CONTROL_FIFO_LEVEL);
 278 }
 279
 280 /*
 281  * Returns the encoder attached to the CRTC.
 282  *
 283  * VC4 can only scan out to one encoder at a time, while the DRM core
 284  * allows drivers to push pixels to more than one encoder from the
 285  * same CRTC.
 286  */
 287 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
 288                                          struct drm_crtc_state *state)
 289 {
 290         struct drm_encoder *encoder;
 291
 292         WARN_ON(hweight32(state->encoder_mask) > 1);
 293
 294         drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
 295                 return encoder;
 296
 297         return NULL;
 298 }
 299
 300 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
 301 {
 302         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 303
 304         /* The PV needs to be disabled before it can be flushed */
 305         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
 306         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
 307 }
 308
 309 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder,
 310                                struct drm_atomic_state *state)
 311 {
 312         struct drm_device *dev = crtc->dev;
 313         struct vc4_dev *vc4 = to_vc4_dev(dev);
 314         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 315         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 316         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 317         struct drm_crtc_state *crtc_state = crtc->state;
 318         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 319         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 320         bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 ||
 321                        vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1;
 322         u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1;
 323         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 324                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 325         bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
 326         u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 327         u8 ppc = pv_data->pixels_per_clock;
 328         bool debug_dump_regs = false;
 329
 330         if (debug_dump_regs) {
 331                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 332                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 333                          drm_crtc_index(crtc));
 334                 drm_print_regset32(&p, &vc4_crtc->regset);
 335         }
 336
 337         vc4_crtc_pixelvalve_reset(crtc);
 338
 339         CRTC_WRITE(PV_HORZA,
 340                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 341                                  PV_HORZA_HBP) |
 342                    VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
 343                                  PV_HORZA_HSYNC));
 344
 345         CRTC_WRITE(PV_HORZB,
 346                    VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
 347                                  PV_HORZB_HFP) |
 348                    VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
 349                                  PV_HORZB_HACTIVE));
 350
 351         CRTC_WRITE(PV_VERTA,
 352                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
 353                                  interlace,
 354                                  PV_VERTA_VBP) |
 355                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 356                                  PV_VERTA_VSYNC));
 357         CRTC_WRITE(PV_VERTB,
 358                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 359                                  PV_VERTB_VFP) |
 360                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 361
 362         if (interlace) {
 363                 CRTC_WRITE(PV_VERTA_EVEN,
 364                            VC4_SET_FIELD(mode->crtc_vtotal -
 365                                          mode->crtc_vsync_end,
 366                                          PV_VERTA_VBP) |
 367                            VC4_SET_FIELD(mode->crtc_vsync_end -
 368                                          mode->crtc_vsync_start,
 369                                          PV_VERTA_VSYNC));
 370                 CRTC_WRITE(PV_VERTB_EVEN,
 371                            VC4_SET_FIELD(mode->crtc_vsync_start -
 372                                          mode->crtc_vdisplay,
 373                                          PV_VERTB_VFP) |
 374                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 375
 376                 /* We set up first field even mode for HDMI.  VEC's
 377                  * NTSC mode would want first field odd instead, once
 378                  * we support it (to do so, set ODD_FIRST and put the
 379                  * delay in VSYNCD_EVEN instead).
 380                  */
 381                 CRTC_WRITE(PV_V_CONTROL,
 382                            PV_VCONTROL_CONTINUOUS |
 383                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 384                            PV_VCONTROL_INTERLACE |
 385                            VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
 386                                          PV_VCONTROL_ODD_DELAY));
 387                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 388         } else {
 389                 CRTC_WRITE(PV_V_CONTROL,
 390                            PV_VCONTROL_CONTINUOUS |
 391                            (is_dsi ? PV_VCONTROL_DSI : 0));
 392         }
 393
 394         if (is_dsi)
 395                 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 396
 397         if (vc4->is_vc5)
 398                 CRTC_WRITE(PV_MUX_CFG,
 399                            VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
 400                                          PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
 401
 402         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
 403                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 404                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 405                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 406                    PV_CONTROL_CLR_AT_START |
 407                    PV_CONTROL_TRIGGER_UNDERFLOW |
 408                    PV_CONTROL_WAIT_HSTART |
 409                    VC4_SET_FIELD(vc4_encoder->clock_select,
 410                                  PV_CONTROL_CLK_SELECT));
 411
 412         if (debug_dump_regs) {
 413                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 414                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 415                          drm_crtc_index(crtc));
 416                 drm_print_regset32(&p, &vc4_crtc->regset);
 417         }
 418 }
 419
 420 static void require_hvs_enabled(struct drm_device *dev)
 421 {
 422         struct vc4_dev *vc4 = to_vc4_dev(dev);
 423         struct vc4_hvs *hvs = vc4->hvs;
 424
 425         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 426                      SCALER_DISPCTRL_ENABLE);
 427 }
 428
 429 static int vc4_crtc_disable(struct drm_crtc *crtc,
 430                             struct drm_encoder *encoder,
 431                             struct drm_atomic_state *state,
 432                             unsigned int channel)
 433 {
 434         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 435         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 436         struct drm_device *dev = crtc->dev;
 437         struct vc4_dev *vc4 = to_vc4_dev(dev);
 438         int ret;
 439
 440         CRTC_WRITE(PV_V_CONTROL,
 441                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 442         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 443         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 444
 445         /*
 446          * This delay is needed to avoid to get a pixel stuck in an
 447          * unflushable FIFO between the pixelvalve and the HDMI
 448          * controllers on the BCM2711.
 449          *
 450          * Timing is fairly sensitive here, so mdelay is the safest
 451          * approach.
 452          *
 453          * If it was to be reworked, the stuck pixel happens on a
 454          * BCM2711 when changing mode with a good probability, so a
 455          * script that changes mode on a regular basis should trigger
 456          * the bug after less than 10 attempts. It manifests itself with
 457          * every pixels being shifted by one to the right, and thus the
 458          * last pixel of a line actually being displayed as the first
 459          * pixel on the next line.
 460          */
 461         mdelay(20);
 462
 463         if (vc4_encoder && vc4_encoder->post_crtc_disable)
 464                 vc4_encoder->post_crtc_disable(encoder, state);
 465
 466         vc4_crtc_pixelvalve_reset(crtc);
 467         vc4_hvs_stop_channel(vc4->hvs, channel);
 468
 469         if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
 470                 vc4_encoder->post_crtc_powerdown(encoder, state);
 471
 472         return 0;
 473 }
 474
 475 static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc,
 476                                                         enum vc4_encoder_type type)
 477 {
 478         struct drm_encoder *encoder;
 479
 480         drm_for_each_encoder(encoder, crtc->dev) {
 481                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 482
 483                 if (vc4_encoder->type == type)
 484                         return encoder;
 485         }
 486
 487         return NULL;
 488 }
 489
 490 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
 491 {
 492         struct drm_device *drm = crtc->dev;
 493         struct vc4_dev *vc4 = to_vc4_dev(drm);
 494         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 495         enum vc4_encoder_type encoder_type;
 496         const struct vc4_pv_data *pv_data;
 497         struct drm_encoder *encoder;
 498         struct vc4_hdmi *vc4_hdmi;
 499         unsigned encoder_sel;
 500         int channel;
 501         int ret;
 502
 503         if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 504                                       "brcm,bcm2711-pixelvalve2") ||
 505               of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 506                                       "brcm,bcm2711-pixelvalve4")))
 507                 return 0;
 508
 509         if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
 510                 return 0;
 511
 512         if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
 513                 return 0;
 514
 515         channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
 516         if (channel < 0)
 517                 return 0;
 518
 519         encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
 520         if (WARN_ON(encoder_sel != 0))
 521                 return 0;
 522
 523         pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 524         encoder_type = pv_data->encoder_types[encoder_sel];
 525         encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type);
 526         if (WARN_ON(!encoder))
 527                 return 0;
 528
 529         vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 530         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 531         if (ret)
 532                 return ret;
 533
 534         ret = vc4_crtc_disable(crtc, encoder, NULL, channel);
 535         if (ret)
 536                 return ret;
 537
 538         /*
 539          * post_crtc_powerdown will have called pm_runtime_put, so we
 540          * don't need it here otherwise we'll get the reference counting
 541          * wrong.
 542          */
 543
 544         return 0;
 545 }
 546
 547 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 548                                     struct drm_atomic_state *state)
 549 {
 550         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
 551                                                                          crtc);
 552         struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
 553         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);
 554         struct drm_device *dev = crtc->dev;
 555
 556         drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)",
 557                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 558
 559         require_hvs_enabled(dev);
 560
 561         /* Disable vblank irq handling before crtc is disabled. */
 562         drm_crtc_vblank_off(crtc);
 563
 564         vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
 565
 566         /*
 567          * Make sure we issue a vblank event after disabling the CRTC if
 568          * someone was waiting it.
 569          */
 570         if (crtc->state->event) {
 571                 unsigned long flags;
 572
 573                 spin_lock_irqsave(&dev->event_lock, flags);
 574                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 575                 crtc->state->event = NULL;
 576                 spin_unlock_irqrestore(&dev->event_lock, flags);
 577         }
 578 }
 579
 580 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 581                                    struct drm_atomic_state *state)
 582 {
 583         struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,
 584                                                                          crtc);
 585         struct drm_device *dev = crtc->dev;
 586         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 587         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);
 588         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 589
 590         drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)",
 591                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 592
 593         require_hvs_enabled(dev);
 594
 595         /* Enable vblank irq handling before crtc is started otherwise
 596          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 597          */
 598         drm_crtc_vblank_on(crtc);
 599
 600         vc4_hvs_atomic_enable(crtc, state);
 601
 602         if (vc4_encoder->pre_crtc_configure)
 603                 vc4_encoder->pre_crtc_configure(encoder, state);
 604
 605         vc4_crtc_config_pv(crtc, encoder, state);
 606
 607         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
 608
 609         if (vc4_encoder->pre_crtc_enable)
 610                 vc4_encoder->pre_crtc_enable(encoder, state);
 611
 612         /* When feeding the transposer block the pixelvalve is unneeded and
 613          * should not be enabled.
 614          */
 615         CRTC_WRITE(PV_V_CONTROL,
 616                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 617
 618         if (vc4_encoder->post_crtc_enable)
 619                 vc4_encoder->post_crtc_enable(encoder, state);
 620 }
 621
 622 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 623                                                 const struct drm_display_mode *mode)
 624 {
 625         /* Do not allow doublescan modes from user space */
 626         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 627                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 628                               crtc->base.id);
 629                 return MODE_NO_DBLESCAN;
 630         }
 631
 632         return MODE_OK;
 633 }
 634
 635 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 636                           unsigned int *left, unsigned int *right,
 637                           unsigned int *top, unsigned int *bottom)
 638 {
 639         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 640         struct drm_connector_state *conn_state;
 641         struct drm_connector *conn;
 642         int i;
 643
 644         *left = vc4_state->margins.left;
 645         *right = vc4_state->margins.right;
 646         *top = vc4_state->margins.top;
 647         *bottom = vc4_state->margins.bottom;
 648
 649         /* We have to interate over all new connector states because
 650          * vc4_crtc_get_margins() might be called before
 651          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 652          * might be outdated.
 653          */
 654         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 655                 if (conn_state->crtc != state->crtc)
 656                         continue;
 657
 658                 *left = conn_state->tv.margins.left;
 659                 *right = conn_state->tv.margins.right;
 660                 *top = conn_state->tv.margins.top;
 661                 *bottom = conn_state->tv.margins.bottom;
 662                 break;
 663         }
 664 }
 665
 666 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 667                                  struct drm_atomic_state *state)
 668 {
 669         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 670                                                                           crtc);
 671         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 672         struct drm_connector *conn;
 673         struct drm_connector_state *conn_state;
 674         struct drm_encoder *encoder;
 675         int ret, i;
 676
 677         ret = vc4_hvs_atomic_check(crtc, state);
 678         if (ret)
 679                 return ret;
 680
 681         encoder = vc4_get_crtc_encoder(crtc, crtc_state);
 682         if (encoder) {
 683                 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 684                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 685
 686                 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
 687                         vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,
 688                                                   mode->clock * 9 / 10) * 1000;
 689                 } else {
 690                         vc4_state->hvs_load = mode->clock * 1000;
 691                 }
 692         }
 693
 694         for_each_new_connector_in_state(state, conn, conn_state,
 695                                         i) {
 696                 if (conn_state->crtc != crtc)
 697                         continue;
 698
 699                 vc4_state->margins.left = conn_state->tv.margins.left;
 700                 vc4_state->margins.right = conn_state->tv.margins.right;
 701                 vc4_state->margins.top = conn_state->tv.margins.top;
 702                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 703                 break;
 704         }
 705
 706         return 0;
 707 }
 708
 709 static int vc4_enable_vblank(struct drm_crtc *crtc)
 710 {
 711         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 712
 713         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 714
 715         return 0;
 716 }
 717
 718 static void vc4_disable_vblank(struct drm_crtc *crtc)
 719 {
 720         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 721
 722         CRTC_WRITE(PV_INTEN, 0);
 723 }
 724
 725 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 726 {
 727         struct drm_crtc *crtc = &vc4_crtc->base;
 728         struct drm_device *dev = crtc->dev;
 729         struct vc4_dev *vc4 = to_vc4_dev(dev);
 730         struct vc4_hvs *hvs = vc4->hvs;
 731         u32 chan = vc4_crtc->current_hvs_channel;
 732         unsigned long flags;
 733
 734         spin_lock_irqsave(&dev->event_lock, flags);
 735         spin_lock(&vc4_crtc->irq_lock);
 736         if (vc4_crtc->event &&
 737             (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) ||
 738              vc4_crtc->feeds_txp)) {
 739                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 740                 vc4_crtc->event = NULL;
 741                 drm_crtc_vblank_put(crtc);
 742
 743                 /* Wait for the page flip to unmask the underrun to ensure that
 744                  * the display list was updated by the hardware. Before that
 745                  * happens, the HVS will be using the previous display list with
 746                  * the CRTC and encoder already reconfigured, leading to
 747                  * underruns. This can be seen when reconfiguring the CRTC.
 748                  */
 749                 vc4_hvs_unmask_underrun(hvs, chan);
 750         }
 751         spin_unlock(&vc4_crtc->irq_lock);
 752         spin_unlock_irqrestore(&dev->event_lock, flags);
 753 }
 754
 755 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 756 {
 757         crtc->t_vblank = ktime_get();
 758         drm_crtc_handle_vblank(&crtc->base);
 759         vc4_crtc_handle_page_flip(crtc);
 760 }
 761
 762 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 763 {
 764         struct vc4_crtc *vc4_crtc = data;
 765         u32 stat = CRTC_READ(PV_INTSTAT);
 766         irqreturn_t ret = IRQ_NONE;
 767
 768         if (stat & PV_INT_VFP_START) {
 769                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 770                 vc4_crtc_handle_vblank(vc4_crtc);
 771                 ret = IRQ_HANDLED;
 772         }
 773
 774         return ret;
 775 }
 776
 777 struct vc4_async_flip_state {
 778         struct drm_crtc *crtc;
 779         struct drm_framebuffer *fb;
 780         struct drm_framebuffer *old_fb;
 781         struct drm_pending_vblank_event *event;
 782
 783         union {
 784                 struct dma_fence_cb fence;
 785                 struct vc4_seqno_cb seqno;
 786         } cb;
 787 };
 788
 789 /* Called when the V3D execution for the BO being flipped to is done, so that
 790  * we can actually update the plane's address to point to it.
 791  */
 792 static void
 793 vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
 794 {
 795         struct drm_crtc *crtc = flip_state->crtc;
 796         struct drm_device *dev = crtc->dev;
 797         struct drm_plane *plane = crtc->primary;
 798
 799         vc4_plane_async_set_fb(plane, flip_state->fb);
 800         if (flip_state->event) {
 801                 unsigned long flags;
 802
 803                 spin_lock_irqsave(&dev->event_lock, flags);
 804                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 805                 spin_unlock_irqrestore(&dev->event_lock, flags);
 806         }
 807
 808         drm_crtc_vblank_put(crtc);
 809         drm_framebuffer_put(flip_state->fb);
 810
 811         if (flip_state->old_fb)
 812                 drm_framebuffer_put(flip_state->old_fb);
 813
 814         kfree(flip_state);
 815 }
 816
 817 static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 818 {
 819         struct vc4_async_flip_state *flip_state =
 820                 container_of(cb, struct vc4_async_flip_state, cb.seqno);
 821         struct vc4_bo *bo = NULL;
 822
 823         if (flip_state->old_fb) {
 824                 struct drm_gem_cma_object *cma_bo =
 825                         drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 826                 bo = to_vc4_bo(&cma_bo->base);
 827         }
 828
 829         vc4_async_page_flip_complete(flip_state);
 830
 831         /*
 832          * Decrement the BO usecnt in order to keep the inc/dec
 833          * calls balanced when the planes are updated through
 834          * the async update path.
 835          *
 836          * FIXME: we should move to generic async-page-flip when
 837          * it's available, so that we can get rid of this
 838          * hand-made cleanup_fb() logic.
 839          */
 840         if (bo)
 841                 vc4_bo_dec_usecnt(bo);
 842 }
 843
 844 static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
 845                                                struct dma_fence_cb *cb)
 846 {
 847         struct vc4_async_flip_state *flip_state =
 848                 container_of(cb, struct vc4_async_flip_state, cb.fence);
 849
 850         vc4_async_page_flip_complete(flip_state);
 851         dma_fence_put(fence);
 852 }
 853
 854 static int vc4_async_set_fence_cb(struct drm_device *dev,
 855                                   struct vc4_async_flip_state *flip_state)
 856 {
 857         struct drm_framebuffer *fb = flip_state->fb;
 858         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 859         struct vc4_dev *vc4 = to_vc4_dev(dev);
 860         struct dma_fence *fence;
 861         int ret;
 862
 863         if (!vc4->is_vc5) {
 864                 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 865
 866                 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
 867                                           vc4_async_page_flip_seqno_complete);
 868         }
 869
 870         ret = dma_resv_get_singleton(cma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
 871         if (ret)
 872                 return ret;
 873
 874         /* If there's no fence, complete the page flip immediately */
 875         if (!fence) {
 876                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 877                 return 0;
 878         }
 879
 880         /* If the fence has already been completed, complete the page flip */
 881         if (dma_fence_add_callback(fence, &flip_state->cb.fence,
 882                                    vc4_async_page_flip_fence_complete))
 883                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 884
 885         return 0;
 886 }
 887
 888 static int
 889 vc4_async_page_flip_common(struct drm_crtc *crtc,
 890                            struct drm_framebuffer *fb,
 891                            struct drm_pending_vblank_event *event,
 892                            uint32_t flags)
 893 {
 894         struct drm_device *dev = crtc->dev;
 895         struct drm_plane *plane = crtc->primary;
 896         struct vc4_async_flip_state *flip_state;
 897
 898         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 899         if (!flip_state)
 900                 return -ENOMEM;
 901
 902         drm_framebuffer_get(fb);
 903         flip_state->fb = fb;
 904         flip_state->crtc = crtc;
 905         flip_state->event = event;
 906
 907         /* Save the current FB before it's replaced by the new one in
 908          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 909          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 910          * it consistent.
 911          * FIXME: we should move to generic async-page-flip when it's
 912          * available, so that we can get rid of this hand-made cleanup_fb()
 913          * logic.
 914          */
 915         flip_state->old_fb = plane->state->fb;
 916         if (flip_state->old_fb)
 917                 drm_framebuffer_get(flip_state->old_fb);
 918
 919         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 920
 921         /* Immediately update the plane's legacy fb pointer, so that later
 922          * modeset prep sees the state that will be present when the semaphore
 923          * is released.
 924          */
 925         drm_atomic_set_fb_for_plane(plane->state, fb);
 926
 927         vc4_async_set_fence_cb(dev, flip_state);
 928
 929         /* Driver takes ownership of state on successful async commit. */
 930         return 0;
 931 }
 932
 933 /* Implements async (non-vblank-synced) page flips.
 934  *
 935  * The page flip ioctl needs to return immediately, so we grab the
 936  * modeset semaphore on the pipe, and queue the address update for
 937  * when V3D is done with the BO being flipped to.
 938  */
 939 static int vc4_async_page_flip(struct drm_crtc *crtc,
 940                                struct drm_framebuffer *fb,
 941                                struct drm_pending_vblank_event *event,
 942                                uint32_t flags)
 943 {
 944         struct drm_device *dev = crtc->dev;
 945         struct vc4_dev *vc4 = to_vc4_dev(dev);
 946         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 947         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 948         int ret;
 949
 950         if (WARN_ON_ONCE(vc4->is_vc5))
 951                 return -ENODEV;
 952
 953         /*
 954          * Increment the BO usecnt here, so that we never end up with an
 955          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 956          * plane is later updated through the non-async path.
 957          *
 958          * FIXME: we should move to generic async-page-flip when
 959          * it's available, so that we can get rid of this
 960          * hand-made prepare_fb() logic.
 961          */
 962         ret = vc4_bo_inc_usecnt(bo);
 963         if (ret)
 964                 return ret;
 965
 966         ret = vc4_async_page_flip_common(crtc, fb, event, flags);
 967         if (ret) {
 968                 vc4_bo_dec_usecnt(bo);
 969                 return ret;
 970         }
 971
 972         return 0;
 973 }
 974
 975 static int vc5_async_page_flip(struct drm_crtc *crtc,
 976                                struct drm_framebuffer *fb,
 977                                struct drm_pending_vblank_event *event,
 978                                uint32_t flags)
 979 {
 980         return vc4_async_page_flip_common(crtc, fb, event, flags);
 981 }
 982
 983 int vc4_page_flip(struct drm_crtc *crtc,
 984                   struct drm_framebuffer *fb,
 985                   struct drm_pending_vblank_event *event,
 986                   uint32_t flags,
 987                   struct drm_modeset_acquire_ctx *ctx)
 988 {
 989         if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
 990                 struct drm_device *dev = crtc->dev;
 991                 struct vc4_dev *vc4 = to_vc4_dev(dev);
 992
 993                 if (vc4->is_vc5)
 994                         return vc5_async_page_flip(crtc, fb, event, flags);
 995                 else
 996                         return vc4_async_page_flip(crtc, fb, event, flags);
 997         } else {
 998                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 999         }
1000 }
1001
1002 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
1003 {
1004         struct vc4_crtc_state *vc4_state, *old_vc4_state;
1005
1006         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1007         if (!vc4_state)
1008                 return NULL;
1009
1010         old_vc4_state = to_vc4_crtc_state(crtc->state);
1011         vc4_state->margins = old_vc4_state->margins;
1012         vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1013
1014         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1015         return &vc4_state->base;
1016 }
1017
1018 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1019                             struct drm_crtc_state *state)
1020 {
1021         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1022         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1023
1024         if (drm_mm_node_allocated(&vc4_state->mm)) {
1025                 unsigned long flags;
1026
1027                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1028                 drm_mm_remove_node(&vc4_state->mm);
1029                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1030
1031         }
1032
1033         drm_atomic_helper_crtc_destroy_state(crtc, state);
1034 }
1035
1036 void vc4_crtc_reset(struct drm_crtc *crtc)
1037 {
1038         struct vc4_crtc_state *vc4_crtc_state;
1039
1040         if (crtc->state)
1041                 vc4_crtc_destroy_state(crtc, crtc->state);
1042
1043         vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
1044         if (!vc4_crtc_state) {
1045                 crtc->state = NULL;
1046                 return;
1047         }
1048
1049         vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
1050         __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
1051 }
1052
1053 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1054         .set_config = drm_atomic_helper_set_config,
1055         .destroy = vc4_crtc_destroy,
1056         .page_flip = vc4_page_flip,
1057         .set_property = NULL,
1058         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1059         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1060         .reset = vc4_crtc_reset,
1061         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1062         .atomic_destroy_state = vc4_crtc_destroy_state,
1063         .enable_vblank = vc4_enable_vblank,
1064         .disable_vblank = vc4_disable_vblank,
1065         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1066 };
1067
1068 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1069         .mode_valid = vc4_crtc_mode_valid,
1070         .atomic_check = vc4_crtc_atomic_check,
1071         .atomic_begin = vc4_hvs_atomic_begin,
1072         .atomic_flush = vc4_hvs_atomic_flush,
1073         .atomic_enable = vc4_crtc_atomic_enable,
1074         .atomic_disable = vc4_crtc_atomic_disable,
1075         .get_scanout_position = vc4_crtc_get_scanout_position,
1076 };
1077
1078 static const struct vc4_pv_data bcm2835_pv0_data = {
1079         .base = {
1080                 .hvs_available_channels = BIT(0),
1081                 .hvs_output = 0,
1082         },
1083         .debugfs_name = "crtc0_regs",
1084         .fifo_depth = 64,
1085         .pixels_per_clock = 1,
1086         .encoder_types = {
1087                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1088                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1089         },
1090 };
1091
1092 static const struct vc4_pv_data bcm2835_pv1_data = {
1093         .base = {
1094                 .hvs_available_channels = BIT(2),
1095                 .hvs_output = 2,
1096         },
1097         .debugfs_name = "crtc1_regs",
1098         .fifo_depth = 64,
1099         .pixels_per_clock = 1,
1100         .encoder_types = {
1101                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1102                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1103         },
1104 };
1105
1106 static const struct vc4_pv_data bcm2835_pv2_data = {
1107         .base = {
1108                 .hvs_available_channels = BIT(1),
1109                 .hvs_output = 1,
1110         },
1111         .debugfs_name = "crtc2_regs",
1112         .fifo_depth = 64,
1113         .pixels_per_clock = 1,
1114         .encoder_types = {
1115                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
1116                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1117         },
1118 };
1119
1120 static const struct vc4_pv_data bcm2711_pv0_data = {
1121         .base = {
1122                 .hvs_available_channels = BIT(0),
1123                 .hvs_output = 0,
1124         },
1125         .debugfs_name = "crtc0_regs",
1126         .fifo_depth = 64,
1127         .pixels_per_clock = 1,
1128         .encoder_types = {
1129                 [0] = VC4_ENCODER_TYPE_DSI0,
1130                 [1] = VC4_ENCODER_TYPE_DPI,
1131         },
1132 };
1133
1134 static const struct vc4_pv_data bcm2711_pv1_data = {
1135         .base = {
1136                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1137                 .hvs_output = 3,
1138         },
1139         .debugfs_name = "crtc1_regs",
1140         .fifo_depth = 64,
1141         .pixels_per_clock = 1,
1142         .encoder_types = {
1143                 [0] = VC4_ENCODER_TYPE_DSI1,
1144                 [1] = VC4_ENCODER_TYPE_SMI,
1145         },
1146 };
1147
1148 static const struct vc4_pv_data bcm2711_pv2_data = {
1149         .base = {
1150                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1151                 .hvs_output = 4,
1152         },
1153         .debugfs_name = "crtc2_regs",
1154         .fifo_depth = 256,
1155         .pixels_per_clock = 2,
1156         .encoder_types = {
1157                 [0] = VC4_ENCODER_TYPE_HDMI0,
1158         },
1159 };
1160
1161 static const struct vc4_pv_data bcm2711_pv3_data = {
1162         .base = {
1163                 .hvs_available_channels = BIT(1),
1164                 .hvs_output = 1,
1165         },
1166         .debugfs_name = "crtc3_regs",
1167         .fifo_depth = 64,
1168         .pixels_per_clock = 1,
1169         .encoder_types = {
1170                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1171         },
1172 };
1173
1174 static const struct vc4_pv_data bcm2711_pv4_data = {
1175         .base = {
1176                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1177                 .hvs_output = 5,
1178         },
1179         .debugfs_name = "crtc4_regs",
1180         .fifo_depth = 64,
1181         .pixels_per_clock = 2,
1182         .encoder_types = {
1183                 [0] = VC4_ENCODER_TYPE_HDMI1,
1184         },
1185 };
1186
1187 static const struct of_device_id vc4_crtc_dt_match[] = {
1188         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1189         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1190         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1191         { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1192         { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1193         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1194         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1195         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1196         {}
1197 };
1198
1199 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1200                                         struct drm_crtc *crtc)
1201 {
1202         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1203         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1204         const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1205         struct drm_encoder *encoder;
1206
1207         drm_for_each_encoder(encoder, drm) {
1208                 struct vc4_encoder *vc4_encoder;
1209                 int i;
1210
1211                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1212                         continue;
1213
1214                 vc4_encoder = to_vc4_encoder(encoder);
1215                 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1216                         if (vc4_encoder->type == encoder_types[i]) {
1217                                 vc4_encoder->clock_select = i;
1218                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1219                                 break;
1220                         }
1221                 }
1222         }
1223 }
1224
1225 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1226                   const struct drm_crtc_funcs *crtc_funcs,
1227                   const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1228 {
1229         struct vc4_dev *vc4 = to_vc4_dev(drm);
1230         struct drm_crtc *crtc = &vc4_crtc->base;
1231         struct drm_plane *primary_plane;
1232         unsigned int i;
1233
1234         /* For now, we create just the primary and the legacy cursor
1235          * planes.  We should be able to stack more planes on easily,
1236          * but to do that we would need to compute the bandwidth
1237          * requirement of the plane configuration, and reject ones
1238          * that will take too much.
1239          */
1240         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1241         if (IS_ERR(primary_plane)) {
1242                 dev_err(drm->dev, "failed to construct primary plane\n");
1243                 return PTR_ERR(primary_plane);
1244         }
1245
1246         spin_lock_init(&vc4_crtc->irq_lock);
1247         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1248                                   crtc_funcs, NULL);
1249         drm_crtc_helper_add(crtc, crtc_helper_funcs);
1250
1251         if (!vc4->is_vc5) {
1252                 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1253
1254                 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1255
1256                 /* We support CTM, but only for one CRTC at a time. It's therefore
1257                  * implemented as private driver state in vc4_kms, not here.
1258                  */
1259                 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1260         }
1261
1262         for (i = 0; i < crtc->gamma_size; i++) {
1263                 vc4_crtc->lut_r[i] = i;
1264                 vc4_crtc->lut_g[i] = i;
1265                 vc4_crtc->lut_b[i] = i;
1266         }
1267
1268         return 0;
1269 }
1270
1271 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1272 {
1273         struct platform_device *pdev = to_platform_device(dev);
1274         struct drm_device *drm = dev_get_drvdata(master);
1275         const struct vc4_pv_data *pv_data;
1276         struct vc4_crtc *vc4_crtc;
1277         struct drm_crtc *crtc;
1278         struct drm_plane *destroy_plane, *temp;
1279         int ret;
1280
1281         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1282         if (!vc4_crtc)
1283                 return -ENOMEM;
1284         crtc = &vc4_crtc->base;
1285
1286         pv_data = of_device_get_match_data(dev);
1287         if (!pv_data)
1288                 return -ENODEV;
1289         vc4_crtc->data = &pv_data->base;
1290         vc4_crtc->pdev = pdev;
1291
1292         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1293         if (IS_ERR(vc4_crtc->regs))
1294                 return PTR_ERR(vc4_crtc->regs);
1295
1296         vc4_crtc->regset.base = vc4_crtc->regs;
1297         vc4_crtc->regset.regs = crtc_regs;
1298         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1299
1300         ret = vc4_crtc_init(drm, vc4_crtc,
1301                             &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1302         if (ret)
1303                 return ret;
1304         vc4_set_crtc_possible_masks(drm, crtc);
1305
1306         CRTC_WRITE(PV_INTEN, 0);
1307         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1308         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1309                                vc4_crtc_irq_handler,
1310                                IRQF_SHARED,
1311                                "vc4 crtc", vc4_crtc);
1312         if (ret)
1313                 goto err_destroy_planes;
1314
1315         platform_set_drvdata(pdev, vc4_crtc);
1316
1317         vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
1318                                  &vc4_crtc->regset);
1319
1320         return 0;
1321
1322 err_destroy_planes:
1323         list_for_each_entry_safe(destroy_plane, temp,
1324                                  &drm->mode_config.plane_list, head) {
1325                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1326                     destroy_plane->funcs->destroy(destroy_plane);
1327         }
1328
1329         return ret;
1330 }
1331
1332 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1333                             void *data)
1334 {
1335         struct platform_device *pdev = to_platform_device(dev);
1336         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1337
1338         vc4_crtc_destroy(&vc4_crtc->base);
1339
1340         CRTC_WRITE(PV_INTEN, 0);
1341
1342         platform_set_drvdata(pdev, NULL);
1343 }
1344
1345 static const struct component_ops vc4_crtc_ops = {
1346         .bind   = vc4_crtc_bind,
1347         .unbind = vc4_crtc_unbind,
1348 };
1349
1350 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1351 {
1352         return component_add(&pdev->dev, &vc4_crtc_ops);
1353 }
1354
1355 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1356 {
1357         component_del(&pdev->dev, &vc4_crtc_ops);
1358         return 0;
1359 }
1360
1361 struct platform_driver vc4_crtc_driver = {
1362         .probe = vc4_crtc_dev_probe,
1363         .remove = vc4_crtc_dev_remove,
1364         .driver = {
1365                 .name = "vc4_crtc",
1366                 .of_match_table = vc4_crtc_dt_match,
1367         },
1368 };