drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_atomic_uapi.h>
  40 #include <drm/drm_fb_dma_helper.h>
  41 #include <drm/drm_framebuffer.h>
  42 #include <drm/drm_drv.h>
  43 #include <drm/drm_print.h>
  44 #include <drm/drm_probe_helper.h>
  45 #include <drm/drm_vblank.h>
  46
  47 #include "vc4_drv.h"
  48 #include "vc4_hdmi.h"
  49 #include "vc4_regs.h"
  50
  51 #define HVS_FIFO_LATENCY_PIX    6
  52
  53 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  54 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  55
  56 static const struct debugfs_reg32 crtc_regs[] = {
  57         VC4_REG32(PV_CONTROL),
  58         VC4_REG32(PV_V_CONTROL),
  59         VC4_REG32(PV_VSYNCD_EVEN),
  60         VC4_REG32(PV_HORZA),
  61         VC4_REG32(PV_HORZB),
  62         VC4_REG32(PV_VERTA),
  63         VC4_REG32(PV_VERTB),
  64         VC4_REG32(PV_VERTA_EVEN),
  65         VC4_REG32(PV_VERTB_EVEN),
  66         VC4_REG32(PV_INTEN),
  67         VC4_REG32(PV_INTSTAT),
  68         VC4_REG32(PV_STAT),
  69         VC4_REG32(PV_HACT_ACT),
  70 };
  71
  72 static unsigned int
  73 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
  74 {
  75         struct vc4_hvs *hvs = vc4->hvs;
  76         u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  77         /* Top/base are supposed to be 4-pixel aligned, but the
  78          * Raspberry Pi firmware fills the low bits (which are
  79          * presumably ignored).
  80          */
  81         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  82         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  83
  84         return top - base + 4;
  85 }
  86
  87 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
  88                                           bool in_vblank_irq,
  89                                           int *vpos, int *hpos,
  90                                           ktime_t *stime, ktime_t *etime,
  91                                           const struct drm_display_mode *mode)
  92 {
  93         struct drm_device *dev = crtc->dev;
  94         struct vc4_dev *vc4 = to_vc4_dev(dev);
  95         struct vc4_hvs *hvs = vc4->hvs;
  96         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  97         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
  98         unsigned int cob_size;
  99         u32 val;
 100         int fifo_lines;
 101         int vblank_lines;
 102         bool ret = false;
 103
 104         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 105
 106         /* Get optional system timestamp before query. */
 107         if (stime)
 108                 *stime = ktime_get();
 109
 110         /*
 111          * Read vertical scanline which is currently composed for our
 112          * pixelvalve by the HVS, and also the scaler status.
 113          */
 114         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
 115
 116         /* Get optional system timestamp after query. */
 117         if (etime)
 118                 *etime = ktime_get();
 119
 120         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 121
 122         /* Vertical position of hvs composed scanline. */
 123         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 124         *hpos = 0;
 125
 126         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 127                 *vpos /= 2;
 128
 129                 /* Use hpos to correct for field offset in interlaced mode. */
 130                 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2)
 131                         *hpos += mode->crtc_htotal / 2;
 132         }
 133
 134         cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
 135         /* This is the offset we need for translating hvs -> pv scanout pos. */
 136         fifo_lines = cob_size / mode->crtc_hdisplay;
 137
 138         if (fifo_lines > 0)
 139                 ret = true;
 140
 141         /* HVS more than fifo_lines into frame for compositing? */
 142         if (*vpos > fifo_lines) {
 143                 /*
 144                  * We are in active scanout and can get some meaningful results
 145                  * from HVS. The actual PV scanout can not trail behind more
 146                  * than fifo_lines as that is the fifo's capacity. Assume that
 147                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 148                  * refilling the fifo and PV consuming from the fifo, ie.
 149                  * whenever the PV consumes and frees up a scanline in the
 150                  * fifo, the HVS will immediately refill it, therefore
 151                  * incrementing vpos. Therefore we choose HVS read position -
 152                  * fifo size in scanlines as a estimate of the real scanout
 153                  * position of the PV.
 154                  */
 155                 *vpos -= fifo_lines + 1;
 156
 157                 return ret;
 158         }
 159
 160         /*
 161          * Less: This happens when we are in vblank and the HVS, after getting
 162          * the VSTART restart signal from the PV, just started refilling its
 163          * fifo with new lines from the top-most lines of the new framebuffers.
 164          * The PV does not scan out in vblank, so does not remove lines from
 165          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 166          * We can't get meaningful readings wrt. scanline position of the PV
 167          * and need to make things up in a approximative but consistent way.
 168          */
 169         vblank_lines = mode->vtotal - mode->vdisplay;
 170
 171         if (in_vblank_irq) {
 172                 /*
 173                  * Assume the irq handler got called close to first
 174                  * line of vblank, so PV has about a full vblank
 175                  * scanlines to go, and as a base timestamp use the
 176                  * one taken at entry into vblank irq handler, so it
 177                  * is not affected by random delays due to lock
 178                  * contention on event_lock or vblank_time lock in
 179                  * the core.
 180                  */
 181                 *vpos = -vblank_lines;
 182
 183                 if (stime)
 184                         *stime = vc4_crtc->t_vblank;
 185                 if (etime)
 186                         *etime = vc4_crtc->t_vblank;
 187
 188                 /*
 189                  * If the HVS fifo is not yet full then we know for certain
 190                  * we are at the very beginning of vblank, as the hvs just
 191                  * started refilling, and the stime and etime timestamps
 192                  * truly correspond to start of vblank.
 193                  *
 194                  * Unfortunately there's no way to report this to upper levels
 195                  * and make it more useful.
 196                  */
 197         } else {
 198                 /*
 199                  * No clue where we are inside vblank. Return a vpos of zero,
 200                  * which will cause calling code to just return the etime
 201                  * timestamp uncorrected. At least this is no worse than the
 202                  * standard fallback.
 203                  */
 204                 *vpos = 0;
 205         }
 206
 207         return ret;
 208 }
 209
 210 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 211 {
 212         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
 213         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 214         struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
 215         u32 fifo_len_bytes = pv_data->fifo_depth;
 216
 217         /*
 218          * Pixels are pulled from the HVS if the number of bytes is
 219          * lower than the FIFO full level.
 220          *
 221          * The latency of the pixel fetch mechanism is 6 pixels, so we
 222          * need to convert those 6 pixels in bytes, depending on the
 223          * format, and then subtract that from the length of the FIFO
 224          * to make sure we never end up in a situation where the FIFO
 225          * is full.
 226          */
 227         switch (format) {
 228         case PV_CONTROL_FORMAT_DSIV_16:
 229         case PV_CONTROL_FORMAT_DSIC_16:
 230                 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
 231         case PV_CONTROL_FORMAT_DSIV_18:
 232                 return fifo_len_bytes - 14;
 233         case PV_CONTROL_FORMAT_24:
 234         case PV_CONTROL_FORMAT_DSIV_24:
 235         default:
 236                 /*
 237                  * For some reason, the pixelvalve4 doesn't work with
 238                  * the usual formula and will only work with 32.
 239                  */
 240                 if (crtc_data->hvs_output == 5)
 241                         return 32;
 242
 243                 /*
 244                  * It looks like in some situations, we will overflow
 245                  * the PixelValve FIFO (with the bit 10 of PV stat being
 246                  * set) and stall the HVS / PV, eventually resulting in
 247                  * a page flip timeout.
 248                  *
 249                  * Displaying the video overlay during a playback with
 250                  * Kodi on an RPi3 seems to be a great solution with a
 251                  * failure rate around 50%.
 252                  *
 253                  * Removing 1 from the FIFO full level however
 254                  * seems to completely remove that issue.
 255                  */
 256                 if (!vc4->is_vc5)
 257                         return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
 258
 259                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 260         }
 261 }
 262
 263 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
 264                                              u32 format)
 265 {
 266         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
 267         u32 ret = 0;
 268
 269         ret |= VC4_SET_FIELD((level >> 6),
 270                              PV5_CONTROL_FIFO_LEVEL_HIGH);
 271
 272         return ret | VC4_SET_FIELD(level & 0x3f,
 273                                    PV_CONTROL_FIFO_LEVEL);
 274 }
 275
 276 /*
 277  * Returns the encoder attached to the CRTC.
 278  *
 279  * VC4 can only scan out to one encoder at a time, while the DRM core
 280  * allows drivers to push pixels to more than one encoder from the
 281  * same CRTC.
 282  */
 283 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
 284                                          struct drm_crtc_state *state)
 285 {
 286         struct drm_encoder *encoder;
 287
 288         WARN_ON(hweight32(state->encoder_mask) > 1);
 289
 290         drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
 291                 return encoder;
 292
 293         return NULL;
 294 }
 295
 296 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
 297 {
 298         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 299         struct drm_device *dev = crtc->dev;
 300         int idx;
 301
 302         if (!drm_dev_enter(dev, &idx))
 303                 return;
 304
 305         /* The PV needs to be disabled before it can be flushed */
 306         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
 307         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
 308
 309         drm_dev_exit(idx);
 310 }
 311
 312 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder,
 313                                struct drm_atomic_state *state)
 314 {
 315         struct drm_device *dev = crtc->dev;
 316         struct vc4_dev *vc4 = to_vc4_dev(dev);
 317         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 318         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 319         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 320         struct drm_crtc_state *crtc_state = crtc->state;
 321         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 322         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 323         bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 ||
 324                        vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1;
 325         u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1;
 326         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 327                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 328         bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
 329         u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 330         u8 ppc = pv_data->pixels_per_clock;
 331         bool debug_dump_regs = false;
 332         int idx;
 333
 334         if (!drm_dev_enter(dev, &idx))
 335                 return;
 336
 337         if (debug_dump_regs) {
 338                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 339                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 340                          drm_crtc_index(crtc));
 341                 drm_print_regset32(&p, &vc4_crtc->regset);
 342         }
 343
 344         vc4_crtc_pixelvalve_reset(crtc);
 345
 346         CRTC_WRITE(PV_HORZA,
 347                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 348                                  PV_HORZA_HBP) |
 349                    VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
 350                                  PV_HORZA_HSYNC));
 351
 352         CRTC_WRITE(PV_HORZB,
 353                    VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
 354                                  PV_HORZB_HFP) |
 355                    VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
 356                                  PV_HORZB_HACTIVE));
 357
 358         CRTC_WRITE(PV_VERTA,
 359                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
 360                                  interlace,
 361                                  PV_VERTA_VBP) |
 362                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 363                                  PV_VERTA_VSYNC));
 364         CRTC_WRITE(PV_VERTB,
 365                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 366                                  PV_VERTB_VFP) |
 367                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 368
 369         if (interlace) {
 370                 CRTC_WRITE(PV_VERTA_EVEN,
 371                            VC4_SET_FIELD(mode->crtc_vtotal -
 372                                          mode->crtc_vsync_end,
 373                                          PV_VERTA_VBP) |
 374                            VC4_SET_FIELD(mode->crtc_vsync_end -
 375                                          mode->crtc_vsync_start,
 376                                          PV_VERTA_VSYNC));
 377                 CRTC_WRITE(PV_VERTB_EVEN,
 378                            VC4_SET_FIELD(mode->crtc_vsync_start -
 379                                          mode->crtc_vdisplay,
 380                                          PV_VERTB_VFP) |
 381                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 382
 383                 /* We set up first field even mode for HDMI.  VEC's
 384                  * NTSC mode would want first field odd instead, once
 385                  * we support it (to do so, set ODD_FIRST and put the
 386                  * delay in VSYNCD_EVEN instead).
 387                  */
 388                 CRTC_WRITE(PV_V_CONTROL,
 389                            PV_VCONTROL_CONTINUOUS |
 390                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 391                            PV_VCONTROL_INTERLACE |
 392                            VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc),
 393                                          PV_VCONTROL_ODD_DELAY));
 394                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 395         } else {
 396                 CRTC_WRITE(PV_V_CONTROL,
 397                            PV_VCONTROL_CONTINUOUS |
 398                            (is_dsi ? PV_VCONTROL_DSI : 0));
 399         }
 400
 401         if (is_dsi)
 402                 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 403
 404         if (vc4->is_vc5)
 405                 CRTC_WRITE(PV_MUX_CFG,
 406                            VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
 407                                          PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
 408
 409         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
 410                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 411                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 412                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 413                    PV_CONTROL_CLR_AT_START |
 414                    PV_CONTROL_TRIGGER_UNDERFLOW |
 415                    PV_CONTROL_WAIT_HSTART |
 416                    VC4_SET_FIELD(vc4_encoder->clock_select,
 417                                  PV_CONTROL_CLK_SELECT));
 418
 419         if (debug_dump_regs) {
 420                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 421                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 422                          drm_crtc_index(crtc));
 423                 drm_print_regset32(&p, &vc4_crtc->regset);
 424         }
 425
 426         drm_dev_exit(idx);
 427 }
 428
 429 static void require_hvs_enabled(struct drm_device *dev)
 430 {
 431         struct vc4_dev *vc4 = to_vc4_dev(dev);
 432         struct vc4_hvs *hvs = vc4->hvs;
 433
 434         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 435                      SCALER_DISPCTRL_ENABLE);
 436 }
 437
 438 static int vc4_crtc_disable(struct drm_crtc *crtc,
 439                             struct drm_encoder *encoder,
 440                             struct drm_atomic_state *state,
 441                             unsigned int channel)
 442 {
 443         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 444         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 445         struct drm_device *dev = crtc->dev;
 446         struct vc4_dev *vc4 = to_vc4_dev(dev);
 447         int idx, ret;
 448
 449         if (!drm_dev_enter(dev, &idx))
 450                 return -ENODEV;
 451
 452         CRTC_WRITE(PV_V_CONTROL,
 453                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 454         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 455         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 456
 457         /*
 458          * This delay is needed to avoid to get a pixel stuck in an
 459          * unflushable FIFO between the pixelvalve and the HDMI
 460          * controllers on the BCM2711.
 461          *
 462          * Timing is fairly sensitive here, so mdelay is the safest
 463          * approach.
 464          *
 465          * If it was to be reworked, the stuck pixel happens on a
 466          * BCM2711 when changing mode with a good probability, so a
 467          * script that changes mode on a regular basis should trigger
 468          * the bug after less than 10 attempts. It manifests itself with
 469          * every pixels being shifted by one to the right, and thus the
 470          * last pixel of a line actually being displayed as the first
 471          * pixel on the next line.
 472          */
 473         mdelay(20);
 474
 475         if (vc4_encoder && vc4_encoder->post_crtc_disable)
 476                 vc4_encoder->post_crtc_disable(encoder, state);
 477
 478         vc4_crtc_pixelvalve_reset(crtc);
 479         vc4_hvs_stop_channel(vc4->hvs, channel);
 480
 481         if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
 482                 vc4_encoder->post_crtc_powerdown(encoder, state);
 483
 484         drm_dev_exit(idx);
 485
 486         return 0;
 487 }
 488
 489 static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc,
 490                                                         enum vc4_encoder_type type)
 491 {
 492         struct drm_encoder *encoder;
 493
 494         drm_for_each_encoder(encoder, crtc->dev) {
 495                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 496
 497                 if (vc4_encoder->type == type)
 498                         return encoder;
 499         }
 500
 501         return NULL;
 502 }
 503
 504 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
 505 {
 506         struct drm_device *drm = crtc->dev;
 507         struct vc4_dev *vc4 = to_vc4_dev(drm);
 508         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 509         enum vc4_encoder_type encoder_type;
 510         const struct vc4_pv_data *pv_data;
 511         struct drm_encoder *encoder;
 512         struct vc4_hdmi *vc4_hdmi;
 513         unsigned encoder_sel;
 514         int channel;
 515         int ret;
 516
 517         if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 518                                       "brcm,bcm2711-pixelvalve2") ||
 519               of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 520                                       "brcm,bcm2711-pixelvalve4")))
 521                 return 0;
 522
 523         if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
 524                 return 0;
 525
 526         if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
 527                 return 0;
 528
 529         channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
 530         if (channel < 0)
 531                 return 0;
 532
 533         encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
 534         if (WARN_ON(encoder_sel != 0))
 535                 return 0;
 536
 537         pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 538         encoder_type = pv_data->encoder_types[encoder_sel];
 539         encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type);
 540         if (WARN_ON(!encoder))
 541                 return 0;
 542
 543         vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 544         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 545         if (ret)
 546                 return ret;
 547
 548         ret = vc4_crtc_disable(crtc, encoder, NULL, channel);
 549         if (ret)
 550                 return ret;
 551
 552         /*
 553          * post_crtc_powerdown will have called pm_runtime_put, so we
 554          * don't need it here otherwise we'll get the reference counting
 555          * wrong.
 556          */
 557
 558         return 0;
 559 }
 560
 561 void vc4_crtc_send_vblank(struct drm_crtc *crtc)
 562 {
 563         struct drm_device *dev = crtc->dev;
 564         unsigned long flags;
 565
 566         if (!crtc->state || !crtc->state->event)
 567                 return;
 568
 569         spin_lock_irqsave(&dev->event_lock, flags);
 570         drm_crtc_send_vblank_event(crtc, crtc->state->event);
 571         crtc->state->event = NULL;
 572         spin_unlock_irqrestore(&dev->event_lock, flags);
 573 }
 574
 575 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 576                                     struct drm_atomic_state *state)
 577 {
 578         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
 579                                                                          crtc);
 580         struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
 581         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);
 582         struct drm_device *dev = crtc->dev;
 583
 584         drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)",
 585                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 586
 587         require_hvs_enabled(dev);
 588
 589         /* Disable vblank irq handling before crtc is disabled. */
 590         drm_crtc_vblank_off(crtc);
 591
 592         vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
 593
 594         /*
 595          * Make sure we issue a vblank event after disabling the CRTC if
 596          * someone was waiting it.
 597          */
 598         vc4_crtc_send_vblank(crtc);
 599 }
 600
 601 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 602                                    struct drm_atomic_state *state)
 603 {
 604         struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,
 605                                                                          crtc);
 606         struct drm_device *dev = crtc->dev;
 607         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 608         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);
 609         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 610         int idx;
 611
 612         drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)",
 613                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 614
 615         if (!drm_dev_enter(dev, &idx))
 616                 return;
 617
 618         require_hvs_enabled(dev);
 619
 620         /* Enable vblank irq handling before crtc is started otherwise
 621          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 622          */
 623         drm_crtc_vblank_on(crtc);
 624
 625         vc4_hvs_atomic_enable(crtc, state);
 626
 627         if (vc4_encoder->pre_crtc_configure)
 628                 vc4_encoder->pre_crtc_configure(encoder, state);
 629
 630         vc4_crtc_config_pv(crtc, encoder, state);
 631
 632         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
 633
 634         if (vc4_encoder->pre_crtc_enable)
 635                 vc4_encoder->pre_crtc_enable(encoder, state);
 636
 637         /* When feeding the transposer block the pixelvalve is unneeded and
 638          * should not be enabled.
 639          */
 640         CRTC_WRITE(PV_V_CONTROL,
 641                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 642
 643         if (vc4_encoder->post_crtc_enable)
 644                 vc4_encoder->post_crtc_enable(encoder, state);
 645
 646         drm_dev_exit(idx);
 647 }
 648
 649 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 650                                                 const struct drm_display_mode *mode)
 651 {
 652         /* Do not allow doublescan modes from user space */
 653         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 654                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 655                               crtc->base.id);
 656                 return MODE_NO_DBLESCAN;
 657         }
 658
 659         return MODE_OK;
 660 }
 661
 662 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 663                           unsigned int *left, unsigned int *right,
 664                           unsigned int *top, unsigned int *bottom)
 665 {
 666         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 667         struct drm_connector_state *conn_state;
 668         struct drm_connector *conn;
 669         int i;
 670
 671         *left = vc4_state->margins.left;
 672         *right = vc4_state->margins.right;
 673         *top = vc4_state->margins.top;
 674         *bottom = vc4_state->margins.bottom;
 675
 676         /* We have to interate over all new connector states because
 677          * vc4_crtc_get_margins() might be called before
 678          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 679          * might be outdated.
 680          */
 681         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 682                 if (conn_state->crtc != state->crtc)
 683                         continue;
 684
 685                 *left = conn_state->tv.margins.left;
 686                 *right = conn_state->tv.margins.right;
 687                 *top = conn_state->tv.margins.top;
 688                 *bottom = conn_state->tv.margins.bottom;
 689                 break;
 690         }
 691 }
 692
 693 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 694                                  struct drm_atomic_state *state)
 695 {
 696         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 697                                                                           crtc);
 698         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 699         struct drm_connector *conn;
 700         struct drm_connector_state *conn_state;
 701         struct drm_encoder *encoder;
 702         int ret, i;
 703
 704         ret = vc4_hvs_atomic_check(crtc, state);
 705         if (ret)
 706                 return ret;
 707
 708         encoder = vc4_get_crtc_encoder(crtc, crtc_state);
 709         if (encoder) {
 710                 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 711                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 712
 713                 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
 714                         vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,
 715                                                   mode->clock * 9 / 10) * 1000;
 716                 } else {
 717                         vc4_state->hvs_load = mode->clock * 1000;
 718                 }
 719         }
 720
 721         for_each_new_connector_in_state(state, conn, conn_state,
 722                                         i) {
 723                 if (conn_state->crtc != crtc)
 724                         continue;
 725
 726                 vc4_state->margins.left = conn_state->tv.margins.left;
 727                 vc4_state->margins.right = conn_state->tv.margins.right;
 728                 vc4_state->margins.top = conn_state->tv.margins.top;
 729                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 730                 break;
 731         }
 732
 733         return 0;
 734 }
 735
 736 static int vc4_enable_vblank(struct drm_crtc *crtc)
 737 {
 738         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 739         struct drm_device *dev = crtc->dev;
 740         int idx;
 741
 742         if (!drm_dev_enter(dev, &idx))
 743                 return -ENODEV;
 744
 745         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 746
 747         drm_dev_exit(idx);
 748
 749         return 0;
 750 }
 751
 752 static void vc4_disable_vblank(struct drm_crtc *crtc)
 753 {
 754         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 755         struct drm_device *dev = crtc->dev;
 756         int idx;
 757
 758         if (!drm_dev_enter(dev, &idx))
 759                 return;
 760
 761         CRTC_WRITE(PV_INTEN, 0);
 762
 763         drm_dev_exit(idx);
 764 }
 765
 766 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 767 {
 768         struct drm_crtc *crtc = &vc4_crtc->base;
 769         struct drm_device *dev = crtc->dev;
 770         struct vc4_dev *vc4 = to_vc4_dev(dev);
 771         struct vc4_hvs *hvs = vc4->hvs;
 772         u32 chan = vc4_crtc->current_hvs_channel;
 773         unsigned long flags;
 774
 775         spin_lock_irqsave(&dev->event_lock, flags);
 776         spin_lock(&vc4_crtc->irq_lock);
 777         if (vc4_crtc->event &&
 778             (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) ||
 779              vc4_crtc->feeds_txp)) {
 780                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 781                 vc4_crtc->event = NULL;
 782                 drm_crtc_vblank_put(crtc);
 783
 784                 /* Wait for the page flip to unmask the underrun to ensure that
 785                  * the display list was updated by the hardware. Before that
 786                  * happens, the HVS will be using the previous display list with
 787                  * the CRTC and encoder already reconfigured, leading to
 788                  * underruns. This can be seen when reconfiguring the CRTC.
 789                  */
 790                 vc4_hvs_unmask_underrun(hvs, chan);
 791         }
 792         spin_unlock(&vc4_crtc->irq_lock);
 793         spin_unlock_irqrestore(&dev->event_lock, flags);
 794 }
 795
 796 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 797 {
 798         crtc->t_vblank = ktime_get();
 799         drm_crtc_handle_vblank(&crtc->base);
 800         vc4_crtc_handle_page_flip(crtc);
 801 }
 802
 803 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 804 {
 805         struct vc4_crtc *vc4_crtc = data;
 806         u32 stat = CRTC_READ(PV_INTSTAT);
 807         irqreturn_t ret = IRQ_NONE;
 808
 809         if (stat & PV_INT_VFP_START) {
 810                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 811                 vc4_crtc_handle_vblank(vc4_crtc);
 812                 ret = IRQ_HANDLED;
 813         }
 814
 815         return ret;
 816 }
 817
 818 struct vc4_async_flip_state {
 819         struct drm_crtc *crtc;
 820         struct drm_framebuffer *fb;
 821         struct drm_framebuffer *old_fb;
 822         struct drm_pending_vblank_event *event;
 823
 824         union {
 825                 struct dma_fence_cb fence;
 826                 struct vc4_seqno_cb seqno;
 827         } cb;
 828 };
 829
 830 /* Called when the V3D execution for the BO being flipped to is done, so that
 831  * we can actually update the plane's address to point to it.
 832  */
 833 static void
 834 vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
 835 {
 836         struct drm_crtc *crtc = flip_state->crtc;
 837         struct drm_device *dev = crtc->dev;
 838         struct drm_plane *plane = crtc->primary;
 839
 840         vc4_plane_async_set_fb(plane, flip_state->fb);
 841         if (flip_state->event) {
 842                 unsigned long flags;
 843
 844                 spin_lock_irqsave(&dev->event_lock, flags);
 845                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 846                 spin_unlock_irqrestore(&dev->event_lock, flags);
 847         }
 848
 849         drm_crtc_vblank_put(crtc);
 850         drm_framebuffer_put(flip_state->fb);
 851
 852         if (flip_state->old_fb)
 853                 drm_framebuffer_put(flip_state->old_fb);
 854
 855         kfree(flip_state);
 856 }
 857
 858 static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 859 {
 860         struct vc4_async_flip_state *flip_state =
 861                 container_of(cb, struct vc4_async_flip_state, cb.seqno);
 862         struct vc4_bo *bo = NULL;
 863
 864         if (flip_state->old_fb) {
 865                 struct drm_gem_dma_object *dma_bo =
 866                         drm_fb_dma_get_gem_obj(flip_state->old_fb, 0);
 867                 bo = to_vc4_bo(&dma_bo->base);
 868         }
 869
 870         vc4_async_page_flip_complete(flip_state);
 871
 872         /*
 873          * Decrement the BO usecnt in order to keep the inc/dec
 874          * calls balanced when the planes are updated through
 875          * the async update path.
 876          *
 877          * FIXME: we should move to generic async-page-flip when
 878          * it's available, so that we can get rid of this
 879          * hand-made cleanup_fb() logic.
 880          */
 881         if (bo)
 882                 vc4_bo_dec_usecnt(bo);
 883 }
 884
 885 static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
 886                                                struct dma_fence_cb *cb)
 887 {
 888         struct vc4_async_flip_state *flip_state =
 889                 container_of(cb, struct vc4_async_flip_state, cb.fence);
 890
 891         vc4_async_page_flip_complete(flip_state);
 892         dma_fence_put(fence);
 893 }
 894
 895 static int vc4_async_set_fence_cb(struct drm_device *dev,
 896                                   struct vc4_async_flip_state *flip_state)
 897 {
 898         struct drm_framebuffer *fb = flip_state->fb;
 899         struct drm_gem_dma_object *dma_bo = drm_fb_dma_get_gem_obj(fb, 0);
 900         struct vc4_dev *vc4 = to_vc4_dev(dev);
 901         struct dma_fence *fence;
 902         int ret;
 903
 904         if (!vc4->is_vc5) {
 905                 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
 906
 907                 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
 908                                           vc4_async_page_flip_seqno_complete);
 909         }
 910
 911         ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
 912         if (ret)
 913                 return ret;
 914
 915         /* If there's no fence, complete the page flip immediately */
 916         if (!fence) {
 917                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 918                 return 0;
 919         }
 920
 921         /* If the fence has already been completed, complete the page flip */
 922         if (dma_fence_add_callback(fence, &flip_state->cb.fence,
 923                                    vc4_async_page_flip_fence_complete))
 924                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 925
 926         return 0;
 927 }
 928
 929 static int
 930 vc4_async_page_flip_common(struct drm_crtc *crtc,
 931                            struct drm_framebuffer *fb,
 932                            struct drm_pending_vblank_event *event,
 933                            uint32_t flags)
 934 {
 935         struct drm_device *dev = crtc->dev;
 936         struct drm_plane *plane = crtc->primary;
 937         struct vc4_async_flip_state *flip_state;
 938
 939         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 940         if (!flip_state)
 941                 return -ENOMEM;
 942
 943         drm_framebuffer_get(fb);
 944         flip_state->fb = fb;
 945         flip_state->crtc = crtc;
 946         flip_state->event = event;
 947
 948         /* Save the current FB before it's replaced by the new one in
 949          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 950          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 951          * it consistent.
 952          * FIXME: we should move to generic async-page-flip when it's
 953          * available, so that we can get rid of this hand-made cleanup_fb()
 954          * logic.
 955          */
 956         flip_state->old_fb = plane->state->fb;
 957         if (flip_state->old_fb)
 958                 drm_framebuffer_get(flip_state->old_fb);
 959
 960         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 961
 962         /* Immediately update the plane's legacy fb pointer, so that later
 963          * modeset prep sees the state that will be present when the semaphore
 964          * is released.
 965          */
 966         drm_atomic_set_fb_for_plane(plane->state, fb);
 967
 968         vc4_async_set_fence_cb(dev, flip_state);
 969
 970         /* Driver takes ownership of state on successful async commit. */
 971         return 0;
 972 }
 973
 974 /* Implements async (non-vblank-synced) page flips.
 975  *
 976  * The page flip ioctl needs to return immediately, so we grab the
 977  * modeset semaphore on the pipe, and queue the address update for
 978  * when V3D is done with the BO being flipped to.
 979  */
 980 static int vc4_async_page_flip(struct drm_crtc *crtc,
 981                                struct drm_framebuffer *fb,
 982                                struct drm_pending_vblank_event *event,
 983                                uint32_t flags)
 984 {
 985         struct drm_device *dev = crtc->dev;
 986         struct vc4_dev *vc4 = to_vc4_dev(dev);
 987         struct drm_gem_dma_object *dma_bo = drm_fb_dma_get_gem_obj(fb, 0);
 988         struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
 989         int ret;
 990
 991         if (WARN_ON_ONCE(vc4->is_vc5))
 992                 return -ENODEV;
 993
 994         /*
 995          * Increment the BO usecnt here, so that we never end up with an
 996          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 997          * plane is later updated through the non-async path.
 998          *
 999          * FIXME: we should move to generic async-page-flip when
1000          * it's available, so that we can get rid of this
1001          * hand-made prepare_fb() logic.
1002          */
1003         ret = vc4_bo_inc_usecnt(bo);
1004         if (ret)
1005                 return ret;
1006
1007         ret = vc4_async_page_flip_common(crtc, fb, event, flags);
1008         if (ret) {
1009                 vc4_bo_dec_usecnt(bo);
1010                 return ret;
1011         }
1012
1013         return 0;
1014 }
1015
1016 static int vc5_async_page_flip(struct drm_crtc *crtc,
1017                                struct drm_framebuffer *fb,
1018                                struct drm_pending_vblank_event *event,
1019                                uint32_t flags)
1020 {
1021         return vc4_async_page_flip_common(crtc, fb, event, flags);
1022 }
1023
1024 int vc4_page_flip(struct drm_crtc *crtc,
1025                   struct drm_framebuffer *fb,
1026                   struct drm_pending_vblank_event *event,
1027                   uint32_t flags,
1028                   struct drm_modeset_acquire_ctx *ctx)
1029 {
1030         if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
1031                 struct drm_device *dev = crtc->dev;
1032                 struct vc4_dev *vc4 = to_vc4_dev(dev);
1033
1034                 if (vc4->is_vc5)
1035                         return vc5_async_page_flip(crtc, fb, event, flags);
1036                 else
1037                         return vc4_async_page_flip(crtc, fb, event, flags);
1038         } else {
1039                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
1040         }
1041 }
1042
1043 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
1044 {
1045         struct vc4_crtc_state *vc4_state, *old_vc4_state;
1046
1047         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1048         if (!vc4_state)
1049                 return NULL;
1050
1051         old_vc4_state = to_vc4_crtc_state(crtc->state);
1052         vc4_state->margins = old_vc4_state->margins;
1053         vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1054
1055         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1056         return &vc4_state->base;
1057 }
1058
1059 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1060                             struct drm_crtc_state *state)
1061 {
1062         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1063         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1064
1065         if (drm_mm_node_allocated(&vc4_state->mm)) {
1066                 unsigned long flags;
1067
1068                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1069                 drm_mm_remove_node(&vc4_state->mm);
1070                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1071
1072         }
1073
1074         drm_atomic_helper_crtc_destroy_state(crtc, state);
1075 }
1076
1077 void vc4_crtc_reset(struct drm_crtc *crtc)
1078 {
1079         struct vc4_crtc_state *vc4_crtc_state;
1080
1081         if (crtc->state)
1082                 vc4_crtc_destroy_state(crtc, crtc->state);
1083
1084         vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
1085         if (!vc4_crtc_state) {
1086                 crtc->state = NULL;
1087                 return;
1088         }
1089
1090         vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
1091         __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
1092 }
1093
1094 int vc4_crtc_late_register(struct drm_crtc *crtc)
1095 {
1096         struct drm_device *drm = crtc->dev;
1097         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1098         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
1099         int ret;
1100
1101         ret = vc4_debugfs_add_regset32(drm->primary, crtc_data->debugfs_name,
1102                                        &vc4_crtc->regset);
1103         if (ret)
1104                 return ret;
1105
1106         return 0;
1107 }
1108
1109 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1110         .set_config = drm_atomic_helper_set_config,
1111         .page_flip = vc4_page_flip,
1112         .set_property = NULL,
1113         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1114         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1115         .reset = vc4_crtc_reset,
1116         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1117         .atomic_destroy_state = vc4_crtc_destroy_state,
1118         .enable_vblank = vc4_enable_vblank,
1119         .disable_vblank = vc4_disable_vblank,
1120         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1121         .late_register = vc4_crtc_late_register,
1122 };
1123
1124 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1125         .mode_valid = vc4_crtc_mode_valid,
1126         .atomic_check = vc4_crtc_atomic_check,
1127         .atomic_begin = vc4_hvs_atomic_begin,
1128         .atomic_flush = vc4_hvs_atomic_flush,
1129         .atomic_enable = vc4_crtc_atomic_enable,
1130         .atomic_disable = vc4_crtc_atomic_disable,
1131         .get_scanout_position = vc4_crtc_get_scanout_position,
1132 };
1133
1134 static const struct vc4_pv_data bcm2835_pv0_data = {
1135         .base = {
1136                 .debugfs_name = "crtc0_regs",
1137                 .hvs_available_channels = BIT(0),
1138                 .hvs_output = 0,
1139         },
1140         .fifo_depth = 64,
1141         .pixels_per_clock = 1,
1142         .encoder_types = {
1143                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1144                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1145         },
1146 };
1147
1148 static const struct vc4_pv_data bcm2835_pv1_data = {
1149         .base = {
1150                 .debugfs_name = "crtc1_regs",
1151                 .hvs_available_channels = BIT(2),
1152                 .hvs_output = 2,
1153         },
1154         .fifo_depth = 64,
1155         .pixels_per_clock = 1,
1156         .encoder_types = {
1157                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1158                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1159         },
1160 };
1161
1162 static const struct vc4_pv_data bcm2835_pv2_data = {
1163         .base = {
1164                 .debugfs_name = "crtc2_regs",
1165                 .hvs_available_channels = BIT(1),
1166                 .hvs_output = 1,
1167         },
1168         .fifo_depth = 64,
1169         .pixels_per_clock = 1,
1170         .encoder_types = {
1171                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
1172                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1173         },
1174 };
1175
1176 static const struct vc4_pv_data bcm2711_pv0_data = {
1177         .base = {
1178                 .debugfs_name = "crtc0_regs",
1179                 .hvs_available_channels = BIT(0),
1180                 .hvs_output = 0,
1181         },
1182         .fifo_depth = 64,
1183         .pixels_per_clock = 1,
1184         .encoder_types = {
1185                 [0] = VC4_ENCODER_TYPE_DSI0,
1186                 [1] = VC4_ENCODER_TYPE_DPI,
1187         },
1188 };
1189
1190 static const struct vc4_pv_data bcm2711_pv1_data = {
1191         .base = {
1192                 .debugfs_name = "crtc1_regs",
1193                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1194                 .hvs_output = 3,
1195         },
1196         .fifo_depth = 64,
1197         .pixels_per_clock = 1,
1198         .encoder_types = {
1199                 [0] = VC4_ENCODER_TYPE_DSI1,
1200                 [1] = VC4_ENCODER_TYPE_SMI,
1201         },
1202 };
1203
1204 static const struct vc4_pv_data bcm2711_pv2_data = {
1205         .base = {
1206                 .debugfs_name = "crtc2_regs",
1207                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1208                 .hvs_output = 4,
1209         },
1210         .fifo_depth = 256,
1211         .pixels_per_clock = 2,
1212         .encoder_types = {
1213                 [0] = VC4_ENCODER_TYPE_HDMI0,
1214         },
1215 };
1216
1217 static const struct vc4_pv_data bcm2711_pv3_data = {
1218         .base = {
1219                 .debugfs_name = "crtc3_regs",
1220                 .hvs_available_channels = BIT(1),
1221                 .hvs_output = 1,
1222         },
1223         .fifo_depth = 64,
1224         .pixels_per_clock = 1,
1225         .encoder_types = {
1226                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1227         },
1228 };
1229
1230 static const struct vc4_pv_data bcm2711_pv4_data = {
1231         .base = {
1232                 .debugfs_name = "crtc4_regs",
1233                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1234                 .hvs_output = 5,
1235         },
1236         .fifo_depth = 64,
1237         .pixels_per_clock = 2,
1238         .encoder_types = {
1239                 [0] = VC4_ENCODER_TYPE_HDMI1,
1240         },
1241 };
1242
1243 static const struct of_device_id vc4_crtc_dt_match[] = {
1244         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1245         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1246         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1247         { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1248         { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1249         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1250         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1251         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1252         {}
1253 };
1254
1255 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1256                                         struct drm_crtc *crtc)
1257 {
1258         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1259         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1260         const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1261         struct drm_encoder *encoder;
1262
1263         drm_for_each_encoder(encoder, drm) {
1264                 struct vc4_encoder *vc4_encoder;
1265                 int i;
1266
1267                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1268                         continue;
1269
1270                 vc4_encoder = to_vc4_encoder(encoder);
1271                 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1272                         if (vc4_encoder->type == encoder_types[i]) {
1273                                 vc4_encoder->clock_select = i;
1274                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1275                                 break;
1276                         }
1277                 }
1278         }
1279 }
1280
1281 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1282                   const struct drm_crtc_funcs *crtc_funcs,
1283                   const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1284 {
1285         struct vc4_dev *vc4 = to_vc4_dev(drm);
1286         struct drm_crtc *crtc = &vc4_crtc->base;
1287         struct drm_plane *primary_plane;
1288         unsigned int i;
1289         int ret;
1290
1291         /* For now, we create just the primary and the legacy cursor
1292          * planes.  We should be able to stack more planes on easily,
1293          * but to do that we would need to compute the bandwidth
1294          * requirement of the plane configuration, and reject ones
1295          * that will take too much.
1296          */
1297         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY, 0);
1298         if (IS_ERR(primary_plane)) {
1299                 dev_err(drm->dev, "failed to construct primary plane\n");
1300                 return PTR_ERR(primary_plane);
1301         }
1302
1303         spin_lock_init(&vc4_crtc->irq_lock);
1304         ret = drmm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1305                                          crtc_funcs, NULL);
1306         if (ret)
1307                 return ret;
1308
1309         drm_crtc_helper_add(crtc, crtc_helper_funcs);
1310
1311         if (!vc4->is_vc5) {
1312                 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1313
1314                 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1315
1316                 /* We support CTM, but only for one CRTC at a time. It's therefore
1317                  * implemented as private driver state in vc4_kms, not here.
1318                  */
1319                 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1320         }
1321
1322         for (i = 0; i < crtc->gamma_size; i++) {
1323                 vc4_crtc->lut_r[i] = i;
1324                 vc4_crtc->lut_g[i] = i;
1325                 vc4_crtc->lut_b[i] = i;
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1332 {
1333         struct platform_device *pdev = to_platform_device(dev);
1334         struct drm_device *drm = dev_get_drvdata(master);
1335         const struct vc4_pv_data *pv_data;
1336         struct vc4_crtc *vc4_crtc;
1337         struct drm_crtc *crtc;
1338         int ret;
1339
1340         vc4_crtc = drmm_kzalloc(drm, sizeof(*vc4_crtc), GFP_KERNEL);
1341         if (!vc4_crtc)
1342                 return -ENOMEM;
1343         crtc = &vc4_crtc->base;
1344
1345         pv_data = of_device_get_match_data(dev);
1346         if (!pv_data)
1347                 return -ENODEV;
1348         vc4_crtc->data = &pv_data->base;
1349         vc4_crtc->pdev = pdev;
1350
1351         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1352         if (IS_ERR(vc4_crtc->regs))
1353                 return PTR_ERR(vc4_crtc->regs);
1354
1355         vc4_crtc->regset.base = vc4_crtc->regs;
1356         vc4_crtc->regset.regs = crtc_regs;
1357         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1358
1359         ret = vc4_crtc_init(drm, vc4_crtc,
1360                             &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1361         if (ret)
1362                 return ret;
1363         vc4_set_crtc_possible_masks(drm, crtc);
1364
1365         CRTC_WRITE(PV_INTEN, 0);
1366         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1367         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1368                                vc4_crtc_irq_handler,
1369                                IRQF_SHARED,
1370                                "vc4 crtc", vc4_crtc);
1371         if (ret)
1372                 return ret;
1373
1374         platform_set_drvdata(pdev, vc4_crtc);
1375
1376         return 0;
1377 }
1378
1379 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1380                             void *data)
1381 {
1382         struct platform_device *pdev = to_platform_device(dev);
1383         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1384
1385         CRTC_WRITE(PV_INTEN, 0);
1386
1387         platform_set_drvdata(pdev, NULL);
1388 }
1389
1390 static const struct component_ops vc4_crtc_ops = {
1391         .bind   = vc4_crtc_bind,
1392         .unbind = vc4_crtc_unbind,
1393 };
1394
1395 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1396 {
1397         return component_add(&pdev->dev, &vc4_crtc_ops);
1398 }
1399
1400 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1401 {
1402         component_del(&pdev->dev, &vc4_crtc_ops);
1403         return 0;
1404 }
1405
1406 struct platform_driver vc4_crtc_driver = {
1407         .probe = vc4_crtc_dev_probe,
1408         .remove = vc4_crtc_dev_remove,
1409         .driver = {
1410                 .name = "vc4_crtc",
1411                 .of_match_table = vc4_crtc_dt_match,
1412         },
1413 };