drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <asm/unaligned.h>
  14 #include <linux/bitfield.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  20 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  21                          PORT_RC | PORT_PLC | PORT_PE)
  22
  23 /* Default sublink speed attribute of each lane */
  24 static u32 ssp_cap_default_ssa[] = {
  25         0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
  26         0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
  27         0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
  28         0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
  29         0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
  30         0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
  31         0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
  32         0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
  33 };
  34
  35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf,
  36                                       u16 wLength)
  37 {
  38         struct usb_bos_descriptor       *bos;
  39         struct usb_ss_cap_descriptor    *ss_cap;
  40         struct usb_ssp_cap_descriptor   *ssp_cap;
  41         struct xhci_port_cap            *port_cap = NULL;
  42         u16                             bcdUSB;
  43         u32                             reg;
  44         u32                             min_rate = 0;
  45         u8                              min_ssid;
  46         u8                              ssac;
  47         u8                              ssic;
  48         int                             offset;
  49         int                             i;
  50
  51         /* BOS descriptor */
  52         bos = (struct usb_bos_descriptor *)buf;
  53         bos->bLength = USB_DT_BOS_SIZE;
  54         bos->bDescriptorType = USB_DT_BOS;
  55         bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
  56                                         USB_DT_USB_SS_CAP_SIZE);
  57         bos->bNumDeviceCaps = 1;
  58
  59         /* Create the descriptor for port with the highest revision */
  60         for (i = 0; i < xhci->num_port_caps; i++) {
  61                 u8 major = xhci->port_caps[i].maj_rev;
  62                 u8 minor = xhci->port_caps[i].min_rev;
  63                 u16 rev = (major << 8) | minor;
  64
  65                 if (i == 0 || bcdUSB < rev) {
  66                         bcdUSB = rev;
  67                         port_cap = &xhci->port_caps[i];
  68                 }
  69         }
  70
  71         if (bcdUSB >= 0x0310) {
  72                 if (port_cap->psi_count) {
  73                         u8 num_sym_ssa = 0;
  74
  75                         for (i = 0; i < port_cap->psi_count; i++) {
  76                                 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM)
  77                                         num_sym_ssa++;
  78                         }
  79
  80                         ssac = port_cap->psi_count + num_sym_ssa - 1;
  81                         ssic = port_cap->psi_uid_count - 1;
  82                 } else {
  83                         if (bcdUSB >= 0x0320)
  84                                 ssac = 7;
  85                         else
  86                                 ssac = 3;
  87
  88                         ssic = (ssac + 1) / 2 - 1;
  89                 }
  90
  91                 bos->bNumDeviceCaps++;
  92                 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
  93                                                 USB_DT_USB_SS_CAP_SIZE +
  94                                                 USB_DT_USB_SSP_CAP_SIZE(ssac));
  95         }
  96
  97         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  98                 return wLength;
  99
 100         /* SuperSpeed USB Device Capability */
 101         ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE];
 102         ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE;
 103         ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
 104         ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE;
 105         ss_cap->bmAttributes = 0; /* set later */
 106         ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION);
 107         ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION;
 108         ss_cap->bU1devExitLat = 0; /* set later */
 109         ss_cap->bU2DevExitLat = 0; /* set later */
 110
 111         reg = readl(&xhci->cap_regs->hcc_params);
 112         if (HCC_LTC(reg))
 113                 ss_cap->bmAttributes |= USB_LTM_SUPPORT;
 114
 115         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 116                 reg = readl(&xhci->cap_regs->hcs_params3);
 117                 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg);
 118                 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg));
 119         }
 120
 121         if (wLength < le16_to_cpu(bos->wTotalLength))
 122                 return wLength;
 123
 124         if (bcdUSB < 0x0310)
 125                 return le16_to_cpu(bos->wTotalLength);
 126
 127         ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE +
 128                 USB_DT_USB_SS_CAP_SIZE];
 129         ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac);
 130         ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
 131         ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE;
 132         ssp_cap->bReserved = 0;
 133         ssp_cap->wReserved = 0;
 134         ssp_cap->bmAttributes =
 135                 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) |
 136                             FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic));
 137
 138         if (!port_cap->psi_count) {
 139                 for (i = 0; i < ssac + 1; i++)
 140                         ssp_cap->bmSublinkSpeedAttr[i] =
 141                                 cpu_to_le32(ssp_cap_default_ssa[i]);
 142
 143                 min_ssid = 4;
 144                 goto out;
 145         }
 146
 147         offset = 0;
 148         for (i = 0; i < port_cap->psi_count; i++) {
 149                 u32 psi;
 150                 u32 attr;
 151                 u8 ssid;
 152                 u8 lp;
 153                 u8 lse;
 154                 u8 psie;
 155                 u16 lane_mantissa;
 156                 u16 psim;
 157                 u16 plt;
 158
 159                 psi = port_cap->psi[i];
 160                 ssid = XHCI_EXT_PORT_PSIV(psi);
 161                 lp = XHCI_EXT_PORT_LP(psi);
 162                 psie = XHCI_EXT_PORT_PSIE(psi);
 163                 psim = XHCI_EXT_PORT_PSIM(psi);
 164                 plt = psi & PLT_MASK;
 165
 166                 lse = psie;
 167                 lane_mantissa = psim;
 168
 169                 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
 170                 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++)
 171                         psim /= 1000;
 172
 173                 if (!min_rate || psim < min_rate) {
 174                         min_ssid = ssid;
 175                         min_rate = psim;
 176                 }
 177
 178                 /* Some host controllers don't set the link protocol for SSP */
 179                 if (psim >= 10)
 180                         lp = USB_SSP_SUBLINK_SPEED_LP_SSP;
 181
 182                 /*
 183                  * PSIM and PSIE represent the total speed of PSI. The BOS
 184                  * descriptor SSP sublink speed attribute lane mantissa
 185                  * describes the lane speed. E.g. PSIM and PSIE for gen2x2
 186                  * is 20Gbps, but the BOS descriptor lane speed mantissa is
 187                  * 10Gbps. Check and modify the mantissa value to match the
 188                  * lane speed.
 189                  */
 190                 if (bcdUSB == 0x0320 && plt == PLT_SYM) {
 191                         /*
 192                          * The PSI dword for gen1x2 and gen2x1 share the same
 193                          * values. But the lane speed for gen1x2 is 5Gbps while
 194                          * gen2x1 is 10Gbps. If the previous PSI dword SSID is
 195                          * 5 and the PSIE and PSIM match with SSID 6, let's
 196                          * assume that the controller follows the default speed
 197                          * id with SSID 6 for gen1x2.
 198                          */
 199                         if (ssid == 6 && psie == 3 && psim == 10 && i) {
 200                                 u32 prev = port_cap->psi[i - 1];
 201
 202                                 if ((prev & PLT_MASK) == PLT_SYM &&
 203                                     XHCI_EXT_PORT_PSIV(prev) == 5 &&
 204                                     XHCI_EXT_PORT_PSIE(prev) == 3 &&
 205                                     XHCI_EXT_PORT_PSIM(prev) == 10) {
 206                                         lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
 207                                         lane_mantissa = 5;
 208                                 }
 209                         }
 210
 211                         if (psie == 3 && psim > 10) {
 212                                 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
 213                                 lane_mantissa = 10;
 214                         }
 215                 }
 216
 217                 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) |
 218                         FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) |
 219                         FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) |
 220                         FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa));
 221
 222                 switch (plt) {
 223                 case PLT_SYM:
 224                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 225                                            USB_SSP_SUBLINK_SPEED_ST_SYM_RX);
 226                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 227
 228                         attr &= ~USB_SSP_SUBLINK_SPEED_ST;
 229                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 230                                            USB_SSP_SUBLINK_SPEED_ST_SYM_TX);
 231                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 232                         break;
 233                 case PLT_ASYM_RX:
 234                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 235                                            USB_SSP_SUBLINK_SPEED_ST_ASYM_RX);
 236                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 237                         break;
 238                 case PLT_ASYM_TX:
 239                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 240                                            USB_SSP_SUBLINK_SPEED_ST_ASYM_TX);
 241                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 242                         break;
 243                 }
 244         }
 245 out:
 246         ssp_cap->wFunctionalitySupport =
 247                 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID,
 248                                        min_ssid) |
 249                             FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |
 250                             FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));
 251
 252         return le16_to_cpu(bos->wTotalLength);
 253 }
 254
 255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 256                 struct usb_hub_descriptor *desc, int ports)
 257 {
 258         u16 temp;
 259
 260         desc->bHubContrCurrent = 0;
 261
 262         desc->bNbrPorts = ports;
 263         temp = 0;
 264         /* Bits 1:0 - support per-port power switching, or power always on */
 265         if (HCC_PPC(xhci->hcc_params))
 266                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 267         else
 268                 temp |= HUB_CHAR_NO_LPSM;
 269         /* Bit  2 - root hubs are not part of a compound device */
 270         /* Bits 4:3 - individual port over current protection */
 271         temp |= HUB_CHAR_INDV_PORT_OCPM;
 272         /* Bits 6:5 - no TTs in root ports */
 273         /* Bit  7 - no port indicators */
 274         desc->wHubCharacteristics = cpu_to_le16(temp);
 275 }
 276
 277 /* Fill in the USB 2.0 roothub descriptor */
 278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 279                 struct usb_hub_descriptor *desc)
 280 {
 281         int ports;
 282         u16 temp;
 283         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 284         u32 portsc;
 285         unsigned int i;
 286         struct xhci_hub *rhub;
 287
 288         rhub = &xhci->usb2_rhub;
 289         ports = rhub->num_ports;
 290         xhci_common_hub_descriptor(xhci, desc, ports);
 291         desc->bDescriptorType = USB_DT_HUB;
 292         temp = 1 + (ports / 8);
 293         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 294         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.8 says 20ms */
 295
 296         /* The Device Removable bits are reported on a byte granularity.
 297          * If the port doesn't exist within that byte, the bit is set to 0.
 298          */
 299         memset(port_removable, 0, sizeof(port_removable));
 300         for (i = 0; i < ports; i++) {
 301                 portsc = readl(rhub->ports[i]->addr);
 302                 /* If a device is removable, PORTSC reports a 0, same as in the
 303                  * hub descriptor DeviceRemovable bits.
 304                  */
 305                 if (portsc & PORT_DEV_REMOVE)
 306                         /* This math is hairy because bit 0 of DeviceRemovable
 307                          * is reserved, and bit 1 is for port 1, etc.
 308                          */
 309                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 310         }
 311
 312         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 313          * ports on it.  The USB 2.0 specification says that there are two
 314          * variable length fields at the end of the hub descriptor:
 315          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 316          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 317          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 318          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 319          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 320          * set of ports that actually exist.
 321          */
 322         memset(desc->u.hs.DeviceRemovable, 0xff,
 323                         sizeof(desc->u.hs.DeviceRemovable));
 324         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 325                         sizeof(desc->u.hs.PortPwrCtrlMask));
 326
 327         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 328                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 329                                 sizeof(__u8));
 330 }
 331
 332 /* Fill in the USB 3.0 roothub descriptor */
 333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 334                 struct usb_hub_descriptor *desc)
 335 {
 336         int ports;
 337         u16 port_removable;
 338         u32 portsc;
 339         unsigned int i;
 340         struct xhci_hub *rhub;
 341
 342         rhub = &xhci->usb3_rhub;
 343         ports = rhub->num_ports;
 344         xhci_common_hub_descriptor(xhci, desc, ports);
 345         desc->bDescriptorType = USB_DT_SS_HUB;
 346         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 347         desc->bPwrOn2PwrGood = 50;      /* usb 3.1 may fail if less than 100ms */
 348
 349         /* header decode latency should be zero for roothubs,
 350          * see section 4.23.5.2.
 351          */
 352         desc->u.ss.bHubHdrDecLat = 0;
 353         desc->u.ss.wHubDelay = 0;
 354
 355         port_removable = 0;
 356         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 357         for (i = 0; i < ports; i++) {
 358                 portsc = readl(rhub->ports[i]->addr);
 359                 if (portsc & PORT_DEV_REMOVE)
 360                         port_removable |= 1 << (i + 1);
 361         }
 362
 363         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 364 }
 365
 366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 367                 struct usb_hub_descriptor *desc)
 368 {
 369
 370         if (hcd->speed >= HCD_USB3)
 371                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 372         else
 373                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 374
 375 }
 376
 377 static unsigned int xhci_port_speed(unsigned int port_status)
 378 {
 379         if (DEV_LOWSPEED(port_status))
 380                 return USB_PORT_STAT_LOW_SPEED;
 381         if (DEV_HIGHSPEED(port_status))
 382                 return USB_PORT_STAT_HIGH_SPEED;
 383         /*
 384          * FIXME: Yes, we should check for full speed, but the core uses that as
 385          * a default in portspeed() in usb/core/hub.c (which is the only place
 386          * USB_PORT_STAT_*_SPEED is used).
 387          */
 388         return 0;
 389 }
 390
 391 /*
 392  * These bits are Read Only (RO) and should be saved and written to the
 393  * registers: 0, 3, 10:13, 30
 394  * connect status, over-current status, port speed, and device removable.
 395  * connect status and port speed are also sticky - meaning they're in
 396  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 397  */
 398 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 399 /*
 400  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 401  * bits 5:8, 9, 14:15, 25:27
 402  * link state, port power, port indicator state, "wake on" enable state
 403  */
 404 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 405 /*
 406  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 407  * bit 4 (port reset)
 408  */
 409 #define XHCI_PORT_RW1S  ((1<<4))
 410 /*
 411  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 412  * bits 1, 17, 18, 19, 20, 21, 22, 23
 413  * port enable/disable, and
 414  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 415  * over-current, reset, link state, and L1 change
 416  */
 417 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 418 /*
 419  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 420  * latched in
 421  */
 422 #define XHCI_PORT_RW    ((1<<16))
 423 /*
 424  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 425  * bits 2, 24, 28:31
 426  */
 427 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 428
 429 /**
 430  * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable
 431  * @state: u32 port value read from portsc register to be cleanup up
 432  *
 433  * Given a port state, this function returns a value that would result in the
 434  * port being in the same state, if the value was written to the port status
 435  * control register.
 436  * Save Read Only (RO) bits and save read/write bits where
 437  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 438  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 439  *
 440  * Return: u32 value that can be written back to portsc register without
 441  * changing port state.
 442  */
 443
 444 u32 xhci_port_state_to_neutral(u32 state)
 445 {
 446         /* Save read-only status and port state */
 447         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 448 }
 449 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral);
 450
 451 /*
 452  * Stop device
 453  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 454  * to complete.
 455  * suspend will set to 1, if suspend bit need to set in command.
 456  */
 457 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 458 {
 459         struct xhci_virt_device *virt_dev;
 460         struct xhci_command *cmd;
 461         unsigned long flags;
 462         int ret;
 463         int i;
 464
 465         ret = 0;
 466         virt_dev = xhci->devs[slot_id];
 467         if (!virt_dev)
 468                 return -ENODEV;
 469
 470         trace_xhci_stop_device(virt_dev);
 471
 472         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 473         if (!cmd)
 474                 return -ENOMEM;
 475
 476         spin_lock_irqsave(&xhci->lock, flags);
 477         for (i = LAST_EP_INDEX; i > 0; i--) {
 478                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 479                         struct xhci_ep_ctx *ep_ctx;
 480                         struct xhci_command *command;
 481
 482                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 483
 484                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 485                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 486                                 continue;
 487
 488                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 489                         if (!command) {
 490                                 spin_unlock_irqrestore(&xhci->lock, flags);
 491                                 ret = -ENOMEM;
 492                                 goto cmd_cleanup;
 493                         }
 494
 495                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 496                                                        i, suspend);
 497                         if (ret) {
 498                                 spin_unlock_irqrestore(&xhci->lock, flags);
 499                                 xhci_free_command(xhci, command);
 500                                 goto cmd_cleanup;
 501                         }
 502                 }
 503         }
 504         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 505         if (ret) {
 506                 spin_unlock_irqrestore(&xhci->lock, flags);
 507                 goto cmd_cleanup;
 508         }
 509
 510         xhci_ring_cmd_db(xhci);
 511         spin_unlock_irqrestore(&xhci->lock, flags);
 512
 513         /* Wait for last stop endpoint command to finish */
 514         wait_for_completion(cmd->completion);
 515
 516         if (cmd->status == COMP_COMMAND_ABORTED ||
 517             cmd->status == COMP_COMMAND_RING_STOPPED) {
 518                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 519                 ret = -ETIME;
 520         }
 521
 522 cmd_cleanup:
 523         xhci_free_command(xhci, cmd);
 524         return ret;
 525 }
 526
 527 /*
 528  * Ring device, it rings the all doorbells unconditionally.
 529  */
 530 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 531 {
 532         int i, s;
 533         struct xhci_virt_ep *ep;
 534
 535         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 536                 ep = &xhci->devs[slot_id]->eps[i];
 537
 538                 if (ep->ep_state & EP_HAS_STREAMS) {
 539                         for (s = 1; s < ep->stream_info->num_streams; s++)
 540                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 541                 } else if (ep->ring && ep->ring->dequeue) {
 542                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 543                 }
 544         }
 545
 546         return;
 547 }
 548
 549 static void xhci_disable_port(struct xhci_hcd *xhci, struct xhci_port *port)
 550 {
 551         struct usb_hcd *hcd;
 552         u32 portsc;
 553
 554         hcd = port->rhub->hcd;
 555
 556         /* Don't allow the USB core to disable SuperSpeed ports. */
 557         if (hcd->speed >= HCD_USB3) {
 558                 xhci_dbg(xhci, "Ignoring request to disable SuperSpeed port.\n");
 559                 return;
 560         }
 561
 562         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 563                 xhci_dbg(xhci,
 564                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 565                 return;
 566         }
 567
 568         portsc = readl(port->addr);
 569         portsc = xhci_port_state_to_neutral(portsc);
 570
 571         /* Write 1 to disable the port */
 572         writel(portsc | PORT_PE, port->addr);
 573
 574         portsc = readl(port->addr);
 575         xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
 576                  hcd->self.busnum, port->hcd_portnum + 1, portsc);
 577 }
 578
 579 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 580                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 581 {
 582         char *port_change_bit;
 583         u32 status;
 584
 585         switch (wValue) {
 586         case USB_PORT_FEAT_C_RESET:
 587                 status = PORT_RC;
 588                 port_change_bit = "reset";
 589                 break;
 590         case USB_PORT_FEAT_C_BH_PORT_RESET:
 591                 status = PORT_WRC;
 592                 port_change_bit = "warm(BH) reset";
 593                 break;
 594         case USB_PORT_FEAT_C_CONNECTION:
 595                 status = PORT_CSC;
 596                 port_change_bit = "connect";
 597                 break;
 598         case USB_PORT_FEAT_C_OVER_CURRENT:
 599                 status = PORT_OCC;
 600                 port_change_bit = "over-current";
 601                 break;
 602         case USB_PORT_FEAT_C_ENABLE:
 603                 status = PORT_PEC;
 604                 port_change_bit = "enable/disable";
 605                 break;
 606         case USB_PORT_FEAT_C_SUSPEND:
 607                 status = PORT_PLC;
 608                 port_change_bit = "suspend/resume";
 609                 break;
 610         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 611                 status = PORT_PLC;
 612                 port_change_bit = "link state";
 613                 break;
 614         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 615                 status = PORT_CEC;
 616                 port_change_bit = "config error";
 617                 break;
 618         default:
 619                 /* Should never happen */
 620                 return;
 621         }
 622         /* Change bits are all write 1 to clear */
 623         writel(port_status | status, addr);
 624         port_status = readl(addr);
 625
 626         xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
 627                  wIndex + 1, port_change_bit, port_status);
 628 }
 629
 630 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 631 {
 632         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 633
 634         if (hcd->speed >= HCD_USB3)
 635                 return &xhci->usb3_rhub;
 636         return &xhci->usb2_rhub;
 637 }
 638
 639 /*
 640  * xhci_set_port_power() must be called with xhci->lock held.
 641  * It will release and re-aquire the lock while calling ACPI
 642  * method.
 643  */
 644 static void xhci_set_port_power(struct xhci_hcd *xhci, struct xhci_port *port,
 645                                 bool on, unsigned long *flags)
 646         __must_hold(&xhci->lock)
 647 {
 648         struct usb_hcd *hcd;
 649         u32 temp;
 650
 651         hcd = port->rhub->hcd;
 652         temp = readl(port->addr);
 653
 654         xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
 655                  hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp);
 656
 657         temp = xhci_port_state_to_neutral(temp);
 658
 659         if (on) {
 660                 /* Power on */
 661                 writel(temp | PORT_POWER, port->addr);
 662                 readl(port->addr);
 663         } else {
 664                 /* Power off */
 665                 writel(temp & ~PORT_POWER, port->addr);
 666         }
 667
 668         spin_unlock_irqrestore(&xhci->lock, *flags);
 669         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 670                                          port->hcd_portnum);
 671         if (temp)
 672                 usb_acpi_set_power_state(hcd->self.root_hub,
 673                                          port->hcd_portnum, on);
 674         spin_lock_irqsave(&xhci->lock, *flags);
 675 }
 676
 677 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 678         u16 test_mode, u16 wIndex)
 679 {
 680         u32 temp;
 681         struct xhci_port *port;
 682
 683         /* xhci only supports test mode for usb2 ports */
 684         port = xhci->usb2_rhub.ports[wIndex];
 685         temp = readl(port->addr + PORTPMSC);
 686         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 687         writel(temp, port->addr + PORTPMSC);
 688         xhci->test_mode = test_mode;
 689         if (test_mode == USB_TEST_FORCE_ENABLE)
 690                 xhci_start(xhci);
 691 }
 692
 693 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 694                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 695         __must_hold(&xhci->lock)
 696 {
 697         int i, retval;
 698
 699         /* Disable all Device Slots */
 700         xhci_dbg(xhci, "Disable all slots\n");
 701         spin_unlock_irqrestore(&xhci->lock, *flags);
 702         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 703                 if (!xhci->devs[i])
 704                         continue;
 705
 706                 retval = xhci_disable_slot(xhci, i);
 707                 xhci_free_virt_device(xhci, i);
 708                 if (retval)
 709                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 710                                  i, retval);
 711         }
 712         spin_lock_irqsave(&xhci->lock, *flags);
 713         /* Put all ports to the Disable state by clear PP */
 714         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 715         /* Power off USB3 ports*/
 716         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 717                 xhci_set_port_power(xhci, xhci->usb3_rhub.ports[i], false, flags);
 718         /* Power off USB2 ports*/
 719         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 720                 xhci_set_port_power(xhci, xhci->usb2_rhub.ports[i], false, flags);
 721         /* Stop the controller */
 722         xhci_dbg(xhci, "Stop controller\n");
 723         retval = xhci_halt(xhci);
 724         if (retval)
 725                 return retval;
 726         /* Disable runtime PM for test mode */
 727         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 728         /* Set PORTPMSC.PTC field to enter selected test mode */
 729         /* Port is selected by wIndex. port_id = wIndex + 1 */
 730         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 731                                         test_mode, wIndex + 1);
 732         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 733         return retval;
 734 }
 735
 736 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 737 {
 738         int retval;
 739
 740         if (!xhci->test_mode) {
 741                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 742                 return 0;
 743         }
 744         if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
 745                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 746                 retval = xhci_halt(xhci);
 747                 if (retval)
 748                         return retval;
 749         }
 750         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 751         xhci->test_mode = 0;
 752         return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 753 }
 754
 755 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 756                          u32 link_state)
 757 {
 758         u32 temp;
 759         u32 portsc;
 760
 761         portsc = readl(port->addr);
 762         temp = xhci_port_state_to_neutral(portsc);
 763         temp &= ~PORT_PLS_MASK;
 764         temp |= PORT_LINK_STROBE | link_state;
 765         writel(temp, port->addr);
 766
 767         xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
 768                  port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
 769                  portsc, temp);
 770 }
 771
 772 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 773                                       struct xhci_port *port, u16 wake_mask)
 774 {
 775         u32 temp;
 776
 777         temp = readl(port->addr);
 778         temp = xhci_port_state_to_neutral(temp);
 779
 780         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 781                 temp |= PORT_WKCONN_E;
 782         else
 783                 temp &= ~PORT_WKCONN_E;
 784
 785         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 786                 temp |= PORT_WKDISC_E;
 787         else
 788                 temp &= ~PORT_WKDISC_E;
 789
 790         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 791                 temp |= PORT_WKOC_E;
 792         else
 793                 temp &= ~PORT_WKOC_E;
 794
 795         writel(temp, port->addr);
 796 }
 797
 798 /* Test and clear port RWC bit */
 799 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 800                              u32 port_bit)
 801 {
 802         u32 temp;
 803
 804         temp = readl(port->addr);
 805         if (temp & port_bit) {
 806                 temp = xhci_port_state_to_neutral(temp);
 807                 temp |= port_bit;
 808                 writel(temp, port->addr);
 809         }
 810 }
 811
 812 /* Updates Link Status for super Speed port */
 813 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 814                 u32 *status, u32 status_reg)
 815 {
 816         u32 pls = status_reg & PORT_PLS_MASK;
 817
 818         /* When the CAS bit is set then warm reset
 819          * should be performed on port
 820          */
 821         if (status_reg & PORT_CAS) {
 822                 /* The CAS bit can be set while the port is
 823                  * in any link state.
 824                  * Only roothubs have CAS bit, so we
 825                  * pretend to be in compliance mode
 826                  * unless we're already in compliance
 827                  * or the inactive state.
 828                  */
 829                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 830                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 831                         pls = USB_SS_PORT_LS_COMP_MOD;
 832                 }
 833                 /* Return also connection bit -
 834                  * hub state machine resets port
 835                  * when this bit is set.
 836                  */
 837                 pls |= USB_PORT_STAT_CONNECTION;
 838         } else {
 839                 /*
 840                  * Resume state is an xHCI internal state.  Do not report it to
 841                  * usb core, instead, pretend to be U3, thus usb core knows
 842                  * it's not ready for transfer.
 843                  */
 844                 if (pls == XDEV_RESUME) {
 845                         *status |= USB_SS_PORT_LS_U3;
 846                         return;
 847                 }
 848
 849                 /*
 850                  * If CAS bit isn't set but the Port is already at
 851                  * Compliance Mode, fake a connection so the USB core
 852                  * notices the Compliance state and resets the port.
 853                  * This resolves an issue generated by the SN65LVPE502CP
 854                  * in which sometimes the port enters compliance mode
 855                  * caused by a delay on the host-device negotiation.
 856                  */
 857                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 858                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 859                         pls |= USB_PORT_STAT_CONNECTION;
 860         }
 861
 862         /* update status field */
 863         *status |= pls;
 864 }
 865
 866 /*
 867  * Function for Compliance Mode Quirk.
 868  *
 869  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 870  * the compliance mode timer is deleted. A port won't enter
 871  * compliance mode if it has previously entered U0.
 872  */
 873 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 874                                     u16 wIndex)
 875 {
 876         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 877         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 878
 879         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 880                 return;
 881
 882         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 883                 xhci->port_status_u0 |= 1 << wIndex;
 884                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 885                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 886                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 887                                 "All USB3 ports have entered U0 already!");
 888                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 889                                 "Compliance Mode Recovery Timer Deleted.");
 890                 }
 891         }
 892 }
 893
 894 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
 895                                              u32 portsc,
 896                                              unsigned long *flags)
 897 {
 898         struct xhci_bus_state *bus_state;
 899         struct xhci_hcd *xhci;
 900         struct usb_hcd *hcd;
 901         u32 wIndex;
 902
 903         hcd = port->rhub->hcd;
 904         bus_state = &port->rhub->bus_state;
 905         xhci = hcd_to_xhci(hcd);
 906         wIndex = port->hcd_portnum;
 907
 908         if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
 909                 return -EINVAL;
 910         }
 911         /* did port event handler already start resume timing? */
 912         if (!port->resume_timestamp) {
 913                 /* If not, maybe we are in a host initated resume? */
 914                 if (test_bit(wIndex, &bus_state->resuming_ports)) {
 915                         /* Host initated resume doesn't time the resume
 916                          * signalling using resume_done[].
 917                          * It manually sets RESUME state, sleeps 20ms
 918                          * and sets U0 state. This should probably be
 919                          * changed, but not right now.
 920                          */
 921                 } else {
 922                         /* port resume was discovered now and here,
 923                          * start resume timing
 924                          */
 925                         unsigned long timeout = jiffies +
 926                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
 927
 928                         set_bit(wIndex, &bus_state->resuming_ports);
 929                         port->resume_timestamp = timeout;
 930                         mod_timer(&hcd->rh_timer, timeout);
 931                         usb_hcd_start_port_resume(&hcd->self, wIndex);
 932                 }
 933         /* Has resume been signalled for USB_RESUME_TIME yet? */
 934         } else if (time_after_eq(jiffies, port->resume_timestamp)) {
 935                 int time_left;
 936
 937                 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
 938                          hcd->self.busnum, wIndex + 1);
 939
 940                 port->resume_timestamp = 0;
 941                 clear_bit(wIndex, &bus_state->resuming_ports);
 942
 943                 reinit_completion(&port->rexit_done);
 944                 port->rexit_active = true;
 945
 946                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 947                 xhci_set_link_state(xhci, port, XDEV_U0);
 948
 949                 spin_unlock_irqrestore(&xhci->lock, *flags);
 950                 time_left = wait_for_completion_timeout(
 951                         &port->rexit_done,
 952                         msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
 953                 spin_lock_irqsave(&xhci->lock, *flags);
 954
 955                 if (time_left) {
 956                         if (!port->slot_id) {
 957                                 xhci_dbg(xhci, "slot_id is zero\n");
 958                                 return -ENODEV;
 959                         }
 960                         xhci_ring_device(xhci, port->slot_id);
 961                 } else {
 962                         int port_status = readl(port->addr);
 963
 964                         xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
 965                                   hcd->self.busnum, wIndex + 1, port_status);
 966                         /*
 967                          * keep rexit_active set if U0 transition failed so we
 968                          * know to report PORT_STAT_SUSPEND status back to
 969                          * usbcore. It will be cleared later once the port is
 970                          * out of RESUME/U3 state
 971                          */
 972                 }
 973
 974                 usb_hcd_end_port_resume(&hcd->self, wIndex);
 975                 bus_state->port_c_suspend |= 1 << wIndex;
 976                 bus_state->suspended_ports &= ~(1 << wIndex);
 977         }
 978
 979         return 0;
 980 }
 981
 982 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
 983 {
 984         u32 ext_stat = 0;
 985         int speed_id;
 986
 987         /* only support rx and tx lane counts of 1 in usb3.1 spec */
 988         speed_id = DEV_PORT_SPEED(raw_port_status);
 989         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
 990         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
 991
 992         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
 993         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
 994
 995         return ext_stat;
 996 }
 997
 998 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
 999                                       u32 portsc)
1000 {
1001         struct xhci_bus_state *bus_state;
1002         struct xhci_hcd *xhci;
1003         struct usb_hcd *hcd;
1004         u32 link_state;
1005         u32 portnum;
1006
1007         bus_state = &port->rhub->bus_state;
1008         xhci = hcd_to_xhci(port->rhub->hcd);
1009         hcd = port->rhub->hcd;
1010         link_state = portsc & PORT_PLS_MASK;
1011         portnum = port->hcd_portnum;
1012
1013         /* USB3 specific wPortChange bits
1014          *
1015          * Port link change with port in resume state should not be
1016          * reported to usbcore, as this is an internal state to be
1017          * handled by xhci driver. Reporting PLC to usbcore may
1018          * cause usbcore clearing PLC first and port change event
1019          * irq won't be generated.
1020          */
1021
1022         if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
1023                 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
1024         if (portsc & PORT_WRC)
1025                 *status |= USB_PORT_STAT_C_BH_RESET << 16;
1026         if (portsc & PORT_CEC)
1027                 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
1028
1029         /* USB3 specific wPortStatus bits */
1030         if (portsc & PORT_POWER)
1031                 *status |= USB_SS_PORT_STAT_POWER;
1032
1033         /* no longer suspended or resuming */
1034         if (link_state != XDEV_U3 &&
1035             link_state != XDEV_RESUME &&
1036             link_state != XDEV_RECOVERY) {
1037                 /* remote wake resume signaling complete */
1038                 if (bus_state->port_remote_wakeup & (1 << portnum)) {
1039                         bus_state->port_remote_wakeup &= ~(1 << portnum);
1040                         usb_hcd_end_port_resume(&hcd->self, portnum);
1041                 }
1042                 bus_state->suspended_ports &= ~(1 << portnum);
1043         }
1044
1045         xhci_hub_report_usb3_link_state(xhci, status, portsc);
1046         xhci_del_comp_mod_timer(xhci, portsc, portnum);
1047 }
1048
1049 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
1050                                       u32 portsc, unsigned long *flags)
1051 {
1052         struct xhci_bus_state *bus_state;
1053         u32 link_state;
1054         u32 portnum;
1055         int err;
1056
1057         bus_state = &port->rhub->bus_state;
1058         link_state = portsc & PORT_PLS_MASK;
1059         portnum = port->hcd_portnum;
1060
1061         /* USB2 wPortStatus bits */
1062         if (portsc & PORT_POWER) {
1063                 *status |= USB_PORT_STAT_POWER;
1064
1065                 /* link state is only valid if port is powered */
1066                 if (link_state == XDEV_U3)
1067                         *status |= USB_PORT_STAT_SUSPEND;
1068                 if (link_state == XDEV_U2)
1069                         *status |= USB_PORT_STAT_L1;
1070                 if (link_state == XDEV_U0) {
1071                         if (bus_state->suspended_ports & (1 << portnum)) {
1072                                 bus_state->suspended_ports &= ~(1 << portnum);
1073                                 bus_state->port_c_suspend |= 1 << portnum;
1074                         }
1075                 }
1076                 if (link_state == XDEV_RESUME) {
1077                         err = xhci_handle_usb2_port_link_resume(port, portsc,
1078                                                                 flags);
1079                         if (err < 0)
1080                                 *status = 0xffffffff;
1081                         else if (port->resume_timestamp || port->rexit_active)
1082                                 *status |= USB_PORT_STAT_SUSPEND;
1083                 }
1084         }
1085
1086         /*
1087          * Clear usb2 resume signalling variables if port is no longer suspended
1088          * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a
1089          * error state. Resume related variables should be cleared in all those cases.
1090          */
1091         if (link_state != XDEV_U3 && link_state != XDEV_RESUME) {
1092                 if (port->resume_timestamp ||
1093                     test_bit(portnum, &bus_state->resuming_ports)) {
1094                         port->resume_timestamp = 0;
1095                         clear_bit(portnum, &bus_state->resuming_ports);
1096                         usb_hcd_end_port_resume(&port->rhub->hcd->self, portnum);
1097                 }
1098                 port->rexit_active = 0;
1099                 bus_state->suspended_ports &= ~(1 << portnum);
1100         }
1101 }
1102
1103 /*
1104  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1105  * 3.0 hubs use.
1106  *
1107  * Possible side effects:
1108  *  - Mark a port as being done with device resume,
1109  *    and ring the endpoint doorbells.
1110  *  - Stop the Synopsys redriver Compliance Mode polling.
1111  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1112  */
1113 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1114                 struct xhci_bus_state *bus_state,
1115         u16 wIndex, u32 raw_port_status,
1116                 unsigned long *flags)
1117         __releases(&xhci->lock)
1118         __acquires(&xhci->lock)
1119 {
1120         u32 status = 0;
1121         struct xhci_hub *rhub;
1122         struct xhci_port *port;
1123
1124         rhub = xhci_get_rhub(hcd);
1125         port = rhub->ports[wIndex];
1126
1127         /* common wPortChange bits */
1128         if (raw_port_status & PORT_CSC)
1129                 status |= USB_PORT_STAT_C_CONNECTION << 16;
1130         if (raw_port_status & PORT_PEC)
1131                 status |= USB_PORT_STAT_C_ENABLE << 16;
1132         if ((raw_port_status & PORT_OCC))
1133                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1134         if ((raw_port_status & PORT_RC))
1135                 status |= USB_PORT_STAT_C_RESET << 16;
1136
1137         /* common wPortStatus bits */
1138         if (raw_port_status & PORT_CONNECT) {
1139                 status |= USB_PORT_STAT_CONNECTION;
1140                 status |= xhci_port_speed(raw_port_status);
1141         }
1142         if (raw_port_status & PORT_PE)
1143                 status |= USB_PORT_STAT_ENABLE;
1144         if (raw_port_status & PORT_OC)
1145                 status |= USB_PORT_STAT_OVERCURRENT;
1146         if (raw_port_status & PORT_RESET)
1147                 status |= USB_PORT_STAT_RESET;
1148
1149         /* USB2 and USB3 specific bits, including Port Link State */
1150         if (hcd->speed >= HCD_USB3)
1151                 xhci_get_usb3_port_status(port, &status, raw_port_status);
1152         else
1153                 xhci_get_usb2_port_status(port, &status, raw_port_status,
1154                                           flags);
1155
1156         if (bus_state->port_c_suspend & (1 << wIndex))
1157                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1158
1159         return status;
1160 }
1161
1162 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1163                 u16 wIndex, char *buf, u16 wLength)
1164 {
1165         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1166         int max_ports;
1167         unsigned long flags;
1168         u32 temp, status;
1169         int retval = 0;
1170         struct xhci_bus_state *bus_state;
1171         u16 link_state = 0;
1172         u16 wake_mask = 0;
1173         u16 timeout = 0;
1174         u16 test_mode = 0;
1175         struct xhci_hub *rhub;
1176         struct xhci_port **ports;
1177         struct xhci_port *port;
1178         int portnum1;
1179
1180         rhub = xhci_get_rhub(hcd);
1181         ports = rhub->ports;
1182         max_ports = rhub->num_ports;
1183         bus_state = &rhub->bus_state;
1184         portnum1 = wIndex & 0xff;
1185
1186         spin_lock_irqsave(&xhci->lock, flags);
1187         switch (typeReq) {
1188         case GetHubStatus:
1189                 /* No power source, over-current reported per port */
1190                 memset(buf, 0, 4);
1191                 break;
1192         case GetHubDescriptor:
1193                 /* Check to make sure userspace is asking for the USB 3.0 hub
1194                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1195                  * endpoint, like external hubs do.
1196                  */
1197                 if (hcd->speed >= HCD_USB3 &&
1198                                 (wLength < USB_DT_SS_HUB_SIZE ||
1199                                  wValue != (USB_DT_SS_HUB << 8))) {
1200                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1201                                         "USB 3.0 roothub.\n");
1202                         goto error;
1203                 }
1204                 xhci_hub_descriptor(hcd, xhci,
1205                                 (struct usb_hub_descriptor *) buf);
1206                 break;
1207         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1208                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1209                         goto error;
1210
1211                 if (hcd->speed < HCD_USB3)
1212                         goto error;
1213
1214                 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength);
1215                 spin_unlock_irqrestore(&xhci->lock, flags);
1216                 return retval;
1217         case GetPortStatus:
1218                 if (!portnum1 || portnum1 > max_ports)
1219                         goto error;
1220
1221                 wIndex--;
1222                 port = ports[portnum1 - 1];
1223                 temp = readl(port->addr);
1224                 if (temp == ~(u32)0) {
1225                         xhci_hc_died(xhci);
1226                         retval = -ENODEV;
1227                         break;
1228                 }
1229                 trace_xhci_get_port_status(port, temp);
1230                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1231                                               &flags);
1232                 if (status == 0xffffffff)
1233                         goto error;
1234
1235                 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1236                          hcd->self.busnum, portnum1, temp, status);
1237
1238                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1239                 /* if USB 3.1 extended port status return additional 4 bytes */
1240                 if (wValue == 0x02) {
1241                         u32 port_li;
1242
1243                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1244                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1245                                 retval = -EINVAL;
1246                                 break;
1247                         }
1248                         port_li = readl(port->addr + PORTLI);
1249                         status = xhci_get_ext_port_status(temp, port_li);
1250                         put_unaligned_le32(status, &buf[4]);
1251                 }
1252                 break;
1253         case SetPortFeature:
1254                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1255                         link_state = (wIndex & 0xff00) >> 3;
1256                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1257                         wake_mask = wIndex & 0xff00;
1258                 if (wValue == USB_PORT_FEAT_TEST)
1259                         test_mode = (wIndex & 0xff00) >> 8;
1260                 /* The MSB of wIndex is the U1/U2 timeout */
1261                 timeout = (wIndex & 0xff00) >> 8;
1262
1263                 wIndex &= 0xff;
1264                 if (!portnum1 || portnum1 > max_ports)
1265                         goto error;
1266
1267                 port = ports[portnum1 - 1];
1268                 wIndex--;
1269                 temp = readl(port->addr);
1270                 if (temp == ~(u32)0) {
1271                         xhci_hc_died(xhci);
1272                         retval = -ENODEV;
1273                         break;
1274                 }
1275                 temp = xhci_port_state_to_neutral(temp);
1276                 /* FIXME: What new port features do we need to support? */
1277                 switch (wValue) {
1278                 case USB_PORT_FEAT_SUSPEND:
1279                         temp = readl(port->addr);
1280                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1281                                 /* Resume the port to U0 first */
1282                                 xhci_set_link_state(xhci, port, XDEV_U0);
1283                                 spin_unlock_irqrestore(&xhci->lock, flags);
1284                                 msleep(10);
1285                                 spin_lock_irqsave(&xhci->lock, flags);
1286                         }
1287                         /* In spec software should not attempt to suspend
1288                          * a port unless the port reports that it is in the
1289                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1290                          */
1291                         temp = readl(port->addr);
1292                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1293                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1294                                 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1295                                           hcd->self.busnum, portnum1);
1296                                 goto error;
1297                         }
1298
1299                         if (!port->slot_id) {
1300                                 xhci_warn(xhci, "slot_id is zero\n");
1301                                 goto error;
1302                         }
1303                         /* unlock to execute stop endpoint commands */
1304                         spin_unlock_irqrestore(&xhci->lock, flags);
1305                         xhci_stop_device(xhci, port->slot_id, 1);
1306                         spin_lock_irqsave(&xhci->lock, flags);
1307
1308                         xhci_set_link_state(xhci, port, XDEV_U3);
1309
1310                         spin_unlock_irqrestore(&xhci->lock, flags);
1311                         msleep(10); /* wait device to enter */
1312                         spin_lock_irqsave(&xhci->lock, flags);
1313
1314                         temp = readl(port->addr);
1315                         bus_state->suspended_ports |= 1 << wIndex;
1316                         break;
1317                 case USB_PORT_FEAT_LINK_STATE:
1318                         temp = readl(port->addr);
1319                         /* Disable port */
1320                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1321                                 xhci_dbg(xhci, "Disable port %d-%d\n",
1322                                          hcd->self.busnum, portnum1);
1323                                 temp = xhci_port_state_to_neutral(temp);
1324                                 /*
1325                                  * Clear all change bits, so that we get a new
1326                                  * connection event.
1327                                  */
1328                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1329                                         PORT_OCC | PORT_RC | PORT_PLC |
1330                                         PORT_CEC;
1331                                 writel(temp | PORT_PE, port->addr);
1332                                 temp = readl(port->addr);
1333                                 break;
1334                         }
1335
1336                         /* Put link in RxDetect (enable port) */
1337                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1338                                 xhci_dbg(xhci, "Enable port %d-%d\n",
1339                                          hcd->self.busnum, portnum1);
1340                                 xhci_set_link_state(xhci, port, link_state);
1341                                 temp = readl(port->addr);
1342                                 break;
1343                         }
1344
1345                         /*
1346                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1347                          * root hub port's transition to compliance mode upon
1348                          * detecting LFPS timeout may be controlled by an
1349                          * Compliance Transition Enabled (CTE) flag (not
1350                          * software visible). This flag is set by writing 0xA
1351                          * to PORTSC PLS field which will allow transition to
1352                          * compliance mode the next time LFPS timeout is
1353                          * encountered. A warm reset will clear it.
1354                          *
1355                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1356                          * flag is set, otherwise, the compliance substate is
1357                          * automatically entered as on 1.0 and prior.
1358                          */
1359                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1360                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1361                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1362                                         break;
1363                                 }
1364
1365                                 if ((temp & PORT_CONNECT)) {
1366                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1367                                         goto error;
1368                                 }
1369
1370                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1371                                          hcd->self.busnum, portnum1);
1372                                 xhci_set_link_state(xhci, port, link_state);
1373
1374                                 temp = readl(port->addr);
1375                                 break;
1376                         }
1377                         /* Port must be enabled */
1378                         if (!(temp & PORT_PE)) {
1379                                 retval = -ENODEV;
1380                                 break;
1381                         }
1382                         /* Can't set port link state above '3' (U3) */
1383                         if (link_state > USB_SS_PORT_LS_U3) {
1384                                 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1385                                           hcd->self.busnum, portnum1, link_state);
1386                                 goto error;
1387                         }
1388
1389                         /*
1390                          * set link to U0, steps depend on current link state.
1391                          * U3: set link to U0 and wait for u3exit completion.
1392                          * U1/U2:  no PLC complete event, only set link to U0.
1393                          * Resume/Recovery: device initiated U0, only wait for
1394                          * completion
1395                          */
1396                         if (link_state == USB_SS_PORT_LS_U0) {
1397                                 u32 pls = temp & PORT_PLS_MASK;
1398                                 bool wait_u0 = false;
1399
1400                                 /* already in U0 */
1401                                 if (pls == XDEV_U0)
1402                                         break;
1403                                 if (pls == XDEV_U3 ||
1404                                     pls == XDEV_RESUME ||
1405                                     pls == XDEV_RECOVERY) {
1406                                         wait_u0 = true;
1407                                         reinit_completion(&port->u3exit_done);
1408                                 }
1409                                 if (pls <= XDEV_U3) /* U1, U2, U3 */
1410                                         xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U0);
1411                                 if (!wait_u0) {
1412                                         if (pls > XDEV_U3)
1413                                                 goto error;
1414                                         break;
1415                                 }
1416                                 spin_unlock_irqrestore(&xhci->lock, flags);
1417                                 if (!wait_for_completion_timeout(&port->u3exit_done,
1418                                                                  msecs_to_jiffies(500)))
1419                                         xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1420                                                  hcd->self.busnum, portnum1);
1421                                 spin_lock_irqsave(&xhci->lock, flags);
1422                                 temp = readl(port->addr);
1423                                 break;
1424                         }
1425
1426                         if (link_state == USB_SS_PORT_LS_U3) {
1427                                 int retries = 16;
1428                                 if (port->slot_id) {
1429                                         /* unlock to execute stop endpoint
1430                                          * commands */
1431                                         spin_unlock_irqrestore(&xhci->lock,
1432                                                                 flags);
1433                                         xhci_stop_device(xhci, port->slot_id, 1);
1434                                         spin_lock_irqsave(&xhci->lock, flags);
1435                                 }
1436                                 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U3);
1437                                 spin_unlock_irqrestore(&xhci->lock, flags);
1438                                 while (retries--) {
1439                                         usleep_range(4000, 8000);
1440                                         temp = readl(port->addr);
1441                                         if ((temp & PORT_PLS_MASK) == XDEV_U3)
1442                                                 break;
1443                                 }
1444                                 spin_lock_irqsave(&xhci->lock, flags);
1445                                 temp = readl(port->addr);
1446                                 bus_state->suspended_ports |= 1 << wIndex;
1447                         }
1448                         break;
1449                 case USB_PORT_FEAT_POWER:
1450                         /*
1451                          * Turn on ports, even if there isn't per-port switching.
1452                          * HC will report connect events even before this is set.
1453                          * However, hub_wq will ignore the roothub events until
1454                          * the roothub is registered.
1455                          */
1456                         xhci_set_port_power(xhci, port, true, &flags);
1457                         break;
1458                 case USB_PORT_FEAT_RESET:
1459                         temp = (temp | PORT_RESET);
1460                         writel(temp, port->addr);
1461
1462                         temp = readl(port->addr);
1463                         xhci_dbg(xhci, "set port reset, actual port %d-%d status  = 0x%x\n",
1464                                  hcd->self.busnum, portnum1, temp);
1465                         break;
1466                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1467                         xhci_set_remote_wake_mask(xhci, port, wake_mask);
1468                         temp = readl(port->addr);
1469                         xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status  = 0x%x\n",
1470                                  hcd->self.busnum, portnum1, temp);
1471                         break;
1472                 case USB_PORT_FEAT_BH_PORT_RESET:
1473                         temp |= PORT_WR;
1474                         writel(temp, port->addr);
1475                         temp = readl(port->addr);
1476                         break;
1477                 case USB_PORT_FEAT_U1_TIMEOUT:
1478                         if (hcd->speed < HCD_USB3)
1479                                 goto error;
1480                         temp = readl(port->addr + PORTPMSC);
1481                         temp &= ~PORT_U1_TIMEOUT_MASK;
1482                         temp |= PORT_U1_TIMEOUT(timeout);
1483                         writel(temp, port->addr + PORTPMSC);
1484                         break;
1485                 case USB_PORT_FEAT_U2_TIMEOUT:
1486                         if (hcd->speed < HCD_USB3)
1487                                 goto error;
1488                         temp = readl(port->addr + PORTPMSC);
1489                         temp &= ~PORT_U2_TIMEOUT_MASK;
1490                         temp |= PORT_U2_TIMEOUT(timeout);
1491                         writel(temp, port->addr + PORTPMSC);
1492                         break;
1493                 case USB_PORT_FEAT_TEST:
1494                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1495                         if (hcd->speed != HCD_USB2)
1496                                 goto error;
1497                         if (test_mode > USB_TEST_FORCE_ENABLE ||
1498                             test_mode < USB_TEST_J)
1499                                 goto error;
1500                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1501                                                       &flags);
1502                         break;
1503                 default:
1504                         goto error;
1505                 }
1506                 /* unblock any posted writes */
1507                 temp = readl(port->addr);
1508                 break;
1509         case ClearPortFeature:
1510                 if (!portnum1 || portnum1 > max_ports)
1511                         goto error;
1512
1513                 port = ports[portnum1 - 1];
1514
1515                 wIndex--;
1516                 temp = readl(port->addr);
1517                 if (temp == ~(u32)0) {
1518                         xhci_hc_died(xhci);
1519                         retval = -ENODEV;
1520                         break;
1521                 }
1522                 /* FIXME: What new port features do we need to support? */
1523                 temp = xhci_port_state_to_neutral(temp);
1524                 switch (wValue) {
1525                 case USB_PORT_FEAT_SUSPEND:
1526                         temp = readl(port->addr);
1527                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1528                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1529                         if (temp & PORT_RESET)
1530                                 goto error;
1531                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1532                                 if ((temp & PORT_PE) == 0)
1533                                         goto error;
1534
1535                                 set_bit(wIndex, &bus_state->resuming_ports);
1536                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1537                                 xhci_set_link_state(xhci, port, XDEV_RESUME);
1538                                 spin_unlock_irqrestore(&xhci->lock, flags);
1539                                 msleep(USB_RESUME_TIMEOUT);
1540                                 spin_lock_irqsave(&xhci->lock, flags);
1541                                 xhci_set_link_state(xhci, port, XDEV_U0);
1542                                 clear_bit(wIndex, &bus_state->resuming_ports);
1543                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1544                         }
1545                         bus_state->port_c_suspend |= 1 << wIndex;
1546
1547                         if (!port->slot_id) {
1548                                 xhci_dbg(xhci, "slot_id is zero\n");
1549                                 goto error;
1550                         }
1551                         xhci_ring_device(xhci, port->slot_id);
1552                         break;
1553                 case USB_PORT_FEAT_C_SUSPEND:
1554                         bus_state->port_c_suspend &= ~(1 << wIndex);
1555                         fallthrough;
1556                 case USB_PORT_FEAT_C_RESET:
1557                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1558                 case USB_PORT_FEAT_C_CONNECTION:
1559                 case USB_PORT_FEAT_C_OVER_CURRENT:
1560                 case USB_PORT_FEAT_C_ENABLE:
1561                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1562                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1563                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1564                                         port->addr, temp);
1565                         break;
1566                 case USB_PORT_FEAT_ENABLE:
1567                         xhci_disable_port(xhci, port);
1568                         break;
1569                 case USB_PORT_FEAT_POWER:
1570                         xhci_set_port_power(xhci, port, false, &flags);
1571                         break;
1572                 case USB_PORT_FEAT_TEST:
1573                         retval = xhci_exit_test_mode(xhci);
1574                         break;
1575                 default:
1576                         goto error;
1577                 }
1578                 break;
1579         default:
1580 error:
1581                 /* "stall" on error */
1582                 retval = -EPIPE;
1583         }
1584         spin_unlock_irqrestore(&xhci->lock, flags);
1585         return retval;
1586 }
1587 EXPORT_SYMBOL_GPL(xhci_hub_control);
1588
1589 /*
1590  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1591  * Ports are 0-indexed from the HCD point of view,
1592  * and 1-indexed from the USB core pointer of view.
1593  *
1594  * Note that the status change bits will be cleared as soon as a port status
1595  * change event is generated, so we use the saved status from that event.
1596  */
1597 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1598 {
1599         unsigned long flags;
1600         u32 temp, status;
1601         u32 mask;
1602         int i, retval;
1603         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1604         int max_ports;
1605         struct xhci_bus_state *bus_state;
1606         bool reset_change = false;
1607         struct xhci_hub *rhub;
1608         struct xhci_port **ports;
1609
1610         rhub = xhci_get_rhub(hcd);
1611         ports = rhub->ports;
1612         max_ports = rhub->num_ports;
1613         bus_state = &rhub->bus_state;
1614
1615         /* Initial status is no changes */
1616         retval = (max_ports + 8) / 8;
1617         memset(buf, 0, retval);
1618
1619         /*
1620          * Inform the usbcore about resume-in-progress by returning
1621          * a non-zero value even if there are no status changes.
1622          */
1623         spin_lock_irqsave(&xhci->lock, flags);
1624
1625         status = bus_state->resuming_ports;
1626
1627         /*
1628          * SS devices are only visible to roothub after link training completes.
1629          * Keep polling roothubs for a grace period after xHC start
1630          */
1631         if (xhci->run_graceperiod) {
1632                 if (time_before(jiffies, xhci->run_graceperiod))
1633                         status = 1;
1634                 else
1635                         xhci->run_graceperiod = 0;
1636         }
1637
1638         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1639
1640         /* For each port, did anything change?  If so, set that bit in buf. */
1641         for (i = 0; i < max_ports; i++) {
1642                 temp = readl(ports[i]->addr);
1643                 if (temp == ~(u32)0) {
1644                         xhci_hc_died(xhci);
1645                         retval = -ENODEV;
1646                         break;
1647                 }
1648                 trace_xhci_hub_status_data(ports[i], temp);
1649
1650                 if ((temp & mask) != 0 ||
1651                         (bus_state->port_c_suspend & 1 << i) ||
1652                         (ports[i]->resume_timestamp && time_after_eq(
1653                             jiffies, ports[i]->resume_timestamp))) {
1654                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1655                         status = 1;
1656                 }
1657                 if ((temp & PORT_RC))
1658                         reset_change = true;
1659                 if (temp & PORT_OC)
1660                         status = 1;
1661         }
1662         if (!status && !reset_change) {
1663                 xhci_dbg(xhci, "%s: stopping usb%d port polling\n",
1664                          __func__, hcd->self.busnum);
1665                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1666         }
1667         spin_unlock_irqrestore(&xhci->lock, flags);
1668         return status ? retval : 0;
1669 }
1670
1671 #ifdef CONFIG_PM
1672
1673 int xhci_bus_suspend(struct usb_hcd *hcd)
1674 {
1675         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1676         int max_ports, port_index;
1677         struct xhci_bus_state *bus_state;
1678         unsigned long flags;
1679         struct xhci_hub *rhub;
1680         struct xhci_port **ports;
1681         u32 portsc_buf[USB_MAXCHILDREN];
1682         bool wake_enabled;
1683
1684         rhub = xhci_get_rhub(hcd);
1685         ports = rhub->ports;
1686         max_ports = rhub->num_ports;
1687         bus_state = &rhub->bus_state;
1688         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1689
1690         spin_lock_irqsave(&xhci->lock, flags);
1691
1692         if (wake_enabled) {
1693                 if (bus_state->resuming_ports ||        /* USB2 */
1694                     bus_state->port_remote_wakeup) {    /* USB3 */
1695                         spin_unlock_irqrestore(&xhci->lock, flags);
1696                         xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n",
1697                                  hcd->self.busnum);
1698                         return -EBUSY;
1699                 }
1700         }
1701         /*
1702          * Prepare ports for suspend, but don't write anything before all ports
1703          * are checked and we know bus suspend can proceed
1704          */
1705         bus_state->bus_suspended = 0;
1706         port_index = max_ports;
1707         while (port_index--) {
1708                 u32 t1, t2;
1709                 int retries = 10;
1710 retry:
1711                 t1 = readl(ports[port_index]->addr);
1712                 t2 = xhci_port_state_to_neutral(t1);
1713                 portsc_buf[port_index] = 0;
1714
1715                 /*
1716                  * Give a USB3 port in link training time to finish, but don't
1717                  * prevent suspend as port might be stuck
1718                  */
1719                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1720                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1721                         spin_unlock_irqrestore(&xhci->lock, flags);
1722                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1723                         spin_lock_irqsave(&xhci->lock, flags);
1724                         xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1725                                  hcd->self.busnum, port_index + 1);
1726                         goto retry;
1727                 }
1728                 /* bail out if port detected a over-current condition */
1729                 if (t1 & PORT_OC) {
1730                         bus_state->bus_suspended = 0;
1731                         spin_unlock_irqrestore(&xhci->lock, flags);
1732                         xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1733                         return -EBUSY;
1734                 }
1735                 /* suspend ports in U0, or bail out for new connect changes */
1736                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1737                         if ((t1 & PORT_CSC) && wake_enabled) {
1738                                 bus_state->bus_suspended = 0;
1739                                 spin_unlock_irqrestore(&xhci->lock, flags);
1740                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1741                                 return -EBUSY;
1742                         }
1743                         xhci_dbg(xhci, "port %d-%d not suspended\n",
1744                                  hcd->self.busnum, port_index + 1);
1745                         t2 &= ~PORT_PLS_MASK;
1746                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1747                         set_bit(port_index, &bus_state->bus_suspended);
1748                 }
1749                 /* USB core sets remote wake mask for USB 3.0 hubs,
1750                  * including the USB 3.0 roothub, but only if CONFIG_PM
1751                  * is enabled, so also enable remote wake here.
1752                  */
1753                 if (wake_enabled) {
1754                         if (t1 & PORT_CONNECT) {
1755                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1756                                 t2 &= ~PORT_WKCONN_E;
1757                         } else {
1758                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1759                                 t2 &= ~PORT_WKDISC_E;
1760                         }
1761
1762                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1763                             (hcd->speed < HCD_USB3)) {
1764                                 if (usb_amd_pt_check_port(hcd->self.controller,
1765                                                           port_index))
1766                                         t2 &= ~PORT_WAKE_BITS;
1767                         }
1768                 } else
1769                         t2 &= ~PORT_WAKE_BITS;
1770
1771                 t1 = xhci_port_state_to_neutral(t1);
1772                 if (t1 != t2)
1773                         portsc_buf[port_index] = t2;
1774         }
1775
1776         /* write port settings, stopping and suspending ports if needed */
1777         port_index = max_ports;
1778         while (port_index--) {
1779                 if (!portsc_buf[port_index])
1780                         continue;
1781                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1782                         int slot_id = ports[port_index]->slot_id;
1783                         if (slot_id) {
1784                                 spin_unlock_irqrestore(&xhci->lock, flags);
1785                                 xhci_stop_device(xhci, slot_id, 1);
1786                                 spin_lock_irqsave(&xhci->lock, flags);
1787                         }
1788                 }
1789                 writel(portsc_buf[port_index], ports[port_index]->addr);
1790         }
1791         hcd->state = HC_STATE_SUSPENDED;
1792         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1793         spin_unlock_irqrestore(&xhci->lock, flags);
1794
1795         if (bus_state->bus_suspended)
1796                 usleep_range(5000, 10000);
1797
1798         return 0;
1799 }
1800
1801 /*
1802  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1803  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1804  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1805  */
1806 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1807 {
1808         u32 portsc;
1809
1810         portsc = readl(port->addr);
1811
1812         /* if any of these are set we are not stuck */
1813         if (portsc & (PORT_CONNECT | PORT_CAS))
1814                 return false;
1815
1816         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1817             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1818                 return false;
1819
1820         /* clear wakeup/change bits, and do a warm port reset */
1821         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1822         portsc |= PORT_WR;
1823         writel(portsc, port->addr);
1824         /* flush write */
1825         readl(port->addr);
1826         return true;
1827 }
1828
1829 int xhci_bus_resume(struct usb_hcd *hcd)
1830 {
1831         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1832         struct xhci_bus_state *bus_state;
1833         unsigned long flags;
1834         int max_ports, port_index;
1835         int sret;
1836         u32 next_state;
1837         u32 temp, portsc;
1838         struct xhci_hub *rhub;
1839         struct xhci_port **ports;
1840
1841         rhub = xhci_get_rhub(hcd);
1842         ports = rhub->ports;
1843         max_ports = rhub->num_ports;
1844         bus_state = &rhub->bus_state;
1845
1846         if (time_before(jiffies, bus_state->next_statechange))
1847                 msleep(5);
1848
1849         spin_lock_irqsave(&xhci->lock, flags);
1850         if (!HCD_HW_ACCESSIBLE(hcd)) {
1851                 spin_unlock_irqrestore(&xhci->lock, flags);
1852                 return -ESHUTDOWN;
1853         }
1854
1855         /* delay the irqs */
1856         temp = readl(&xhci->op_regs->command);
1857         temp &= ~CMD_EIE;
1858         writel(temp, &xhci->op_regs->command);
1859
1860         /* bus specific resume for ports we suspended at bus_suspend */
1861         if (hcd->speed >= HCD_USB3)
1862                 next_state = XDEV_U0;
1863         else
1864                 next_state = XDEV_RESUME;
1865
1866         port_index = max_ports;
1867         while (port_index--) {
1868                 portsc = readl(ports[port_index]->addr);
1869
1870                 /* warm reset CAS limited ports stuck in polling/compliance */
1871                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1872                     (hcd->speed >= HCD_USB3) &&
1873                     xhci_port_missing_cas_quirk(ports[port_index])) {
1874                         xhci_dbg(xhci, "reset stuck port %d-%d\n",
1875                                  hcd->self.busnum, port_index + 1);
1876                         clear_bit(port_index, &bus_state->bus_suspended);
1877                         continue;
1878                 }
1879                 /* resume if we suspended the link, and it is still suspended */
1880                 if (test_bit(port_index, &bus_state->bus_suspended))
1881                         switch (portsc & PORT_PLS_MASK) {
1882                         case XDEV_U3:
1883                                 portsc = xhci_port_state_to_neutral(portsc);
1884                                 portsc &= ~PORT_PLS_MASK;
1885                                 portsc |= PORT_LINK_STROBE | next_state;
1886                                 break;
1887                         case XDEV_RESUME:
1888                                 /* resume already initiated */
1889                                 break;
1890                         default:
1891                                 /* not in a resumeable state, ignore it */
1892                                 clear_bit(port_index,
1893                                           &bus_state->bus_suspended);
1894                                 break;
1895                         }
1896                 /* disable wake for all ports, write new link state if needed */
1897                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1898                 writel(portsc, ports[port_index]->addr);
1899         }
1900
1901         /* USB2 specific resume signaling delay and U0 link state transition */
1902         if (hcd->speed < HCD_USB3) {
1903                 if (bus_state->bus_suspended) {
1904                         spin_unlock_irqrestore(&xhci->lock, flags);
1905                         msleep(USB_RESUME_TIMEOUT);
1906                         spin_lock_irqsave(&xhci->lock, flags);
1907                 }
1908                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1909                                  BITS_PER_LONG) {
1910                         /* Clear PLC to poll it later for U0 transition */
1911                         xhci_test_and_clear_bit(xhci, ports[port_index],
1912                                                 PORT_PLC);
1913                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1914                 }
1915         }
1916
1917         /* poll for U0 link state complete, both USB2 and USB3 */
1918         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1919                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1920                                       PORT_PLC, 10 * 1000);
1921                 if (sret) {
1922                         xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1923                                   hcd->self.busnum, port_index + 1);
1924                         continue;
1925                 }
1926                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1927                 if (ports[port_index]->slot_id)
1928                         xhci_ring_device(xhci, ports[port_index]->slot_id);
1929         }
1930         (void) readl(&xhci->op_regs->command);
1931
1932         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1933         /* re-enable irqs */
1934         temp = readl(&xhci->op_regs->command);
1935         temp |= CMD_EIE;
1936         writel(temp, &xhci->op_regs->command);
1937         temp = readl(&xhci->op_regs->command);
1938
1939         spin_unlock_irqrestore(&xhci->lock, flags);
1940         return 0;
1941 }
1942
1943 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1944 {
1945         struct xhci_hub *rhub = xhci_get_rhub(hcd);
1946
1947         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1948         return rhub->bus_state.resuming_ports;  /* USB2 ports only */
1949 }
1950
1951 #endif  /* CONFIG_PM */