drivers/usb/host/xhci-hub.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  */
  10
  11
  12 #include <linux/slab.h>
  13 #include <linux/unaligned.h>
  14 #include <linux/bitfield.h>
  15
  16 #include "xhci.h"
  17 #include "xhci-trace.h"
  18
  19 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  20 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  21                          PORT_RC | PORT_PLC | PORT_PE)
  22
  23 /* Default sublink speed attribute of each lane */
  24 static u32 ssp_cap_default_ssa[] = {
  25         0x00050034, /* USB 3.0 SS Gen1x1 id:4 symmetric rx 5Gbps */
  26         0x000500b4, /* USB 3.0 SS Gen1x1 id:4 symmetric tx 5Gbps */
  27         0x000a4035, /* USB 3.1 SSP Gen2x1 id:5 symmetric rx 10Gbps */
  28         0x000a40b5, /* USB 3.1 SSP Gen2x1 id:5 symmetric tx 10Gbps */
  29         0x00054036, /* USB 3.2 SSP Gen1x2 id:6 symmetric rx 5Gbps */
  30         0x000540b6, /* USB 3.2 SSP Gen1x2 id:6 symmetric tx 5Gbps */
  31         0x000a4037, /* USB 3.2 SSP Gen2x2 id:7 symmetric rx 10Gbps */
  32         0x000a40b7, /* USB 3.2 SSP Gen2x2 id:7 symmetric tx 10Gbps */
  33 };
  34
  35 static int xhci_create_usb3x_bos_desc(struct xhci_hcd *xhci, char *buf,
  36                                       u16 wLength)
  37 {
  38         struct usb_bos_descriptor       *bos;
  39         struct usb_ss_cap_descriptor    *ss_cap;
  40         struct usb_ssp_cap_descriptor   *ssp_cap;
  41         struct xhci_port_cap            *port_cap = NULL;
  42         u16                             bcdUSB;
  43         u32                             reg;
  44         u32                             min_rate = 0;
  45         u8                              min_ssid;
  46         u8                              ssac;
  47         u8                              ssic;
  48         int                             offset;
  49         int                             i;
  50
  51         /* BOS descriptor */
  52         bos = (struct usb_bos_descriptor *)buf;
  53         bos->bLength = USB_DT_BOS_SIZE;
  54         bos->bDescriptorType = USB_DT_BOS;
  55         bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
  56                                         USB_DT_USB_SS_CAP_SIZE);
  57         bos->bNumDeviceCaps = 1;
  58
  59         /* Create the descriptor for port with the highest revision */
  60         for (i = 0; i < xhci->num_port_caps; i++) {
  61                 u8 major = xhci->port_caps[i].maj_rev;
  62                 u8 minor = xhci->port_caps[i].min_rev;
  63                 u16 rev = (major << 8) | minor;
  64
  65                 if (i == 0 || bcdUSB < rev) {
  66                         bcdUSB = rev;
  67                         port_cap = &xhci->port_caps[i];
  68                 }
  69         }
  70
  71         if (bcdUSB >= 0x0310) {
  72                 if (port_cap->psi_count) {
  73                         u8 num_sym_ssa = 0;
  74
  75                         for (i = 0; i < port_cap->psi_count; i++) {
  76                                 if ((port_cap->psi[i] & PLT_MASK) == PLT_SYM)
  77                                         num_sym_ssa++;
  78                         }
  79
  80                         ssac = port_cap->psi_count + num_sym_ssa - 1;
  81                         ssic = port_cap->psi_uid_count - 1;
  82                 } else {
  83                         if (bcdUSB >= 0x0320)
  84                                 ssac = 7;
  85                         else
  86                                 ssac = 3;
  87
  88                         ssic = (ssac + 1) / 2 - 1;
  89                 }
  90
  91                 bos->bNumDeviceCaps++;
  92                 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE +
  93                                                 USB_DT_USB_SS_CAP_SIZE +
  94                                                 USB_DT_USB_SSP_CAP_SIZE(ssac));
  95         }
  96
  97         if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
  98                 return wLength;
  99
 100         /* SuperSpeed USB Device Capability */
 101         ss_cap = (struct usb_ss_cap_descriptor *)&buf[USB_DT_BOS_SIZE];
 102         ss_cap->bLength = USB_DT_USB_SS_CAP_SIZE;
 103         ss_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
 104         ss_cap->bDevCapabilityType = USB_SS_CAP_TYPE;
 105         ss_cap->bmAttributes = 0; /* set later */
 106         ss_cap->wSpeedSupported = cpu_to_le16(USB_5GBPS_OPERATION);
 107         ss_cap->bFunctionalitySupport = USB_LOW_SPEED_OPERATION;
 108         ss_cap->bU1devExitLat = 0; /* set later */
 109         ss_cap->bU2DevExitLat = 0; /* set later */
 110
 111         reg = readl(&xhci->cap_regs->hcc_params);
 112         if (HCC_LTC(reg))
 113                 ss_cap->bmAttributes |= USB_LTM_SUPPORT;
 114
 115         if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 116                 reg = readl(&xhci->cap_regs->hcs_params3);
 117                 ss_cap->bU1devExitLat = HCS_U1_LATENCY(reg);
 118                 ss_cap->bU2DevExitLat = cpu_to_le16(HCS_U2_LATENCY(reg));
 119         }
 120
 121         if (wLength < le16_to_cpu(bos->wTotalLength))
 122                 return wLength;
 123
 124         if (bcdUSB < 0x0310)
 125                 return le16_to_cpu(bos->wTotalLength);
 126
 127         ssp_cap = (struct usb_ssp_cap_descriptor *)&buf[USB_DT_BOS_SIZE +
 128                 USB_DT_USB_SS_CAP_SIZE];
 129         ssp_cap->bLength = USB_DT_USB_SSP_CAP_SIZE(ssac);
 130         ssp_cap->bDescriptorType = USB_DT_DEVICE_CAPABILITY;
 131         ssp_cap->bDevCapabilityType = USB_SSP_CAP_TYPE;
 132         ssp_cap->bReserved = 0;
 133         ssp_cap->wReserved = 0;
 134         ssp_cap->bmAttributes =
 135                 cpu_to_le32(FIELD_PREP(USB_SSP_SUBLINK_SPEED_ATTRIBS, ssac) |
 136                             FIELD_PREP(USB_SSP_SUBLINK_SPEED_IDS, ssic));
 137
 138         if (!port_cap->psi_count) {
 139                 for (i = 0; i < ssac + 1; i++)
 140                         ssp_cap->bmSublinkSpeedAttr[i] =
 141                                 cpu_to_le32(ssp_cap_default_ssa[i]);
 142
 143                 min_ssid = 4;
 144                 goto out;
 145         }
 146
 147         offset = 0;
 148         for (i = 0; i < port_cap->psi_count; i++) {
 149                 u32 psi;
 150                 u32 attr;
 151                 u8 ssid;
 152                 u8 lp;
 153                 u8 lse;
 154                 u8 psie;
 155                 u16 lane_mantissa;
 156                 u16 psim;
 157                 u16 plt;
 158
 159                 psi = port_cap->psi[i];
 160                 ssid = XHCI_EXT_PORT_PSIV(psi);
 161                 lp = XHCI_EXT_PORT_LP(psi);
 162                 psie = XHCI_EXT_PORT_PSIE(psi);
 163                 psim = XHCI_EXT_PORT_PSIM(psi);
 164                 plt = psi & PLT_MASK;
 165
 166                 lse = psie;
 167                 lane_mantissa = psim;
 168
 169                 /* Shift to Gbps and set SSP Link Protocol if 10Gpbs */
 170                 for (; psie < USB_SSP_SUBLINK_SPEED_LSE_GBPS; psie++)
 171                         psim /= 1000;
 172
 173                 if (!min_rate || psim < min_rate) {
 174                         min_ssid = ssid;
 175                         min_rate = psim;
 176                 }
 177
 178                 /* Some host controllers don't set the link protocol for SSP */
 179                 if (psim >= 10)
 180                         lp = USB_SSP_SUBLINK_SPEED_LP_SSP;
 181
 182                 /*
 183                  * PSIM and PSIE represent the total speed of PSI. The BOS
 184                  * descriptor SSP sublink speed attribute lane mantissa
 185                  * describes the lane speed. E.g. PSIM and PSIE for gen2x2
 186                  * is 20Gbps, but the BOS descriptor lane speed mantissa is
 187                  * 10Gbps. Check and modify the mantissa value to match the
 188                  * lane speed.
 189                  */
 190                 if (bcdUSB == 0x0320 && plt == PLT_SYM) {
 191                         /*
 192                          * The PSI dword for gen1x2 and gen2x1 share the same
 193                          * values. But the lane speed for gen1x2 is 5Gbps while
 194                          * gen2x1 is 10Gbps. If the previous PSI dword SSID is
 195                          * 5 and the PSIE and PSIM match with SSID 6, let's
 196                          * assume that the controller follows the default speed
 197                          * id with SSID 6 for gen1x2.
 198                          */
 199                         if (ssid == 6 && psie == 3 && psim == 10 && i) {
 200                                 u32 prev = port_cap->psi[i - 1];
 201
 202                                 if ((prev & PLT_MASK) == PLT_SYM &&
 203                                     XHCI_EXT_PORT_PSIV(prev) == 5 &&
 204                                     XHCI_EXT_PORT_PSIE(prev) == 3 &&
 205                                     XHCI_EXT_PORT_PSIM(prev) == 10) {
 206                                         lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
 207                                         lane_mantissa = 5;
 208                                 }
 209                         }
 210
 211                         if (psie == 3 && psim > 10) {
 212                                 lse = USB_SSP_SUBLINK_SPEED_LSE_GBPS;
 213                                 lane_mantissa = 10;
 214                         }
 215                 }
 216
 217                 attr = (FIELD_PREP(USB_SSP_SUBLINK_SPEED_SSID, ssid) |
 218                         FIELD_PREP(USB_SSP_SUBLINK_SPEED_LP, lp) |
 219                         FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSE, lse) |
 220                         FIELD_PREP(USB_SSP_SUBLINK_SPEED_LSM, lane_mantissa));
 221
 222                 switch (plt) {
 223                 case PLT_SYM:
 224                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 225                                            USB_SSP_SUBLINK_SPEED_ST_SYM_RX);
 226                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 227
 228                         attr &= ~USB_SSP_SUBLINK_SPEED_ST;
 229                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 230                                            USB_SSP_SUBLINK_SPEED_ST_SYM_TX);
 231                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 232                         break;
 233                 case PLT_ASYM_RX:
 234                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 235                                            USB_SSP_SUBLINK_SPEED_ST_ASYM_RX);
 236                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 237                         break;
 238                 case PLT_ASYM_TX:
 239                         attr |= FIELD_PREP(USB_SSP_SUBLINK_SPEED_ST,
 240                                            USB_SSP_SUBLINK_SPEED_ST_ASYM_TX);
 241                         ssp_cap->bmSublinkSpeedAttr[offset++] = cpu_to_le32(attr);
 242                         break;
 243                 }
 244         }
 245 out:
 246         ssp_cap->wFunctionalitySupport =
 247                 cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID,
 248                                        min_ssid) |
 249                             FIELD_PREP(USB_SSP_MIN_RX_LANE_COUNT, 1) |
 250                             FIELD_PREP(USB_SSP_MIN_TX_LANE_COUNT, 1));
 251
 252         return le16_to_cpu(bos->wTotalLength);
 253 }
 254
 255 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
 256                 struct usb_hub_descriptor *desc, int ports)
 257 {
 258         u16 temp;
 259
 260         desc->bHubContrCurrent = 0;
 261
 262         desc->bNbrPorts = ports;
 263         temp = 0;
 264         /* Bits 1:0 - support per-port power switching, or power always on */
 265         if (HCC_PPC(xhci->hcc_params))
 266                 temp |= HUB_CHAR_INDV_PORT_LPSM;
 267         else
 268                 temp |= HUB_CHAR_NO_LPSM;
 269         /* Bit  2 - root hubs are not part of a compound device */
 270         /* Bits 4:3 - individual port over current protection */
 271         temp |= HUB_CHAR_INDV_PORT_OCPM;
 272         /* Bits 6:5 - no TTs in root ports */
 273         /* Bit  7 - no port indicators */
 274         desc->wHubCharacteristics = cpu_to_le16(temp);
 275 }
 276
 277 /* Fill in the USB 2.0 roothub descriptor */
 278 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 279                 struct usb_hub_descriptor *desc)
 280 {
 281         int ports;
 282         u16 temp;
 283         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
 284         u32 portsc;
 285         unsigned int i;
 286         struct xhci_hub *rhub;
 287
 288         rhub = &xhci->usb2_rhub;
 289         ports = rhub->num_ports;
 290         xhci_common_hub_descriptor(xhci, desc, ports);
 291         desc->bDescriptorType = USB_DT_HUB;
 292         temp = 1 + (ports / 8);
 293         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
 294         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.8 says 20ms */
 295
 296         /* The Device Removable bits are reported on a byte granularity.
 297          * If the port doesn't exist within that byte, the bit is set to 0.
 298          */
 299         memset(port_removable, 0, sizeof(port_removable));
 300         for (i = 0; i < ports; i++) {
 301                 portsc = readl(rhub->ports[i]->addr);
 302                 /* If a device is removable, PORTSC reports a 0, same as in the
 303                  * hub descriptor DeviceRemovable bits.
 304                  */
 305                 if (portsc & PORT_DEV_REMOVE)
 306                         /* This math is hairy because bit 0 of DeviceRemovable
 307                          * is reserved, and bit 1 is for port 1, etc.
 308                          */
 309                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 310         }
 311
 312         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 313          * ports on it.  The USB 2.0 specification says that there are two
 314          * variable length fields at the end of the hub descriptor:
 315          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 316          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 317          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 318          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 319          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 320          * set of ports that actually exist.
 321          */
 322         memset(desc->u.hs.DeviceRemovable, 0xff,
 323                         sizeof(desc->u.hs.DeviceRemovable));
 324         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 325                         sizeof(desc->u.hs.PortPwrCtrlMask));
 326
 327         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 328                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 329                                 sizeof(__u8));
 330 }
 331
 332 /* Fill in the USB 3.0 roothub descriptor */
 333 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 334                 struct usb_hub_descriptor *desc)
 335 {
 336         int ports;
 337         u16 port_removable;
 338         u32 portsc;
 339         unsigned int i;
 340         struct xhci_hub *rhub;
 341
 342         rhub = &xhci->usb3_rhub;
 343         ports = rhub->num_ports;
 344         xhci_common_hub_descriptor(xhci, desc, ports);
 345         desc->bDescriptorType = USB_DT_SS_HUB;
 346         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 347         desc->bPwrOn2PwrGood = 50;      /* usb 3.1 may fail if less than 100ms */
 348
 349         /* header decode latency should be zero for roothubs,
 350          * see section 4.23.5.2.
 351          */
 352         desc->u.ss.bHubHdrDecLat = 0;
 353         desc->u.ss.wHubDelay = 0;
 354
 355         port_removable = 0;
 356         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 357         for (i = 0; i < ports; i++) {
 358                 portsc = readl(rhub->ports[i]->addr);
 359                 if (portsc & PORT_DEV_REMOVE)
 360                         port_removable |= 1 << (i + 1);
 361         }
 362
 363         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 364 }
 365
 366 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 367                 struct usb_hub_descriptor *desc)
 368 {
 369
 370         if (hcd->speed >= HCD_USB3)
 371                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 372         else
 373                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 374
 375 }
 376
 377 static unsigned int xhci_port_speed(unsigned int port_status)
 378 {
 379         if (DEV_LOWSPEED(port_status))
 380                 return USB_PORT_STAT_LOW_SPEED;
 381         if (DEV_HIGHSPEED(port_status))
 382                 return USB_PORT_STAT_HIGH_SPEED;
 383         /*
 384          * FIXME: Yes, we should check for full speed, but the core uses that as
 385          * a default in portspeed() in usb/core/hub.c (which is the only place
 386          * USB_PORT_STAT_*_SPEED is used).
 387          */
 388         return 0;
 389 }
 390
 391 /*
 392  * These bits are Read Only (RO) and should be saved and written to the
 393  * registers: 0, 3, 10:13, 30
 394  * connect status, over-current status, port speed, and device removable.
 395  * connect status and port speed are also sticky - meaning they're in
 396  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 397  */
 398 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 399 /*
 400  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 401  * bits 5:8, 9, 14:15, 25:27
 402  * link state, port power, port indicator state, "wake on" enable state
 403  */
 404 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 405 /*
 406  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 407  * bit 4 (port reset)
 408  */
 409 #define XHCI_PORT_RW1S  ((1<<4))
 410 /*
 411  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 412  * bits 1, 17, 18, 19, 20, 21, 22, 23
 413  * port enable/disable, and
 414  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 415  * over-current, reset, link state, and L1 change
 416  */
 417 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 418 /*
 419  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 420  * latched in
 421  */
 422 #define XHCI_PORT_RW    ((1<<16))
 423 /*
 424  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 425  * bits 2, 24, 28:31
 426  */
 427 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 428
 429 /**
 430  * xhci_port_state_to_neutral() - Clean up read portsc value back into writeable
 431  * @state: u32 port value read from portsc register to be cleanup up
 432  *
 433  * Given a port state, this function returns a value that would result in the
 434  * port being in the same state, if the value was written to the port status
 435  * control register.
 436  * Save Read Only (RO) bits and save read/write bits where
 437  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 438  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 439  *
 440  * Return: u32 value that can be written back to portsc register without
 441  * changing port state.
 442  */
 443
 444 u32 xhci_port_state_to_neutral(u32 state)
 445 {
 446         /* Save read-only status and port state */
 447         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 448 }
 449 EXPORT_SYMBOL_GPL(xhci_port_state_to_neutral);
 450
 451 /*
 452  * Stop device
 453  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 454  * to complete.
 455  * suspend will set to 1, if suspend bit need to set in command.
 456  */
 457 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 458 {
 459         struct xhci_virt_device *virt_dev;
 460         struct xhci_command *cmd;
 461         unsigned long flags;
 462         int ret;
 463         int i;
 464
 465         ret = 0;
 466         virt_dev = xhci->devs[slot_id];
 467         if (!virt_dev)
 468                 return -ENODEV;
 469
 470         trace_xhci_stop_device(virt_dev);
 471
 472         cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
 473         if (!cmd)
 474                 return -ENOMEM;
 475
 476         spin_lock_irqsave(&xhci->lock, flags);
 477         for (i = LAST_EP_INDEX; i > 0; i--) {
 478                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 479                         struct xhci_ep_ctx *ep_ctx;
 480                         struct xhci_command *command;
 481
 482                         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
 483
 484                         /* Check ep is running, required by AMD SNPS 3.1 xHC */
 485                         if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
 486                                 continue;
 487
 488                         command = xhci_alloc_command(xhci, false, GFP_NOWAIT);
 489                         if (!command) {
 490                                 spin_unlock_irqrestore(&xhci->lock, flags);
 491                                 ret = -ENOMEM;
 492                                 goto cmd_cleanup;
 493                         }
 494
 495                         ret = xhci_queue_stop_endpoint(xhci, command, slot_id,
 496                                                        i, suspend);
 497                         if (ret) {
 498                                 spin_unlock_irqrestore(&xhci->lock, flags);
 499                                 xhci_free_command(xhci, command);
 500                                 goto cmd_cleanup;
 501                         }
 502                 }
 503         }
 504         ret = xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 505         if (ret) {
 506                 spin_unlock_irqrestore(&xhci->lock, flags);
 507                 goto cmd_cleanup;
 508         }
 509
 510         xhci_ring_cmd_db(xhci);
 511         spin_unlock_irqrestore(&xhci->lock, flags);
 512
 513         /* Wait for last stop endpoint command to finish */
 514         wait_for_completion(cmd->completion);
 515
 516         if (cmd->status == COMP_COMMAND_ABORTED ||
 517             cmd->status == COMP_COMMAND_RING_STOPPED) {
 518                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 519                 ret = -ETIME;
 520         }
 521
 522 cmd_cleanup:
 523         xhci_free_command(xhci, cmd);
 524         return ret;
 525 }
 526
 527 /*
 528  * Ring device, it rings the all doorbells unconditionally.
 529  */
 530 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 531 {
 532         int i, s;
 533         struct xhci_virt_ep *ep;
 534
 535         for (i = 0; i < LAST_EP_INDEX + 1; i++) {
 536                 ep = &xhci->devs[slot_id]->eps[i];
 537
 538                 if (ep->ep_state & EP_HAS_STREAMS) {
 539                         for (s = 1; s < ep->stream_info->num_streams; s++)
 540                                 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
 541                 } else if (ep->ring && ep->ring->dequeue) {
 542                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 543                 }
 544         }
 545
 546         return;
 547 }
 548
 549 static void xhci_disable_port(struct xhci_hcd *xhci, struct xhci_port *port)
 550 {
 551         struct usb_hcd *hcd;
 552         u32 portsc;
 553
 554         hcd = port->rhub->hcd;
 555
 556         /* Don't allow the USB core to disable SuperSpeed ports. */
 557         if (hcd->speed >= HCD_USB3) {
 558                 xhci_dbg(xhci, "Ignoring request to disable SuperSpeed port.\n");
 559                 return;
 560         }
 561
 562         if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
 563                 xhci_dbg(xhci,
 564                          "Broken Port Enabled/Disabled, ignoring port disable request.\n");
 565                 return;
 566         }
 567
 568         portsc = readl(port->addr);
 569         portsc = xhci_port_state_to_neutral(portsc);
 570
 571         /* Write 1 to disable the port */
 572         writel(portsc | PORT_PE, port->addr);
 573
 574         portsc = readl(port->addr);
 575         xhci_dbg(xhci, "disable port %d-%d, portsc: 0x%x\n",
 576                  hcd->self.busnum, port->hcd_portnum + 1, portsc);
 577 }
 578
 579 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 580                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 581 {
 582         char *port_change_bit;
 583         u32 status;
 584
 585         switch (wValue) {
 586         case USB_PORT_FEAT_C_RESET:
 587                 status = PORT_RC;
 588                 port_change_bit = "reset";
 589                 break;
 590         case USB_PORT_FEAT_C_BH_PORT_RESET:
 591                 status = PORT_WRC;
 592                 port_change_bit = "warm(BH) reset";
 593                 break;
 594         case USB_PORT_FEAT_C_CONNECTION:
 595                 status = PORT_CSC;
 596                 port_change_bit = "connect";
 597                 break;
 598         case USB_PORT_FEAT_C_OVER_CURRENT:
 599                 status = PORT_OCC;
 600                 port_change_bit = "over-current";
 601                 break;
 602         case USB_PORT_FEAT_C_ENABLE:
 603                 status = PORT_PEC;
 604                 port_change_bit = "enable/disable";
 605                 break;
 606         case USB_PORT_FEAT_C_SUSPEND:
 607                 status = PORT_PLC;
 608                 port_change_bit = "suspend/resume";
 609                 break;
 610         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 611                 status = PORT_PLC;
 612                 port_change_bit = "link state";
 613                 break;
 614         case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
 615                 status = PORT_CEC;
 616                 port_change_bit = "config error";
 617                 break;
 618         default:
 619                 /* Should never happen */
 620                 return;
 621         }
 622         /* Change bits are all write 1 to clear */
 623         writel(port_status | status, addr);
 624         port_status = readl(addr);
 625
 626         xhci_dbg(xhci, "clear port%d %s change, portsc: 0x%x\n",
 627                  wIndex + 1, port_change_bit, port_status);
 628 }
 629
 630 struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd)
 631 {
 632         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 633
 634         if (hcd->speed >= HCD_USB3)
 635                 return &xhci->usb3_rhub;
 636         return &xhci->usb2_rhub;
 637 }
 638
 639 /*
 640  * xhci_set_port_power() must be called with xhci->lock held.
 641  * It will release and re-aquire the lock while calling ACPI
 642  * method.
 643  */
 644 static void xhci_set_port_power(struct xhci_hcd *xhci, struct xhci_port *port,
 645                                 bool on, unsigned long *flags)
 646         __must_hold(&xhci->lock)
 647 {
 648         struct usb_hcd *hcd;
 649         u32 temp;
 650
 651         hcd = port->rhub->hcd;
 652         temp = readl(port->addr);
 653
 654         xhci_dbg(xhci, "set port power %d-%d %s, portsc: 0x%x\n",
 655                  hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp);
 656
 657         temp = xhci_port_state_to_neutral(temp);
 658
 659         if (on) {
 660                 /* Power on */
 661                 writel(temp | PORT_POWER, port->addr);
 662                 readl(port->addr);
 663         } else {
 664                 /* Power off */
 665                 writel(temp & ~PORT_POWER, port->addr);
 666         }
 667
 668         spin_unlock_irqrestore(&xhci->lock, *flags);
 669         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 670                                          port->hcd_portnum);
 671         if (temp)
 672                 usb_acpi_set_power_state(hcd->self.root_hub,
 673                                          port->hcd_portnum, on);
 674         spin_lock_irqsave(&xhci->lock, *flags);
 675 }
 676
 677 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
 678         u16 test_mode, u16 wIndex)
 679 {
 680         u32 temp;
 681         struct xhci_port *port;
 682
 683         /* xhci only supports test mode for usb2 ports */
 684         port = xhci->usb2_rhub.ports[wIndex];
 685         temp = readl(port->addr + PORTPMSC);
 686         temp |= test_mode << PORT_TEST_MODE_SHIFT;
 687         writel(temp, port->addr + PORTPMSC);
 688         xhci->test_mode = test_mode;
 689         if (test_mode == USB_TEST_FORCE_ENABLE)
 690                 xhci_start(xhci);
 691 }
 692
 693 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
 694                                 u16 test_mode, u16 wIndex, unsigned long *flags)
 695         __must_hold(&xhci->lock)
 696 {
 697         int i, retval;
 698
 699         /* Disable all Device Slots */
 700         xhci_dbg(xhci, "Disable all slots\n");
 701         spin_unlock_irqrestore(&xhci->lock, *flags);
 702         for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 703                 if (!xhci->devs[i])
 704                         continue;
 705
 706                 retval = xhci_disable_slot(xhci, i);
 707                 xhci_free_virt_device(xhci, i);
 708                 if (retval)
 709                         xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
 710                                  i, retval);
 711         }
 712         spin_lock_irqsave(&xhci->lock, *flags);
 713         /* Put all ports to the Disable state by clear PP */
 714         xhci_dbg(xhci, "Disable all port (PP = 0)\n");
 715         /* Power off USB3 ports*/
 716         for (i = 0; i < xhci->usb3_rhub.num_ports; i++)
 717                 xhci_set_port_power(xhci, xhci->usb3_rhub.ports[i], false, flags);
 718         /* Power off USB2 ports*/
 719         for (i = 0; i < xhci->usb2_rhub.num_ports; i++)
 720                 xhci_set_port_power(xhci, xhci->usb2_rhub.ports[i], false, flags);
 721         /* Stop the controller */
 722         xhci_dbg(xhci, "Stop controller\n");
 723         retval = xhci_halt(xhci);
 724         if (retval)
 725                 return retval;
 726         /* Disable runtime PM for test mode */
 727         pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
 728         /* Set PORTPMSC.PTC field to enter selected test mode */
 729         /* Port is selected by wIndex. port_id = wIndex + 1 */
 730         xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
 731                                         test_mode, wIndex + 1);
 732         xhci_port_set_test_mode(xhci, test_mode, wIndex);
 733         return retval;
 734 }
 735
 736 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
 737 {
 738         int retval;
 739
 740         if (!xhci->test_mode) {
 741                 xhci_err(xhci, "Not in test mode, do nothing.\n");
 742                 return 0;
 743         }
 744         if (xhci->test_mode == USB_TEST_FORCE_ENABLE &&
 745                 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
 746                 retval = xhci_halt(xhci);
 747                 if (retval)
 748                         return retval;
 749         }
 750         pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
 751         xhci->test_mode = 0;
 752         return xhci_reset(xhci, XHCI_RESET_SHORT_USEC);
 753 }
 754
 755 /**
 756  * xhci_port_is_tunneled() - Check if USB3 connection is tunneled over USB4
 757  * @xhci: xhci host controller
 758  * @port: USB3 port to be checked.
 759  *
 760  * Some hosts can detect if a USB3 connection is native USB3 or tunneled over
 761  * USB4. Intel hosts expose this via vendor specific extended capability 206
 762  * eSS PORT registers TUNEN (tunnel enabled) bit.
 763  *
 764  * A USB3 device must be connected to the port to detect the tunnel.
 765  *
 766  * Return: link tunnel mode enum, USB_LINK_UNKNOWN if host is incapable of
 767  * detecting USB3 over USB4 tunnels. USB_LINK_NATIVE or USB_LINK_TUNNELED
 768  * otherwise.
 769  */
 770 enum usb_link_tunnel_mode xhci_port_is_tunneled(struct xhci_hcd *xhci,
 771                                                 struct xhci_port *port)
 772 {
 773         void __iomem *base;
 774         u32 offset;
 775
 776         base = &xhci->cap_regs->hc_capbase;
 777         offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_INTEL_SPR_SHADOW);
 778
 779         if (offset && offset <= XHCI_INTEL_SPR_ESS_PORT_OFFSET) {
 780                 offset = XHCI_INTEL_SPR_ESS_PORT_OFFSET + port->hcd_portnum * 0x20;
 781
 782                 if (readl(base + offset) & XHCI_INTEL_SPR_TUNEN)
 783                         return USB_LINK_TUNNELED;
 784                 else
 785                         return USB_LINK_NATIVE;
 786         }
 787
 788         return USB_LINK_UNKNOWN;
 789 }
 790
 791 void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
 792                          u32 link_state)
 793 {
 794         u32 temp;
 795         u32 portsc;
 796
 797         portsc = readl(port->addr);
 798         temp = xhci_port_state_to_neutral(portsc);
 799         temp &= ~PORT_PLS_MASK;
 800         temp |= PORT_LINK_STROBE | link_state;
 801         writel(temp, port->addr);
 802
 803         xhci_dbg(xhci, "Set port %d-%d link state, portsc: 0x%x, write 0x%x",
 804                  port->rhub->hcd->self.busnum, port->hcd_portnum + 1,
 805                  portsc, temp);
 806 }
 807
 808 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 809                                       struct xhci_port *port, u16 wake_mask)
 810 {
 811         u32 temp;
 812
 813         temp = readl(port->addr);
 814         temp = xhci_port_state_to_neutral(temp);
 815
 816         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 817                 temp |= PORT_WKCONN_E;
 818         else
 819                 temp &= ~PORT_WKCONN_E;
 820
 821         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 822                 temp |= PORT_WKDISC_E;
 823         else
 824                 temp &= ~PORT_WKDISC_E;
 825
 826         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 827                 temp |= PORT_WKOC_E;
 828         else
 829                 temp &= ~PORT_WKOC_E;
 830
 831         writel(temp, port->addr);
 832 }
 833
 834 /* Test and clear port RWC bit */
 835 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
 836                              u32 port_bit)
 837 {
 838         u32 temp;
 839
 840         temp = readl(port->addr);
 841         if (temp & port_bit) {
 842                 temp = xhci_port_state_to_neutral(temp);
 843                 temp |= port_bit;
 844                 writel(temp, port->addr);
 845         }
 846 }
 847
 848 /* Updates Link Status for super Speed port */
 849 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
 850                 u32 *status, u32 status_reg)
 851 {
 852         u32 pls = status_reg & PORT_PLS_MASK;
 853
 854         /* When the CAS bit is set then warm reset
 855          * should be performed on port
 856          */
 857         if (status_reg & PORT_CAS) {
 858                 /* The CAS bit can be set while the port is
 859                  * in any link state.
 860                  * Only roothubs have CAS bit, so we
 861                  * pretend to be in compliance mode
 862                  * unless we're already in compliance
 863                  * or the inactive state.
 864                  */
 865                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 866                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 867                         pls = USB_SS_PORT_LS_COMP_MOD;
 868                 }
 869                 /* Return also connection bit -
 870                  * hub state machine resets port
 871                  * when this bit is set.
 872                  */
 873                 pls |= USB_PORT_STAT_CONNECTION;
 874         } else {
 875                 /*
 876                  * Resume state is an xHCI internal state.  Do not report it to
 877                  * usb core, instead, pretend to be U3, thus usb core knows
 878                  * it's not ready for transfer.
 879                  */
 880                 if (pls == XDEV_RESUME) {
 881                         *status |= USB_SS_PORT_LS_U3;
 882                         return;
 883                 }
 884
 885                 /*
 886                  * If CAS bit isn't set but the Port is already at
 887                  * Compliance Mode, fake a connection so the USB core
 888                  * notices the Compliance state and resets the port.
 889                  * This resolves an issue generated by the SN65LVPE502CP
 890                  * in which sometimes the port enters compliance mode
 891                  * caused by a delay on the host-device negotiation.
 892                  */
 893                 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
 894                                 (pls == USB_SS_PORT_LS_COMP_MOD))
 895                         pls |= USB_PORT_STAT_CONNECTION;
 896         }
 897
 898         /* update status field */
 899         *status |= pls;
 900 }
 901
 902 /*
 903  * Function for Compliance Mode Quirk.
 904  *
 905  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 906  * the compliance mode timer is deleted. A port won't enter
 907  * compliance mode if it has previously entered U0.
 908  */
 909 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 910                                     u16 wIndex)
 911 {
 912         u32 all_ports_seen_u0 = ((1 << xhci->usb3_rhub.num_ports) - 1);
 913         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 914
 915         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 916                 return;
 917
 918         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 919                 xhci->port_status_u0 |= 1 << wIndex;
 920                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 921                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 922                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 923                                 "All USB3 ports have entered U0 already!");
 924                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 925                                 "Compliance Mode Recovery Timer Deleted.");
 926                 }
 927         }
 928 }
 929
 930 static int xhci_handle_usb2_port_link_resume(struct xhci_port *port,
 931                                              u32 portsc,
 932                                              unsigned long *flags)
 933 {
 934         struct xhci_bus_state *bus_state;
 935         struct xhci_hcd *xhci;
 936         struct usb_hcd *hcd;
 937         u32 wIndex;
 938
 939         hcd = port->rhub->hcd;
 940         bus_state = &port->rhub->bus_state;
 941         xhci = hcd_to_xhci(hcd);
 942         wIndex = port->hcd_portnum;
 943
 944         if ((portsc & PORT_RESET) || !(portsc & PORT_PE)) {
 945                 return -EINVAL;
 946         }
 947         /* did port event handler already start resume timing? */
 948         if (!port->resume_timestamp) {
 949                 /* If not, maybe we are in a host initiated resume? */
 950                 if (test_bit(wIndex, &bus_state->resuming_ports)) {
 951                         /* Host initiated resume doesn't time the resume
 952                          * signalling using resume_done[].
 953                          * It manually sets RESUME state, sleeps 20ms
 954                          * and sets U0 state. This should probably be
 955                          * changed, but not right now.
 956                          */
 957                 } else {
 958                         /* port resume was discovered now and here,
 959                          * start resume timing
 960                          */
 961                         unsigned long timeout = jiffies +
 962                                 msecs_to_jiffies(USB_RESUME_TIMEOUT);
 963
 964                         set_bit(wIndex, &bus_state->resuming_ports);
 965                         port->resume_timestamp = timeout;
 966                         mod_timer(&hcd->rh_timer, timeout);
 967                         usb_hcd_start_port_resume(&hcd->self, wIndex);
 968                 }
 969         /* Has resume been signalled for USB_RESUME_TIME yet? */
 970         } else if (time_after_eq(jiffies, port->resume_timestamp)) {
 971                 int time_left;
 972
 973                 xhci_dbg(xhci, "resume USB2 port %d-%d\n",
 974                          hcd->self.busnum, wIndex + 1);
 975
 976                 port->resume_timestamp = 0;
 977                 clear_bit(wIndex, &bus_state->resuming_ports);
 978
 979                 reinit_completion(&port->rexit_done);
 980                 port->rexit_active = true;
 981
 982                 xhci_test_and_clear_bit(xhci, port, PORT_PLC);
 983                 xhci_set_link_state(xhci, port, XDEV_U0);
 984
 985                 spin_unlock_irqrestore(&xhci->lock, *flags);
 986                 time_left = wait_for_completion_timeout(
 987                         &port->rexit_done,
 988                         msecs_to_jiffies(XHCI_MAX_REXIT_TIMEOUT_MS));
 989                 spin_lock_irqsave(&xhci->lock, *flags);
 990
 991                 if (time_left) {
 992                         if (!port->slot_id) {
 993                                 xhci_dbg(xhci, "slot_id is zero\n");
 994                                 return -ENODEV;
 995                         }
 996                         xhci_ring_device(xhci, port->slot_id);
 997                 } else {
 998                         int port_status = readl(port->addr);
 999
1000                         xhci_warn(xhci, "Port resume timed out, port %d-%d: 0x%x\n",
1001                                   hcd->self.busnum, wIndex + 1, port_status);
1002                         /*
1003                          * keep rexit_active set if U0 transition failed so we
1004                          * know to report PORT_STAT_SUSPEND status back to
1005                          * usbcore. It will be cleared later once the port is
1006                          * out of RESUME/U3 state
1007                          */
1008                 }
1009
1010                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1011                 bus_state->port_c_suspend |= 1 << wIndex;
1012                 bus_state->suspended_ports &= ~(1 << wIndex);
1013         }
1014
1015         return 0;
1016 }
1017
1018 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
1019 {
1020         u32 ext_stat = 0;
1021         int speed_id;
1022
1023         /* only support rx and tx lane counts of 1 in usb3.1 spec */
1024         speed_id = DEV_PORT_SPEED(raw_port_status);
1025         ext_stat |= speed_id;           /* bits 3:0, RX speed id */
1026         ext_stat |= speed_id << 4;      /* bits 7:4, TX speed id */
1027
1028         ext_stat |= PORT_RX_LANES(port_li) << 8;  /* bits 11:8 Rx lane count */
1029         ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
1030
1031         return ext_stat;
1032 }
1033
1034 static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
1035                                       u32 portsc)
1036 {
1037         struct xhci_bus_state *bus_state;
1038         struct xhci_hcd *xhci;
1039         struct usb_hcd *hcd;
1040         u32 link_state;
1041         u32 portnum;
1042
1043         bus_state = &port->rhub->bus_state;
1044         xhci = hcd_to_xhci(port->rhub->hcd);
1045         hcd = port->rhub->hcd;
1046         link_state = portsc & PORT_PLS_MASK;
1047         portnum = port->hcd_portnum;
1048
1049         /* USB3 specific wPortChange bits
1050          *
1051          * Port link change with port in resume state should not be
1052          * reported to usbcore, as this is an internal state to be
1053          * handled by xhci driver. Reporting PLC to usbcore may
1054          * cause usbcore clearing PLC first and port change event
1055          * irq won't be generated.
1056          */
1057
1058         if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
1059                 *status |= USB_PORT_STAT_C_LINK_STATE << 16;
1060         if (portsc & PORT_WRC)
1061                 *status |= USB_PORT_STAT_C_BH_RESET << 16;
1062         if (portsc & PORT_CEC)
1063                 *status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
1064
1065         /* USB3 specific wPortStatus bits */
1066         if (portsc & PORT_POWER)
1067                 *status |= USB_SS_PORT_STAT_POWER;
1068
1069         /* no longer suspended or resuming */
1070         if (link_state != XDEV_U3 &&
1071             link_state != XDEV_RESUME &&
1072             link_state != XDEV_RECOVERY) {
1073                 /* remote wake resume signaling complete */
1074                 if (bus_state->port_remote_wakeup & (1 << portnum)) {
1075                         bus_state->port_remote_wakeup &= ~(1 << portnum);
1076                         usb_hcd_end_port_resume(&hcd->self, portnum);
1077                 }
1078                 bus_state->suspended_ports &= ~(1 << portnum);
1079         }
1080
1081         xhci_hub_report_usb3_link_state(xhci, status, portsc);
1082         xhci_del_comp_mod_timer(xhci, portsc, portnum);
1083 }
1084
1085 static void xhci_get_usb2_port_status(struct xhci_port *port, u32 *status,
1086                                       u32 portsc, unsigned long *flags)
1087 {
1088         struct xhci_bus_state *bus_state;
1089         u32 link_state;
1090         u32 portnum;
1091         int err;
1092
1093         bus_state = &port->rhub->bus_state;
1094         link_state = portsc & PORT_PLS_MASK;
1095         portnum = port->hcd_portnum;
1096
1097         /* USB2 wPortStatus bits */
1098         if (portsc & PORT_POWER) {
1099                 *status |= USB_PORT_STAT_POWER;
1100
1101                 /* link state is only valid if port is powered */
1102                 if (link_state == XDEV_U3)
1103                         *status |= USB_PORT_STAT_SUSPEND;
1104                 if (link_state == XDEV_U2)
1105                         *status |= USB_PORT_STAT_L1;
1106                 if (link_state == XDEV_U0) {
1107                         if (bus_state->suspended_ports & (1 << portnum)) {
1108                                 bus_state->suspended_ports &= ~(1 << portnum);
1109                                 bus_state->port_c_suspend |= 1 << portnum;
1110                         }
1111                 }
1112                 if (link_state == XDEV_RESUME) {
1113                         err = xhci_handle_usb2_port_link_resume(port, portsc,
1114                                                                 flags);
1115                         if (err < 0)
1116                                 *status = 0xffffffff;
1117                         else if (port->resume_timestamp || port->rexit_active)
1118                                 *status |= USB_PORT_STAT_SUSPEND;
1119                 }
1120         }
1121
1122         /*
1123          * Clear usb2 resume signalling variables if port is no longer suspended
1124          * or resuming. Port either resumed to U0/U1/U2, disconnected, or in a
1125          * error state. Resume related variables should be cleared in all those cases.
1126          */
1127         if (link_state != XDEV_U3 && link_state != XDEV_RESUME) {
1128                 if (port->resume_timestamp ||
1129                     test_bit(portnum, &bus_state->resuming_ports)) {
1130                         port->resume_timestamp = 0;
1131                         clear_bit(portnum, &bus_state->resuming_ports);
1132                         usb_hcd_end_port_resume(&port->rhub->hcd->self, portnum);
1133                 }
1134                 port->rexit_active = 0;
1135                 bus_state->suspended_ports &= ~(1 << portnum);
1136         }
1137 }
1138
1139 /*
1140  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
1141  * 3.0 hubs use.
1142  *
1143  * Possible side effects:
1144  *  - Mark a port as being done with device resume,
1145  *    and ring the endpoint doorbells.
1146  *  - Stop the Synopsys redriver Compliance Mode polling.
1147  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
1148  */
1149 static u32 xhci_get_port_status(struct usb_hcd *hcd,
1150                 struct xhci_bus_state *bus_state,
1151         u16 wIndex, u32 raw_port_status,
1152                 unsigned long *flags)
1153         __releases(&xhci->lock)
1154         __acquires(&xhci->lock)
1155 {
1156         u32 status = 0;
1157         struct xhci_hub *rhub;
1158         struct xhci_port *port;
1159
1160         rhub = xhci_get_rhub(hcd);
1161         port = rhub->ports[wIndex];
1162
1163         /* common wPortChange bits */
1164         if (raw_port_status & PORT_CSC)
1165                 status |= USB_PORT_STAT_C_CONNECTION << 16;
1166         if (raw_port_status & PORT_PEC)
1167                 status |= USB_PORT_STAT_C_ENABLE << 16;
1168         if ((raw_port_status & PORT_OCC))
1169                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1170         if ((raw_port_status & PORT_RC))
1171                 status |= USB_PORT_STAT_C_RESET << 16;
1172
1173         /* common wPortStatus bits */
1174         if (raw_port_status & PORT_CONNECT) {
1175                 status |= USB_PORT_STAT_CONNECTION;
1176                 status |= xhci_port_speed(raw_port_status);
1177         }
1178         if (raw_port_status & PORT_PE)
1179                 status |= USB_PORT_STAT_ENABLE;
1180         if (raw_port_status & PORT_OC)
1181                 status |= USB_PORT_STAT_OVERCURRENT;
1182         if (raw_port_status & PORT_RESET)
1183                 status |= USB_PORT_STAT_RESET;
1184
1185         /* USB2 and USB3 specific bits, including Port Link State */
1186         if (hcd->speed >= HCD_USB3)
1187                 xhci_get_usb3_port_status(port, &status, raw_port_status);
1188         else
1189                 xhci_get_usb2_port_status(port, &status, raw_port_status,
1190                                           flags);
1191
1192         if (bus_state->port_c_suspend & (1 << wIndex))
1193                 status |= USB_PORT_STAT_C_SUSPEND << 16;
1194
1195         return status;
1196 }
1197
1198 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1199                 u16 wIndex, char *buf, u16 wLength)
1200 {
1201         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1202         int max_ports;
1203         unsigned long flags;
1204         u32 temp, status;
1205         int retval = 0;
1206         struct xhci_bus_state *bus_state;
1207         u16 link_state = 0;
1208         u16 wake_mask = 0;
1209         u16 timeout = 0;
1210         u16 test_mode = 0;
1211         struct xhci_hub *rhub;
1212         struct xhci_port **ports;
1213         struct xhci_port *port;
1214         int portnum1;
1215
1216         rhub = xhci_get_rhub(hcd);
1217         ports = rhub->ports;
1218         max_ports = rhub->num_ports;
1219         bus_state = &rhub->bus_state;
1220         portnum1 = wIndex & 0xff;
1221
1222         spin_lock_irqsave(&xhci->lock, flags);
1223         switch (typeReq) {
1224         case GetHubStatus:
1225                 /* No power source, over-current reported per port */
1226                 memset(buf, 0, 4);
1227                 break;
1228         case GetHubDescriptor:
1229                 /* Check to make sure userspace is asking for the USB 3.0 hub
1230                  * descriptor for the USB 3.0 roothub.  If not, we stall the
1231                  * endpoint, like external hubs do.
1232                  */
1233                 if (hcd->speed >= HCD_USB3 &&
1234                                 (wLength < USB_DT_SS_HUB_SIZE ||
1235                                  wValue != (USB_DT_SS_HUB << 8))) {
1236                         xhci_dbg(xhci, "Wrong hub descriptor type for "
1237                                         "USB 3.0 roothub.\n");
1238                         goto error;
1239                 }
1240                 xhci_hub_descriptor(hcd, xhci,
1241                                 (struct usb_hub_descriptor *) buf);
1242                 break;
1243         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1244                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1245                         goto error;
1246
1247                 if (hcd->speed < HCD_USB3)
1248                         goto error;
1249
1250                 retval = xhci_create_usb3x_bos_desc(xhci, buf, wLength);
1251                 spin_unlock_irqrestore(&xhci->lock, flags);
1252                 return retval;
1253         case GetPortStatus:
1254                 if (!portnum1 || portnum1 > max_ports)
1255                         goto error;
1256
1257                 wIndex--;
1258                 port = ports[portnum1 - 1];
1259                 temp = readl(port->addr);
1260                 if (temp == ~(u32)0) {
1261                         xhci_hc_died(xhci);
1262                         retval = -ENODEV;
1263                         break;
1264                 }
1265                 trace_xhci_get_port_status(port, temp);
1266                 status = xhci_get_port_status(hcd, bus_state, wIndex, temp,
1267                                               &flags);
1268                 if (status == 0xffffffff)
1269                         goto error;
1270
1271                 xhci_dbg(xhci, "Get port status %d-%d read: 0x%x, return 0x%x",
1272                          hcd->self.busnum, portnum1, temp, status);
1273
1274                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1275                 /* if USB 3.1 extended port status return additional 4 bytes */
1276                 if (wValue == 0x02) {
1277                         u32 port_li;
1278
1279                         if (hcd->speed < HCD_USB31 || wLength != 8) {
1280                                 xhci_err(xhci, "get ext port status invalid parameter\n");
1281                                 retval = -EINVAL;
1282                                 break;
1283                         }
1284                         port_li = readl(port->addr + PORTLI);
1285                         status = xhci_get_ext_port_status(temp, port_li);
1286                         put_unaligned_le32(status, &buf[4]);
1287                 }
1288                 break;
1289         case SetPortFeature:
1290                 if (wValue == USB_PORT_FEAT_LINK_STATE)
1291                         link_state = (wIndex & 0xff00) >> 3;
1292                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1293                         wake_mask = wIndex & 0xff00;
1294                 if (wValue == USB_PORT_FEAT_TEST)
1295                         test_mode = (wIndex & 0xff00) >> 8;
1296                 /* The MSB of wIndex is the U1/U2 timeout */
1297                 timeout = (wIndex & 0xff00) >> 8;
1298
1299                 wIndex &= 0xff;
1300                 if (!portnum1 || portnum1 > max_ports)
1301                         goto error;
1302
1303                 port = ports[portnum1 - 1];
1304                 wIndex--;
1305                 temp = readl(port->addr);
1306                 if (temp == ~(u32)0) {
1307                         xhci_hc_died(xhci);
1308                         retval = -ENODEV;
1309                         break;
1310                 }
1311                 temp = xhci_port_state_to_neutral(temp);
1312                 /* FIXME: What new port features do we need to support? */
1313                 switch (wValue) {
1314                 case USB_PORT_FEAT_SUSPEND:
1315                         temp = readl(port->addr);
1316                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1317                                 /* Resume the port to U0 first */
1318                                 xhci_set_link_state(xhci, port, XDEV_U0);
1319                                 spin_unlock_irqrestore(&xhci->lock, flags);
1320                                 msleep(10);
1321                                 spin_lock_irqsave(&xhci->lock, flags);
1322                         }
1323                         /* In spec software should not attempt to suspend
1324                          * a port unless the port reports that it is in the
1325                          * enabled (PED = ‘1’,PLS < ‘3’) state.
1326                          */
1327                         temp = readl(port->addr);
1328                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1329                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1330                                 xhci_warn(xhci, "USB core suspending port %d-%d not in U0/U1/U2\n",
1331                                           hcd->self.busnum, portnum1);
1332                                 goto error;
1333                         }
1334
1335                         if (!port->slot_id) {
1336                                 xhci_warn(xhci, "slot_id is zero\n");
1337                                 goto error;
1338                         }
1339                         /* unlock to execute stop endpoint commands */
1340                         spin_unlock_irqrestore(&xhci->lock, flags);
1341                         xhci_stop_device(xhci, port->slot_id, 1);
1342                         spin_lock_irqsave(&xhci->lock, flags);
1343
1344                         xhci_set_link_state(xhci, port, XDEV_U3);
1345
1346                         spin_unlock_irqrestore(&xhci->lock, flags);
1347                         msleep(10); /* wait device to enter */
1348                         spin_lock_irqsave(&xhci->lock, flags);
1349
1350                         temp = readl(port->addr);
1351                         bus_state->suspended_ports |= 1 << wIndex;
1352                         break;
1353                 case USB_PORT_FEAT_LINK_STATE:
1354                         temp = readl(port->addr);
1355                         /* Disable port */
1356                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1357                                 xhci_dbg(xhci, "Disable port %d-%d\n",
1358                                          hcd->self.busnum, portnum1);
1359                                 temp = xhci_port_state_to_neutral(temp);
1360                                 /*
1361                                  * Clear all change bits, so that we get a new
1362                                  * connection event.
1363                                  */
1364                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1365                                         PORT_OCC | PORT_RC | PORT_PLC |
1366                                         PORT_CEC;
1367                                 writel(temp | PORT_PE, port->addr);
1368                                 temp = readl(port->addr);
1369                                 break;
1370                         }
1371
1372                         /* Put link in RxDetect (enable port) */
1373                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1374                                 xhci_dbg(xhci, "Enable port %d-%d\n",
1375                                          hcd->self.busnum, portnum1);
1376                                 xhci_set_link_state(xhci, port, link_state);
1377                                 temp = readl(port->addr);
1378                                 break;
1379                         }
1380
1381                         /*
1382                          * For xHCI 1.1 according to section 4.19.1.2.4.1 a
1383                          * root hub port's transition to compliance mode upon
1384                          * detecting LFPS timeout may be controlled by an
1385                          * Compliance Transition Enabled (CTE) flag (not
1386                          * software visible). This flag is set by writing 0xA
1387                          * to PORTSC PLS field which will allow transition to
1388                          * compliance mode the next time LFPS timeout is
1389                          * encountered. A warm reset will clear it.
1390                          *
1391                          * The CTE flag is only supported if the HCCPARAMS2 CTC
1392                          * flag is set, otherwise, the compliance substate is
1393                          * automatically entered as on 1.0 and prior.
1394                          */
1395                         if (link_state == USB_SS_PORT_LS_COMP_MOD) {
1396                                 if (!HCC2_CTC(xhci->hcc_params2)) {
1397                                         xhci_dbg(xhci, "CTC flag is 0, port already supports entering compliance mode\n");
1398                                         break;
1399                                 }
1400
1401                                 if ((temp & PORT_CONNECT)) {
1402                                         xhci_warn(xhci, "Can't set compliance mode when port is connected\n");
1403                                         goto error;
1404                                 }
1405
1406                                 xhci_dbg(xhci, "Enable compliance mode transition for port %d-%d\n",
1407                                          hcd->self.busnum, portnum1);
1408                                 xhci_set_link_state(xhci, port, link_state);
1409
1410                                 temp = readl(port->addr);
1411                                 break;
1412                         }
1413                         /* Port must be enabled */
1414                         if (!(temp & PORT_PE)) {
1415                                 retval = -ENODEV;
1416                                 break;
1417                         }
1418                         /* Can't set port link state above '3' (U3) */
1419                         if (link_state > USB_SS_PORT_LS_U3) {
1420                                 xhci_warn(xhci, "Cannot set port %d-%d link state %d\n",
1421                                           hcd->self.busnum, portnum1, link_state);
1422                                 goto error;
1423                         }
1424
1425                         /*
1426                          * set link to U0, steps depend on current link state.
1427                          * U3: set link to U0 and wait for u3exit completion.
1428                          * U1/U2:  no PLC complete event, only set link to U0.
1429                          * Resume/Recovery: device initiated U0, only wait for
1430                          * completion
1431                          */
1432                         if (link_state == USB_SS_PORT_LS_U0) {
1433                                 u32 pls = temp & PORT_PLS_MASK;
1434                                 bool wait_u0 = false;
1435
1436                                 /* already in U0 */
1437                                 if (pls == XDEV_U0)
1438                                         break;
1439                                 if (pls == XDEV_U3 ||
1440                                     pls == XDEV_RESUME ||
1441                                     pls == XDEV_RECOVERY) {
1442                                         wait_u0 = true;
1443                                         reinit_completion(&port->u3exit_done);
1444                                 }
1445                                 if (pls <= XDEV_U3) /* U1, U2, U3 */
1446                                         xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U0);
1447                                 if (!wait_u0) {
1448                                         if (pls > XDEV_U3)
1449                                                 goto error;
1450                                         break;
1451                                 }
1452                                 spin_unlock_irqrestore(&xhci->lock, flags);
1453                                 if (!wait_for_completion_timeout(&port->u3exit_done,
1454                                                                  msecs_to_jiffies(500)))
1455                                         xhci_dbg(xhci, "missing U0 port change event for port %d-%d\n",
1456                                                  hcd->self.busnum, portnum1);
1457                                 spin_lock_irqsave(&xhci->lock, flags);
1458                                 temp = readl(port->addr);
1459                                 break;
1460                         }
1461
1462                         if (link_state == USB_SS_PORT_LS_U3) {
1463                                 int retries = 16;
1464                                 if (port->slot_id) {
1465                                         /* unlock to execute stop endpoint
1466                                          * commands */
1467                                         spin_unlock_irqrestore(&xhci->lock,
1468                                                                 flags);
1469                                         xhci_stop_device(xhci, port->slot_id, 1);
1470                                         spin_lock_irqsave(&xhci->lock, flags);
1471                                 }
1472                                 xhci_set_link_state(xhci, port, USB_SS_PORT_LS_U3);
1473                                 spin_unlock_irqrestore(&xhci->lock, flags);
1474                                 while (retries--) {
1475                                         usleep_range(4000, 8000);
1476                                         temp = readl(port->addr);
1477                                         if ((temp & PORT_PLS_MASK) == XDEV_U3)
1478                                                 break;
1479                                 }
1480                                 spin_lock_irqsave(&xhci->lock, flags);
1481                                 temp = readl(port->addr);
1482                                 bus_state->suspended_ports |= 1 << wIndex;
1483                         }
1484                         break;
1485                 case USB_PORT_FEAT_POWER:
1486                         /*
1487                          * Turn on ports, even if there isn't per-port switching.
1488                          * HC will report connect events even before this is set.
1489                          * However, hub_wq will ignore the roothub events until
1490                          * the roothub is registered.
1491                          */
1492                         xhci_set_port_power(xhci, port, true, &flags);
1493                         break;
1494                 case USB_PORT_FEAT_RESET:
1495                         temp = (temp | PORT_RESET);
1496                         writel(temp, port->addr);
1497
1498                         temp = readl(port->addr);
1499                         xhci_dbg(xhci, "set port reset, actual port %d-%d status  = 0x%x\n",
1500                                  hcd->self.busnum, portnum1, temp);
1501                         break;
1502                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1503                         xhci_set_remote_wake_mask(xhci, port, wake_mask);
1504                         temp = readl(port->addr);
1505                         xhci_dbg(xhci, "set port remote wake mask, actual port %d-%d status  = 0x%x\n",
1506                                  hcd->self.busnum, portnum1, temp);
1507                         break;
1508                 case USB_PORT_FEAT_BH_PORT_RESET:
1509                         temp |= PORT_WR;
1510                         writel(temp, port->addr);
1511                         temp = readl(port->addr);
1512                         break;
1513                 case USB_PORT_FEAT_U1_TIMEOUT:
1514                         if (hcd->speed < HCD_USB3)
1515                                 goto error;
1516                         temp = readl(port->addr + PORTPMSC);
1517                         temp &= ~PORT_U1_TIMEOUT_MASK;
1518                         temp |= PORT_U1_TIMEOUT(timeout);
1519                         writel(temp, port->addr + PORTPMSC);
1520                         break;
1521                 case USB_PORT_FEAT_U2_TIMEOUT:
1522                         if (hcd->speed < HCD_USB3)
1523                                 goto error;
1524                         temp = readl(port->addr + PORTPMSC);
1525                         temp &= ~PORT_U2_TIMEOUT_MASK;
1526                         temp |= PORT_U2_TIMEOUT(timeout);
1527                         writel(temp, port->addr + PORTPMSC);
1528                         break;
1529                 case USB_PORT_FEAT_TEST:
1530                         /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1531                         if (hcd->speed != HCD_USB2)
1532                                 goto error;
1533                         if (test_mode > USB_TEST_FORCE_ENABLE ||
1534                             test_mode < USB_TEST_J)
1535                                 goto error;
1536                         retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1537                                                       &flags);
1538                         break;
1539                 default:
1540                         goto error;
1541                 }
1542                 /* unblock any posted writes */
1543                 temp = readl(port->addr);
1544                 break;
1545         case ClearPortFeature:
1546                 if (!portnum1 || portnum1 > max_ports)
1547                         goto error;
1548
1549                 port = ports[portnum1 - 1];
1550
1551                 wIndex--;
1552                 temp = readl(port->addr);
1553                 if (temp == ~(u32)0) {
1554                         xhci_hc_died(xhci);
1555                         retval = -ENODEV;
1556                         break;
1557                 }
1558                 /* FIXME: What new port features do we need to support? */
1559                 temp = xhci_port_state_to_neutral(temp);
1560                 switch (wValue) {
1561                 case USB_PORT_FEAT_SUSPEND:
1562                         temp = readl(port->addr);
1563                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1564                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
1565                         if (temp & PORT_RESET)
1566                                 goto error;
1567                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1568                                 if ((temp & PORT_PE) == 0)
1569                                         goto error;
1570
1571                                 set_bit(wIndex, &bus_state->resuming_ports);
1572                                 usb_hcd_start_port_resume(&hcd->self, wIndex);
1573                                 xhci_set_link_state(xhci, port, XDEV_RESUME);
1574                                 spin_unlock_irqrestore(&xhci->lock, flags);
1575                                 msleep(USB_RESUME_TIMEOUT);
1576                                 spin_lock_irqsave(&xhci->lock, flags);
1577                                 xhci_set_link_state(xhci, port, XDEV_U0);
1578                                 clear_bit(wIndex, &bus_state->resuming_ports);
1579                                 usb_hcd_end_port_resume(&hcd->self, wIndex);
1580                         }
1581                         bus_state->port_c_suspend |= 1 << wIndex;
1582
1583                         if (!port->slot_id) {
1584                                 xhci_dbg(xhci, "slot_id is zero\n");
1585                                 goto error;
1586                         }
1587                         xhci_ring_device(xhci, port->slot_id);
1588                         break;
1589                 case USB_PORT_FEAT_C_SUSPEND:
1590                         bus_state->port_c_suspend &= ~(1 << wIndex);
1591                         fallthrough;
1592                 case USB_PORT_FEAT_C_RESET:
1593                 case USB_PORT_FEAT_C_BH_PORT_RESET:
1594                 case USB_PORT_FEAT_C_CONNECTION:
1595                 case USB_PORT_FEAT_C_OVER_CURRENT:
1596                 case USB_PORT_FEAT_C_ENABLE:
1597                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1598                 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1599                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1600                                         port->addr, temp);
1601                         break;
1602                 case USB_PORT_FEAT_ENABLE:
1603                         xhci_disable_port(xhci, port);
1604                         break;
1605                 case USB_PORT_FEAT_POWER:
1606                         xhci_set_port_power(xhci, port, false, &flags);
1607                         break;
1608                 case USB_PORT_FEAT_TEST:
1609                         retval = xhci_exit_test_mode(xhci);
1610                         break;
1611                 default:
1612                         goto error;
1613                 }
1614                 break;
1615         default:
1616 error:
1617                 /* "stall" on error */
1618                 retval = -EPIPE;
1619         }
1620         spin_unlock_irqrestore(&xhci->lock, flags);
1621         return retval;
1622 }
1623 EXPORT_SYMBOL_GPL(xhci_hub_control);
1624
1625 /*
1626  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1627  * Ports are 0-indexed from the HCD point of view,
1628  * and 1-indexed from the USB core pointer of view.
1629  *
1630  * Note that the status change bits will be cleared as soon as a port status
1631  * change event is generated, so we use the saved status from that event.
1632  */
1633 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1634 {
1635         unsigned long flags;
1636         u32 temp, status;
1637         u32 mask;
1638         int i, retval;
1639         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1640         int max_ports;
1641         struct xhci_bus_state *bus_state;
1642         bool reset_change = false;
1643         struct xhci_hub *rhub;
1644         struct xhci_port **ports;
1645
1646         rhub = xhci_get_rhub(hcd);
1647         ports = rhub->ports;
1648         max_ports = rhub->num_ports;
1649         bus_state = &rhub->bus_state;
1650
1651         /* Initial status is no changes */
1652         retval = (max_ports + 8) / 8;
1653         memset(buf, 0, retval);
1654
1655         /*
1656          * Inform the usbcore about resume-in-progress by returning
1657          * a non-zero value even if there are no status changes.
1658          */
1659         spin_lock_irqsave(&xhci->lock, flags);
1660
1661         status = bus_state->resuming_ports;
1662
1663         /*
1664          * SS devices are only visible to roothub after link training completes.
1665          * Keep polling roothubs for a grace period after xHC start
1666          */
1667         if (xhci->run_graceperiod) {
1668                 if (time_before(jiffies, xhci->run_graceperiod))
1669                         status = 1;
1670                 else
1671                         xhci->run_graceperiod = 0;
1672         }
1673
1674         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1675
1676         /* For each port, did anything change?  If so, set that bit in buf. */
1677         for (i = 0; i < max_ports; i++) {
1678                 temp = readl(ports[i]->addr);
1679                 if (temp == ~(u32)0) {
1680                         xhci_hc_died(xhci);
1681                         retval = -ENODEV;
1682                         break;
1683                 }
1684                 trace_xhci_hub_status_data(ports[i], temp);
1685
1686                 if ((temp & mask) != 0 ||
1687                         (bus_state->port_c_suspend & 1 << i) ||
1688                         (ports[i]->resume_timestamp && time_after_eq(
1689                             jiffies, ports[i]->resume_timestamp))) {
1690                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1691                         status = 1;
1692                 }
1693                 if ((temp & PORT_RC))
1694                         reset_change = true;
1695                 if (temp & PORT_OC)
1696                         status = 1;
1697         }
1698         if (!status && !reset_change) {
1699                 xhci_dbg(xhci, "%s: stopping usb%d port polling\n",
1700                          __func__, hcd->self.busnum);
1701                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1702         }
1703         spin_unlock_irqrestore(&xhci->lock, flags);
1704         return status ? retval : 0;
1705 }
1706
1707 #ifdef CONFIG_PM
1708
1709 int xhci_bus_suspend(struct usb_hcd *hcd)
1710 {
1711         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1712         int max_ports, port_index;
1713         struct xhci_bus_state *bus_state;
1714         unsigned long flags;
1715         struct xhci_hub *rhub;
1716         struct xhci_port **ports;
1717         u32 portsc_buf[USB_MAXCHILDREN];
1718         bool wake_enabled;
1719
1720         rhub = xhci_get_rhub(hcd);
1721         ports = rhub->ports;
1722         max_ports = rhub->num_ports;
1723         bus_state = &rhub->bus_state;
1724         wake_enabled = hcd->self.root_hub->do_remote_wakeup;
1725
1726         spin_lock_irqsave(&xhci->lock, flags);
1727
1728         if (wake_enabled) {
1729                 if (bus_state->resuming_ports ||        /* USB2 */
1730                     bus_state->port_remote_wakeup) {    /* USB3 */
1731                         spin_unlock_irqrestore(&xhci->lock, flags);
1732                         xhci_dbg(xhci, "usb%d bus suspend to fail because a port is resuming\n",
1733                                  hcd->self.busnum);
1734                         return -EBUSY;
1735                 }
1736         }
1737         /*
1738          * Prepare ports for suspend, but don't write anything before all ports
1739          * are checked and we know bus suspend can proceed
1740          */
1741         bus_state->bus_suspended = 0;
1742         port_index = max_ports;
1743         while (port_index--) {
1744                 u32 t1, t2;
1745                 int retries = 10;
1746 retry:
1747                 t1 = readl(ports[port_index]->addr);
1748                 t2 = xhci_port_state_to_neutral(t1);
1749                 portsc_buf[port_index] = 0;
1750
1751                 /*
1752                  * Give a USB3 port in link training time to finish, but don't
1753                  * prevent suspend as port might be stuck
1754                  */
1755                 if ((hcd->speed >= HCD_USB3) && retries-- &&
1756                     (t1 & PORT_PLS_MASK) == XDEV_POLLING) {
1757                         spin_unlock_irqrestore(&xhci->lock, flags);
1758                         msleep(XHCI_PORT_POLLING_LFPS_TIME);
1759                         spin_lock_irqsave(&xhci->lock, flags);
1760                         xhci_dbg(xhci, "port %d-%d polling in bus suspend, waiting\n",
1761                                  hcd->self.busnum, port_index + 1);
1762                         goto retry;
1763                 }
1764                 /* bail out if port detected a over-current condition */
1765                 if (t1 & PORT_OC) {
1766                         bus_state->bus_suspended = 0;
1767                         spin_unlock_irqrestore(&xhci->lock, flags);
1768                         xhci_dbg(xhci, "Bus suspend bailout, port over-current detected\n");
1769                         return -EBUSY;
1770                 }
1771                 /* suspend ports in U0, or bail out for new connect changes */
1772                 if ((t1 & PORT_PE) && (t1 & PORT_PLS_MASK) == XDEV_U0) {
1773                         if ((t1 & PORT_CSC) && wake_enabled) {
1774                                 bus_state->bus_suspended = 0;
1775                                 spin_unlock_irqrestore(&xhci->lock, flags);
1776                                 xhci_dbg(xhci, "Bus suspend bailout, port connect change\n");
1777                                 return -EBUSY;
1778                         }
1779                         xhci_dbg(xhci, "port %d-%d not suspended\n",
1780                                  hcd->self.busnum, port_index + 1);
1781                         t2 &= ~PORT_PLS_MASK;
1782                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1783                         set_bit(port_index, &bus_state->bus_suspended);
1784                 }
1785                 /* USB core sets remote wake mask for USB 3.0 hubs,
1786                  * including the USB 3.0 roothub, but only if CONFIG_PM
1787                  * is enabled, so also enable remote wake here.
1788                  */
1789                 if (wake_enabled) {
1790                         if (t1 & PORT_CONNECT) {
1791                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1792                                 t2 &= ~PORT_WKCONN_E;
1793                         } else {
1794                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1795                                 t2 &= ~PORT_WKDISC_E;
1796                         }
1797
1798                         if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1799                             (hcd->speed < HCD_USB3)) {
1800                                 if (usb_amd_pt_check_port(hcd->self.controller,
1801                                                           port_index))
1802                                         t2 &= ~PORT_WAKE_BITS;
1803                         }
1804                 } else
1805                         t2 &= ~PORT_WAKE_BITS;
1806
1807                 t1 = xhci_port_state_to_neutral(t1);
1808                 if (t1 != t2)
1809                         portsc_buf[port_index] = t2;
1810         }
1811
1812         /* write port settings, stopping and suspending ports if needed */
1813         port_index = max_ports;
1814         while (port_index--) {
1815                 if (!portsc_buf[port_index])
1816                         continue;
1817                 if (test_bit(port_index, &bus_state->bus_suspended)) {
1818                         int slot_id = ports[port_index]->slot_id;
1819                         if (slot_id) {
1820                                 spin_unlock_irqrestore(&xhci->lock, flags);
1821                                 xhci_stop_device(xhci, slot_id, 1);
1822                                 spin_lock_irqsave(&xhci->lock, flags);
1823                         }
1824                 }
1825                 writel(portsc_buf[port_index], ports[port_index]->addr);
1826         }
1827         hcd->state = HC_STATE_SUSPENDED;
1828         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1829         spin_unlock_irqrestore(&xhci->lock, flags);
1830
1831         if (bus_state->bus_suspended)
1832                 usleep_range(5000, 10000);
1833
1834         return 0;
1835 }
1836
1837 /*
1838  * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1839  * warm reset a USB3 device stuck in polling or compliance mode after resume.
1840  * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1841  */
1842 static bool xhci_port_missing_cas_quirk(struct xhci_port *port)
1843 {
1844         u32 portsc;
1845
1846         portsc = readl(port->addr);
1847
1848         /* if any of these are set we are not stuck */
1849         if (portsc & (PORT_CONNECT | PORT_CAS))
1850                 return false;
1851
1852         if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1853             ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1854                 return false;
1855
1856         /* clear wakeup/change bits, and do a warm port reset */
1857         portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1858         portsc |= PORT_WR;
1859         writel(portsc, port->addr);
1860         /* flush write */
1861         readl(port->addr);
1862         return true;
1863 }
1864
1865 int xhci_bus_resume(struct usb_hcd *hcd)
1866 {
1867         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1868         struct xhci_bus_state *bus_state;
1869         unsigned long flags;
1870         int max_ports, port_index;
1871         int sret;
1872         u32 next_state;
1873         u32 temp, portsc;
1874         struct xhci_hub *rhub;
1875         struct xhci_port **ports;
1876
1877         rhub = xhci_get_rhub(hcd);
1878         ports = rhub->ports;
1879         max_ports = rhub->num_ports;
1880         bus_state = &rhub->bus_state;
1881
1882         if (time_before(jiffies, bus_state->next_statechange))
1883                 msleep(5);
1884
1885         spin_lock_irqsave(&xhci->lock, flags);
1886         if (!HCD_HW_ACCESSIBLE(hcd)) {
1887                 spin_unlock_irqrestore(&xhci->lock, flags);
1888                 return -ESHUTDOWN;
1889         }
1890
1891         /* delay the irqs */
1892         temp = readl(&xhci->op_regs->command);
1893         temp &= ~CMD_EIE;
1894         writel(temp, &xhci->op_regs->command);
1895
1896         /* bus specific resume for ports we suspended at bus_suspend */
1897         if (hcd->speed >= HCD_USB3)
1898                 next_state = XDEV_U0;
1899         else
1900                 next_state = XDEV_RESUME;
1901
1902         port_index = max_ports;
1903         while (port_index--) {
1904                 portsc = readl(ports[port_index]->addr);
1905
1906                 /* warm reset CAS limited ports stuck in polling/compliance */
1907                 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1908                     (hcd->speed >= HCD_USB3) &&
1909                     xhci_port_missing_cas_quirk(ports[port_index])) {
1910                         xhci_dbg(xhci, "reset stuck port %d-%d\n",
1911                                  hcd->self.busnum, port_index + 1);
1912                         clear_bit(port_index, &bus_state->bus_suspended);
1913                         continue;
1914                 }
1915                 /* resume if we suspended the link, and it is still suspended */
1916                 if (test_bit(port_index, &bus_state->bus_suspended))
1917                         switch (portsc & PORT_PLS_MASK) {
1918                         case XDEV_U3:
1919                                 portsc = xhci_port_state_to_neutral(portsc);
1920                                 portsc &= ~PORT_PLS_MASK;
1921                                 portsc |= PORT_LINK_STROBE | next_state;
1922                                 break;
1923                         case XDEV_RESUME:
1924                                 /* resume already initiated */
1925                                 break;
1926                         default:
1927                                 /* not in a resumable state, ignore it */
1928                                 clear_bit(port_index,
1929                                           &bus_state->bus_suspended);
1930                                 break;
1931                         }
1932                 /* disable wake for all ports, write new link state if needed */
1933                 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1934                 writel(portsc, ports[port_index]->addr);
1935         }
1936
1937         /* USB2 specific resume signaling delay and U0 link state transition */
1938         if (hcd->speed < HCD_USB3) {
1939                 if (bus_state->bus_suspended) {
1940                         spin_unlock_irqrestore(&xhci->lock, flags);
1941                         msleep(USB_RESUME_TIMEOUT);
1942                         spin_lock_irqsave(&xhci->lock, flags);
1943                 }
1944                 for_each_set_bit(port_index, &bus_state->bus_suspended,
1945                                  BITS_PER_LONG) {
1946                         /* Clear PLC to poll it later for U0 transition */
1947                         xhci_test_and_clear_bit(xhci, ports[port_index],
1948                                                 PORT_PLC);
1949                         xhci_set_link_state(xhci, ports[port_index], XDEV_U0);
1950                 }
1951         }
1952
1953         /* poll for U0 link state complete, both USB2 and USB3 */
1954         for_each_set_bit(port_index, &bus_state->bus_suspended, BITS_PER_LONG) {
1955                 sret = xhci_handshake(ports[port_index]->addr, PORT_PLC,
1956                                       PORT_PLC, 10 * 1000);
1957                 if (sret) {
1958                         xhci_warn(xhci, "port %d-%d resume PLC timeout\n",
1959                                   hcd->self.busnum, port_index + 1);
1960                         continue;
1961                 }
1962                 xhci_test_and_clear_bit(xhci, ports[port_index], PORT_PLC);
1963                 if (ports[port_index]->slot_id)
1964                         xhci_ring_device(xhci, ports[port_index]->slot_id);
1965         }
1966         (void) readl(&xhci->op_regs->command);
1967
1968         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1969         /* re-enable irqs */
1970         temp = readl(&xhci->op_regs->command);
1971         temp |= CMD_EIE;
1972         writel(temp, &xhci->op_regs->command);
1973         temp = readl(&xhci->op_regs->command);
1974
1975         spin_unlock_irqrestore(&xhci->lock, flags);
1976         return 0;
1977 }
1978
1979 unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd)
1980 {
1981         struct xhci_hub *rhub = xhci_get_rhub(hcd);
1982
1983         /* USB3 port wakeups are reported via usb_wakeup_notification() */
1984         return rhub->bus_state.resuming_ports;  /* USB2 ports only */
1985 }
1986
1987 #endif  /* CONFIG_PM */