drivers/gpu/drm/vc4/vc4_crtc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 CRTC module
   8  *
   9  * In VC4, the Pixel Valve is what most closely corresponds to the
  10  * DRM's concept of a CRTC.  The PV generates video timings from the
  11  * encoder's clock plus its configuration.  It pulls scaled pixels from
  12  * the HVS at that timing, and feeds it to the encoder.
  13  *
  14  * However, the DRM CRTC also collects the configuration of all the
  15  * DRM planes attached to it.  As a result, the CRTC is also
  16  * responsible for writing the display list for the HVS channel that
  17  * the CRTC will use.
  18  *
  19  * The 2835 has 3 different pixel valves.  pv0 in the audio power
  20  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
  21  * image domain can feed either HDMI or the SDTV controller.  The
  22  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
  23  * SDTV, etc.) according to which output type is chosen in the mux.
  24  *
  25  * For power management, the pixel valve's registers are all clocked
  26  * by the AXI clock, while the timings and FIFOs make use of the
  27  * output-specific clock.  Since the encoders also directly consume
  28  * the CPRMAN clocks, and know what timings they need, they are the
  29  * ones that set the clock.
  30  */
  31
  32 #include <linux/clk.h>
  33 #include <linux/component.h>
  34 #include <linux/of_device.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #include <drm/drm_atomic.h>
  38 #include <drm/drm_atomic_helper.h>
  39 #include <drm/drm_atomic_uapi.h>
  40 #include <drm/drm_fb_cma_helper.h>
  41 #include <drm/drm_print.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_vblank.h>
  44
  45 #include "vc4_drv.h"
  46 #include "vc4_hdmi.h"
  47 #include "vc4_regs.h"
  48
  49 #define HVS_FIFO_LATENCY_PIX    6
  50
  51 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  52 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
  53
  54 static const struct debugfs_reg32 crtc_regs[] = {
  55         VC4_REG32(PV_CONTROL),
  56         VC4_REG32(PV_V_CONTROL),
  57         VC4_REG32(PV_VSYNCD_EVEN),
  58         VC4_REG32(PV_HORZA),
  59         VC4_REG32(PV_HORZB),
  60         VC4_REG32(PV_VERTA),
  61         VC4_REG32(PV_VERTB),
  62         VC4_REG32(PV_VERTA_EVEN),
  63         VC4_REG32(PV_VERTB_EVEN),
  64         VC4_REG32(PV_INTEN),
  65         VC4_REG32(PV_INTSTAT),
  66         VC4_REG32(PV_STAT),
  67         VC4_REG32(PV_HACT_ACT),
  68 };
  69
  70 static unsigned int
  71 vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
  72 {
  73         struct vc4_hvs *hvs = vc4->hvs;
  74         u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
  75         /* Top/base are supposed to be 4-pixel aligned, but the
  76          * Raspberry Pi firmware fills the low bits (which are
  77          * presumably ignored).
  78          */
  79         u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
  80         u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
  81
  82         return top - base + 4;
  83 }
  84
  85 static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
  86                                           bool in_vblank_irq,
  87                                           int *vpos, int *hpos,
  88                                           ktime_t *stime, ktime_t *etime,
  89                                           const struct drm_display_mode *mode)
  90 {
  91         struct drm_device *dev = crtc->dev;
  92         struct vc4_dev *vc4 = to_vc4_dev(dev);
  93         struct vc4_hvs *hvs = vc4->hvs;
  94         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  95         struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
  96         unsigned int cob_size;
  97         u32 val;
  98         int fifo_lines;
  99         int vblank_lines;
 100         bool ret = false;
 101
 102         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 103
 104         /* Get optional system timestamp before query. */
 105         if (stime)
 106                 *stime = ktime_get();
 107
 108         /*
 109          * Read vertical scanline which is currently composed for our
 110          * pixelvalve by the HVS, and also the scaler status.
 111          */
 112         val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel));
 113
 114         /* Get optional system timestamp after query. */
 115         if (etime)
 116                 *etime = ktime_get();
 117
 118         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 119
 120         /* Vertical position of hvs composed scanline. */
 121         *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
 122         *hpos = 0;
 123
 124         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 125                 *vpos /= 2;
 126
 127                 /* Use hpos to correct for field offset in interlaced mode. */
 128                 if (vc4_hvs_get_fifo_frame_count(hvs, vc4_crtc_state->assigned_channel) % 2)
 129                         *hpos += mode->crtc_htotal / 2;
 130         }
 131
 132         cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel);
 133         /* This is the offset we need for translating hvs -> pv scanout pos. */
 134         fifo_lines = cob_size / mode->crtc_hdisplay;
 135
 136         if (fifo_lines > 0)
 137                 ret = true;
 138
 139         /* HVS more than fifo_lines into frame for compositing? */
 140         if (*vpos > fifo_lines) {
 141                 /*
 142                  * We are in active scanout and can get some meaningful results
 143                  * from HVS. The actual PV scanout can not trail behind more
 144                  * than fifo_lines as that is the fifo's capacity. Assume that
 145                  * in active scanout the HVS and PV work in lockstep wrt. HVS
 146                  * refilling the fifo and PV consuming from the fifo, ie.
 147                  * whenever the PV consumes and frees up a scanline in the
 148                  * fifo, the HVS will immediately refill it, therefore
 149                  * incrementing vpos. Therefore we choose HVS read position -
 150                  * fifo size in scanlines as a estimate of the real scanout
 151                  * position of the PV.
 152                  */
 153                 *vpos -= fifo_lines + 1;
 154
 155                 return ret;
 156         }
 157
 158         /*
 159          * Less: This happens when we are in vblank and the HVS, after getting
 160          * the VSTART restart signal from the PV, just started refilling its
 161          * fifo with new lines from the top-most lines of the new framebuffers.
 162          * The PV does not scan out in vblank, so does not remove lines from
 163          * the fifo, so the fifo will be full quickly and the HVS has to pause.
 164          * We can't get meaningful readings wrt. scanline position of the PV
 165          * and need to make things up in a approximative but consistent way.
 166          */
 167         vblank_lines = mode->vtotal - mode->vdisplay;
 168
 169         if (in_vblank_irq) {
 170                 /*
 171                  * Assume the irq handler got called close to first
 172                  * line of vblank, so PV has about a full vblank
 173                  * scanlines to go, and as a base timestamp use the
 174                  * one taken at entry into vblank irq handler, so it
 175                  * is not affected by random delays due to lock
 176                  * contention on event_lock or vblank_time lock in
 177                  * the core.
 178                  */
 179                 *vpos = -vblank_lines;
 180
 181                 if (stime)
 182                         *stime = vc4_crtc->t_vblank;
 183                 if (etime)
 184                         *etime = vc4_crtc->t_vblank;
 185
 186                 /*
 187                  * If the HVS fifo is not yet full then we know for certain
 188                  * we are at the very beginning of vblank, as the hvs just
 189                  * started refilling, and the stime and etime timestamps
 190                  * truly correspond to start of vblank.
 191                  *
 192                  * Unfortunately there's no way to report this to upper levels
 193                  * and make it more useful.
 194                  */
 195         } else {
 196                 /*
 197                  * No clue where we are inside vblank. Return a vpos of zero,
 198                  * which will cause calling code to just return the etime
 199                  * timestamp uncorrected. At least this is no worse than the
 200                  * standard fallback.
 201                  */
 202                 *vpos = 0;
 203         }
 204
 205         return ret;
 206 }
 207
 208 void vc4_crtc_destroy(struct drm_crtc *crtc)
 209 {
 210         drm_crtc_cleanup(crtc);
 211 }
 212
 213 static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 214 {
 215         const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
 216         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 217         struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
 218         u32 fifo_len_bytes = pv_data->fifo_depth;
 219
 220         /*
 221          * Pixels are pulled from the HVS if the number of bytes is
 222          * lower than the FIFO full level.
 223          *
 224          * The latency of the pixel fetch mechanism is 6 pixels, so we
 225          * need to convert those 6 pixels in bytes, depending on the
 226          * format, and then subtract that from the length of the FIFO
 227          * to make sure we never end up in a situation where the FIFO
 228          * is full.
 229          */
 230         switch (format) {
 231         case PV_CONTROL_FORMAT_DSIV_16:
 232         case PV_CONTROL_FORMAT_DSIC_16:
 233                 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
 234         case PV_CONTROL_FORMAT_DSIV_18:
 235                 return fifo_len_bytes - 14;
 236         case PV_CONTROL_FORMAT_24:
 237         case PV_CONTROL_FORMAT_DSIV_24:
 238         default:
 239                 /*
 240                  * For some reason, the pixelvalve4 doesn't work with
 241                  * the usual formula and will only work with 32.
 242                  */
 243                 if (crtc_data->hvs_output == 5)
 244                         return 32;
 245
 246                 /*
 247                  * It looks like in some situations, we will overflow
 248                  * the PixelValve FIFO (with the bit 10 of PV stat being
 249                  * set) and stall the HVS / PV, eventually resulting in
 250                  * a page flip timeout.
 251                  *
 252                  * Displaying the video overlay during a playback with
 253                  * Kodi on an RPi3 seems to be a great solution with a
 254                  * failure rate around 50%.
 255                  *
 256                  * Removing 1 from the FIFO full level however
 257                  * seems to completely remove that issue.
 258                  */
 259                 if (!vc4->is_vc5)
 260                         return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
 261
 262                 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 263         }
 264 }
 265
 266 static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
 267                                              u32 format)
 268 {
 269         u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
 270         u32 ret = 0;
 271
 272         ret |= VC4_SET_FIELD((level >> 6),
 273                              PV5_CONTROL_FIFO_LEVEL_HIGH);
 274
 275         return ret | VC4_SET_FIELD(level & 0x3f,
 276                                    PV_CONTROL_FIFO_LEVEL);
 277 }
 278
 279 /*
 280  * Returns the encoder attached to the CRTC.
 281  *
 282  * VC4 can only scan out to one encoder at a time, while the DRM core
 283  * allows drivers to push pixels to more than one encoder from the
 284  * same CRTC.
 285  */
 286 struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
 287                                          struct drm_crtc_state *state)
 288 {
 289         struct drm_encoder *encoder;
 290
 291         WARN_ON(hweight32(state->encoder_mask) > 1);
 292
 293         drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
 294                 return encoder;
 295
 296         return NULL;
 297 }
 298
 299 static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
 300 {
 301         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 302
 303         /* The PV needs to be disabled before it can be flushed */
 304         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
 305         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
 306 }
 307
 308 static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder,
 309                                struct drm_atomic_state *state)
 310 {
 311         struct drm_device *dev = crtc->dev;
 312         struct vc4_dev *vc4 = to_vc4_dev(dev);
 313         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 314         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 315         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 316         struct drm_crtc_state *crtc_state = crtc->state;
 317         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 318         bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
 319         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 320         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
 321                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
 322         u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
 323         u8 ppc = pv_data->pixels_per_clock;
 324         bool debug_dump_regs = false;
 325
 326         if (debug_dump_regs) {
 327                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 328                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
 329                          drm_crtc_index(crtc));
 330                 drm_print_regset32(&p, &vc4_crtc->regset);
 331         }
 332
 333         vc4_crtc_pixelvalve_reset(crtc);
 334
 335         CRTC_WRITE(PV_HORZA,
 336                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
 337                                  PV_HORZA_HBP) |
 338                    VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
 339                                  PV_HORZA_HSYNC));
 340
 341         CRTC_WRITE(PV_HORZB,
 342                    VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
 343                                  PV_HORZB_HFP) |
 344                    VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
 345                                  PV_HORZB_HACTIVE));
 346
 347         CRTC_WRITE(PV_VERTA,
 348                    VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 349                                  PV_VERTA_VBP) |
 350                    VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 351                                  PV_VERTA_VSYNC));
 352         CRTC_WRITE(PV_VERTB,
 353                    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 354                                  PV_VERTB_VFP) |
 355                    VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 356
 357         if (interlace) {
 358                 CRTC_WRITE(PV_VERTA_EVEN,
 359                            VC4_SET_FIELD(mode->crtc_vtotal -
 360                                          mode->crtc_vsync_end - 1,
 361                                          PV_VERTA_VBP) |
 362                            VC4_SET_FIELD(mode->crtc_vsync_end -
 363                                          mode->crtc_vsync_start,
 364                                          PV_VERTA_VSYNC));
 365                 CRTC_WRITE(PV_VERTB_EVEN,
 366                            VC4_SET_FIELD(mode->crtc_vsync_start -
 367                                          mode->crtc_vdisplay,
 368                                          PV_VERTB_VFP) |
 369                            VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
 370
 371                 /* We set up first field even mode for HDMI.  VEC's
 372                  * NTSC mode would want first field odd instead, once
 373                  * we support it (to do so, set ODD_FIRST and put the
 374                  * delay in VSYNCD_EVEN instead).
 375                  */
 376                 CRTC_WRITE(PV_V_CONTROL,
 377                            PV_VCONTROL_CONTINUOUS |
 378                            (is_dsi ? PV_VCONTROL_DSI : 0) |
 379                            PV_VCONTROL_INTERLACE |
 380                            VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
 381                                          PV_VCONTROL_ODD_DELAY));
 382                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
 383         } else {
 384                 CRTC_WRITE(PV_V_CONTROL,
 385                            PV_VCONTROL_CONTINUOUS |
 386                            (is_dsi ? PV_VCONTROL_DSI : 0));
 387         }
 388
 389         if (is_dsi)
 390                 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
 391
 392         if (vc4->is_vc5)
 393                 CRTC_WRITE(PV_MUX_CFG,
 394                            VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
 395                                          PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
 396
 397         CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
 398                    vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
 399                    VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
 400                    VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
 401                    PV_CONTROL_CLR_AT_START |
 402                    PV_CONTROL_TRIGGER_UNDERFLOW |
 403                    PV_CONTROL_WAIT_HSTART |
 404                    VC4_SET_FIELD(vc4_encoder->clock_select,
 405                                  PV_CONTROL_CLK_SELECT));
 406
 407         if (debug_dump_regs) {
 408                 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
 409                 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
 410                          drm_crtc_index(crtc));
 411                 drm_print_regset32(&p, &vc4_crtc->regset);
 412         }
 413 }
 414
 415 static void require_hvs_enabled(struct drm_device *dev)
 416 {
 417         struct vc4_dev *vc4 = to_vc4_dev(dev);
 418         struct vc4_hvs *hvs = vc4->hvs;
 419
 420         WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
 421                      SCALER_DISPCTRL_ENABLE);
 422 }
 423
 424 static int vc4_crtc_disable(struct drm_crtc *crtc,
 425                             struct drm_encoder *encoder,
 426                             struct drm_atomic_state *state,
 427                             unsigned int channel)
 428 {
 429         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 430         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 431         struct drm_device *dev = crtc->dev;
 432         struct vc4_dev *vc4 = to_vc4_dev(dev);
 433         int ret;
 434
 435         CRTC_WRITE(PV_V_CONTROL,
 436                    CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
 437         ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
 438         WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
 439
 440         /*
 441          * This delay is needed to avoid to get a pixel stuck in an
 442          * unflushable FIFO between the pixelvalve and the HDMI
 443          * controllers on the BCM2711.
 444          *
 445          * Timing is fairly sensitive here, so mdelay is the safest
 446          * approach.
 447          *
 448          * If it was to be reworked, the stuck pixel happens on a
 449          * BCM2711 when changing mode with a good probability, so a
 450          * script that changes mode on a regular basis should trigger
 451          * the bug after less than 10 attempts. It manifests itself with
 452          * every pixels being shifted by one to the right, and thus the
 453          * last pixel of a line actually being displayed as the first
 454          * pixel on the next line.
 455          */
 456         mdelay(20);
 457
 458         if (vc4_encoder && vc4_encoder->post_crtc_disable)
 459                 vc4_encoder->post_crtc_disable(encoder, state);
 460
 461         vc4_crtc_pixelvalve_reset(crtc);
 462         vc4_hvs_stop_channel(vc4->hvs, channel);
 463
 464         if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
 465                 vc4_encoder->post_crtc_powerdown(encoder, state);
 466
 467         return 0;
 468 }
 469
 470 static struct drm_encoder *vc4_crtc_get_encoder_by_type(struct drm_crtc *crtc,
 471                                                         enum vc4_encoder_type type)
 472 {
 473         struct drm_encoder *encoder;
 474
 475         drm_for_each_encoder(encoder, crtc->dev) {
 476                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 477
 478                 if (vc4_encoder->type == type)
 479                         return encoder;
 480         }
 481
 482         return NULL;
 483 }
 484
 485 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
 486 {
 487         struct drm_device *drm = crtc->dev;
 488         struct vc4_dev *vc4 = to_vc4_dev(drm);
 489         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 490         enum vc4_encoder_type encoder_type;
 491         const struct vc4_pv_data *pv_data;
 492         struct drm_encoder *encoder;
 493         struct vc4_hdmi *vc4_hdmi;
 494         unsigned encoder_sel;
 495         int channel;
 496         int ret;
 497
 498         if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 499                                       "brcm,bcm2711-pixelvalve2") ||
 500               of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
 501                                       "brcm,bcm2711-pixelvalve4")))
 502                 return 0;
 503
 504         if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
 505                 return 0;
 506
 507         if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
 508                 return 0;
 509
 510         channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
 511         if (channel < 0)
 512                 return 0;
 513
 514         encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
 515         if (WARN_ON(encoder_sel != 0))
 516                 return 0;
 517
 518         pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
 519         encoder_type = pv_data->encoder_types[encoder_sel];
 520         encoder = vc4_crtc_get_encoder_by_type(crtc, encoder_type);
 521         if (WARN_ON(!encoder))
 522                 return 0;
 523
 524         vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 525         ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
 526         if (ret)
 527                 return ret;
 528
 529         ret = vc4_crtc_disable(crtc, encoder, NULL, channel);
 530         if (ret)
 531                 return ret;
 532
 533         /*
 534          * post_crtc_powerdown will have called pm_runtime_put, so we
 535          * don't need it here otherwise we'll get the reference counting
 536          * wrong.
 537          */
 538
 539         return 0;
 540 }
 541
 542 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
 543                                     struct drm_atomic_state *state)
 544 {
 545         struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
 546                                                                          crtc);
 547         struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
 548         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);
 549         struct drm_device *dev = crtc->dev;
 550
 551         drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)",
 552                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 553
 554         require_hvs_enabled(dev);
 555
 556         /* Disable vblank irq handling before crtc is disabled. */
 557         drm_crtc_vblank_off(crtc);
 558
 559         vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
 560
 561         /*
 562          * Make sure we issue a vblank event after disabling the CRTC if
 563          * someone was waiting it.
 564          */
 565         if (crtc->state->event) {
 566                 unsigned long flags;
 567
 568                 spin_lock_irqsave(&dev->event_lock, flags);
 569                 drm_crtc_send_vblank_event(crtc, crtc->state->event);
 570                 crtc->state->event = NULL;
 571                 spin_unlock_irqrestore(&dev->event_lock, flags);
 572         }
 573 }
 574
 575 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
 576                                    struct drm_atomic_state *state)
 577 {
 578         struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,
 579                                                                          crtc);
 580         struct drm_device *dev = crtc->dev;
 581         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 582         struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);
 583         struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 584
 585         drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)",
 586                 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
 587
 588         require_hvs_enabled(dev);
 589
 590         /* Enable vblank irq handling before crtc is started otherwise
 591          * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
 592          */
 593         drm_crtc_vblank_on(crtc);
 594
 595         vc4_hvs_atomic_enable(crtc, state);
 596
 597         if (vc4_encoder->pre_crtc_configure)
 598                 vc4_encoder->pre_crtc_configure(encoder, state);
 599
 600         vc4_crtc_config_pv(crtc, encoder, state);
 601
 602         CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
 603
 604         if (vc4_encoder->pre_crtc_enable)
 605                 vc4_encoder->pre_crtc_enable(encoder, state);
 606
 607         /* When feeding the transposer block the pixelvalve is unneeded and
 608          * should not be enabled.
 609          */
 610         CRTC_WRITE(PV_V_CONTROL,
 611                    CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
 612
 613         if (vc4_encoder->post_crtc_enable)
 614                 vc4_encoder->post_crtc_enable(encoder, state);
 615 }
 616
 617 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
 618                                                 const struct drm_display_mode *mode)
 619 {
 620         /* Do not allow doublescan modes from user space */
 621         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 622                 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
 623                               crtc->base.id);
 624                 return MODE_NO_DBLESCAN;
 625         }
 626
 627         return MODE_OK;
 628 }
 629
 630 void vc4_crtc_get_margins(struct drm_crtc_state *state,
 631                           unsigned int *left, unsigned int *right,
 632                           unsigned int *top, unsigned int *bottom)
 633 {
 634         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
 635         struct drm_connector_state *conn_state;
 636         struct drm_connector *conn;
 637         int i;
 638
 639         *left = vc4_state->margins.left;
 640         *right = vc4_state->margins.right;
 641         *top = vc4_state->margins.top;
 642         *bottom = vc4_state->margins.bottom;
 643
 644         /* We have to interate over all new connector states because
 645          * vc4_crtc_get_margins() might be called before
 646          * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
 647          * might be outdated.
 648          */
 649         for_each_new_connector_in_state(state->state, conn, conn_state, i) {
 650                 if (conn_state->crtc != state->crtc)
 651                         continue;
 652
 653                 *left = conn_state->tv.margins.left;
 654                 *right = conn_state->tv.margins.right;
 655                 *top = conn_state->tv.margins.top;
 656                 *bottom = conn_state->tv.margins.bottom;
 657                 break;
 658         }
 659 }
 660
 661 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
 662                                  struct drm_atomic_state *state)
 663 {
 664         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 665                                                                           crtc);
 666         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
 667         struct drm_connector *conn;
 668         struct drm_connector_state *conn_state;
 669         struct drm_encoder *encoder;
 670         int ret, i;
 671
 672         ret = vc4_hvs_atomic_check(crtc, state);
 673         if (ret)
 674                 return ret;
 675
 676         encoder = vc4_get_crtc_encoder(crtc, crtc_state);
 677         if (encoder) {
 678                 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 679                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
 680
 681                 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
 682                         vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 1000,
 683                                                   mode->clock * 9 / 10) * 1000;
 684                 } else {
 685                         vc4_state->hvs_load = mode->clock * 1000;
 686                 }
 687         }
 688
 689         for_each_new_connector_in_state(state, conn, conn_state,
 690                                         i) {
 691                 if (conn_state->crtc != crtc)
 692                         continue;
 693
 694                 vc4_state->margins.left = conn_state->tv.margins.left;
 695                 vc4_state->margins.right = conn_state->tv.margins.right;
 696                 vc4_state->margins.top = conn_state->tv.margins.top;
 697                 vc4_state->margins.bottom = conn_state->tv.margins.bottom;
 698                 break;
 699         }
 700
 701         return 0;
 702 }
 703
 704 static int vc4_enable_vblank(struct drm_crtc *crtc)
 705 {
 706         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 707
 708         CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
 709
 710         return 0;
 711 }
 712
 713 static void vc4_disable_vblank(struct drm_crtc *crtc)
 714 {
 715         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
 716
 717         CRTC_WRITE(PV_INTEN, 0);
 718 }
 719
 720 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
 721 {
 722         struct drm_crtc *crtc = &vc4_crtc->base;
 723         struct drm_device *dev = crtc->dev;
 724         struct vc4_dev *vc4 = to_vc4_dev(dev);
 725         struct vc4_hvs *hvs = vc4->hvs;
 726         u32 chan = vc4_crtc->current_hvs_channel;
 727         unsigned long flags;
 728
 729         spin_lock_irqsave(&dev->event_lock, flags);
 730         spin_lock(&vc4_crtc->irq_lock);
 731         if (vc4_crtc->event &&
 732             (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) ||
 733              vc4_crtc->feeds_txp)) {
 734                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 735                 vc4_crtc->event = NULL;
 736                 drm_crtc_vblank_put(crtc);
 737
 738                 /* Wait for the page flip to unmask the underrun to ensure that
 739                  * the display list was updated by the hardware. Before that
 740                  * happens, the HVS will be using the previous display list with
 741                  * the CRTC and encoder already reconfigured, leading to
 742                  * underruns. This can be seen when reconfiguring the CRTC.
 743                  */
 744                 vc4_hvs_unmask_underrun(hvs, chan);
 745         }
 746         spin_unlock(&vc4_crtc->irq_lock);
 747         spin_unlock_irqrestore(&dev->event_lock, flags);
 748 }
 749
 750 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
 751 {
 752         crtc->t_vblank = ktime_get();
 753         drm_crtc_handle_vblank(&crtc->base);
 754         vc4_crtc_handle_page_flip(crtc);
 755 }
 756
 757 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
 758 {
 759         struct vc4_crtc *vc4_crtc = data;
 760         u32 stat = CRTC_READ(PV_INTSTAT);
 761         irqreturn_t ret = IRQ_NONE;
 762
 763         if (stat & PV_INT_VFP_START) {
 764                 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
 765                 vc4_crtc_handle_vblank(vc4_crtc);
 766                 ret = IRQ_HANDLED;
 767         }
 768
 769         return ret;
 770 }
 771
 772 struct vc4_async_flip_state {
 773         struct drm_crtc *crtc;
 774         struct drm_framebuffer *fb;
 775         struct drm_framebuffer *old_fb;
 776         struct drm_pending_vblank_event *event;
 777
 778         union {
 779                 struct dma_fence_cb fence;
 780                 struct vc4_seqno_cb seqno;
 781         } cb;
 782 };
 783
 784 /* Called when the V3D execution for the BO being flipped to is done, so that
 785  * we can actually update the plane's address to point to it.
 786  */
 787 static void
 788 vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
 789 {
 790         struct drm_crtc *crtc = flip_state->crtc;
 791         struct drm_device *dev = crtc->dev;
 792         struct drm_plane *plane = crtc->primary;
 793
 794         vc4_plane_async_set_fb(plane, flip_state->fb);
 795         if (flip_state->event) {
 796                 unsigned long flags;
 797
 798                 spin_lock_irqsave(&dev->event_lock, flags);
 799                 drm_crtc_send_vblank_event(crtc, flip_state->event);
 800                 spin_unlock_irqrestore(&dev->event_lock, flags);
 801         }
 802
 803         drm_crtc_vblank_put(crtc);
 804         drm_framebuffer_put(flip_state->fb);
 805
 806         if (flip_state->old_fb)
 807                 drm_framebuffer_put(flip_state->old_fb);
 808
 809         kfree(flip_state);
 810 }
 811
 812 static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
 813 {
 814         struct vc4_async_flip_state *flip_state =
 815                 container_of(cb, struct vc4_async_flip_state, cb.seqno);
 816         struct vc4_bo *bo = NULL;
 817
 818         if (flip_state->old_fb) {
 819                 struct drm_gem_cma_object *cma_bo =
 820                         drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
 821                 bo = to_vc4_bo(&cma_bo->base);
 822         }
 823
 824         vc4_async_page_flip_complete(flip_state);
 825
 826         /*
 827          * Decrement the BO usecnt in order to keep the inc/dec
 828          * calls balanced when the planes are updated through
 829          * the async update path.
 830          *
 831          * FIXME: we should move to generic async-page-flip when
 832          * it's available, so that we can get rid of this
 833          * hand-made cleanup_fb() logic.
 834          */
 835         if (bo)
 836                 vc4_bo_dec_usecnt(bo);
 837 }
 838
 839 static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
 840                                                struct dma_fence_cb *cb)
 841 {
 842         struct vc4_async_flip_state *flip_state =
 843                 container_of(cb, struct vc4_async_flip_state, cb.fence);
 844
 845         vc4_async_page_flip_complete(flip_state);
 846         dma_fence_put(fence);
 847 }
 848
 849 static int vc4_async_set_fence_cb(struct drm_device *dev,
 850                                   struct vc4_async_flip_state *flip_state)
 851 {
 852         struct drm_framebuffer *fb = flip_state->fb;
 853         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 854         struct vc4_dev *vc4 = to_vc4_dev(dev);
 855         struct dma_fence *fence;
 856         int ret;
 857
 858         if (!vc4->is_vc5) {
 859                 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 860
 861                 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
 862                                           vc4_async_page_flip_seqno_complete);
 863         }
 864
 865         ret = dma_resv_get_singleton(cma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
 866         if (ret)
 867                 return ret;
 868
 869         /* If there's no fence, complete the page flip immediately */
 870         if (!fence) {
 871                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 872                 return 0;
 873         }
 874
 875         /* If the fence has already been completed, complete the page flip */
 876         if (dma_fence_add_callback(fence, &flip_state->cb.fence,
 877                                    vc4_async_page_flip_fence_complete))
 878                 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
 879
 880         return 0;
 881 }
 882
 883 static int
 884 vc4_async_page_flip_common(struct drm_crtc *crtc,
 885                            struct drm_framebuffer *fb,
 886                            struct drm_pending_vblank_event *event,
 887                            uint32_t flags)
 888 {
 889         struct drm_device *dev = crtc->dev;
 890         struct drm_plane *plane = crtc->primary;
 891         struct vc4_async_flip_state *flip_state;
 892
 893         flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
 894         if (!flip_state)
 895                 return -ENOMEM;
 896
 897         drm_framebuffer_get(fb);
 898         flip_state->fb = fb;
 899         flip_state->crtc = crtc;
 900         flip_state->event = event;
 901
 902         /* Save the current FB before it's replaced by the new one in
 903          * drm_atomic_set_fb_for_plane(). We'll need the old FB in
 904          * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
 905          * it consistent.
 906          * FIXME: we should move to generic async-page-flip when it's
 907          * available, so that we can get rid of this hand-made cleanup_fb()
 908          * logic.
 909          */
 910         flip_state->old_fb = plane->state->fb;
 911         if (flip_state->old_fb)
 912                 drm_framebuffer_get(flip_state->old_fb);
 913
 914         WARN_ON(drm_crtc_vblank_get(crtc) != 0);
 915
 916         /* Immediately update the plane's legacy fb pointer, so that later
 917          * modeset prep sees the state that will be present when the semaphore
 918          * is released.
 919          */
 920         drm_atomic_set_fb_for_plane(plane->state, fb);
 921
 922         vc4_async_set_fence_cb(dev, flip_state);
 923
 924         /* Driver takes ownership of state on successful async commit. */
 925         return 0;
 926 }
 927
 928 /* Implements async (non-vblank-synced) page flips.
 929  *
 930  * The page flip ioctl needs to return immediately, so we grab the
 931  * modeset semaphore on the pipe, and queue the address update for
 932  * when V3D is done with the BO being flipped to.
 933  */
 934 static int vc4_async_page_flip(struct drm_crtc *crtc,
 935                                struct drm_framebuffer *fb,
 936                                struct drm_pending_vblank_event *event,
 937                                uint32_t flags)
 938 {
 939         struct drm_device *dev = crtc->dev;
 940         struct vc4_dev *vc4 = to_vc4_dev(dev);
 941         struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
 942         struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
 943         int ret;
 944
 945         if (WARN_ON_ONCE(vc4->is_vc5))
 946                 return -ENODEV;
 947
 948         /*
 949          * Increment the BO usecnt here, so that we never end up with an
 950          * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
 951          * plane is later updated through the non-async path.
 952          *
 953          * FIXME: we should move to generic async-page-flip when
 954          * it's available, so that we can get rid of this
 955          * hand-made prepare_fb() logic.
 956          */
 957         ret = vc4_bo_inc_usecnt(bo);
 958         if (ret)
 959                 return ret;
 960
 961         ret = vc4_async_page_flip_common(crtc, fb, event, flags);
 962         if (ret) {
 963                 vc4_bo_dec_usecnt(bo);
 964                 return ret;
 965         }
 966
 967         return 0;
 968 }
 969
 970 static int vc5_async_page_flip(struct drm_crtc *crtc,
 971                                struct drm_framebuffer *fb,
 972                                struct drm_pending_vblank_event *event,
 973                                uint32_t flags)
 974 {
 975         return vc4_async_page_flip_common(crtc, fb, event, flags);
 976 }
 977
 978 int vc4_page_flip(struct drm_crtc *crtc,
 979                   struct drm_framebuffer *fb,
 980                   struct drm_pending_vblank_event *event,
 981                   uint32_t flags,
 982                   struct drm_modeset_acquire_ctx *ctx)
 983 {
 984         if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
 985                 struct drm_device *dev = crtc->dev;
 986                 struct vc4_dev *vc4 = to_vc4_dev(dev);
 987
 988                 if (vc4->is_vc5)
 989                         return vc5_async_page_flip(crtc, fb, event, flags);
 990                 else
 991                         return vc4_async_page_flip(crtc, fb, event, flags);
 992         } else {
 993                 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
 994         }
 995 }
 996
 997 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
 998 {
 999         struct vc4_crtc_state *vc4_state, *old_vc4_state;
1000
1001         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1002         if (!vc4_state)
1003                 return NULL;
1004
1005         old_vc4_state = to_vc4_crtc_state(crtc->state);
1006         vc4_state->margins = old_vc4_state->margins;
1007         vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1008
1009         __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1010         return &vc4_state->base;
1011 }
1012
1013 void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1014                             struct drm_crtc_state *state)
1015 {
1016         struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1017         struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1018
1019         if (drm_mm_node_allocated(&vc4_state->mm)) {
1020                 unsigned long flags;
1021
1022                 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1023                 drm_mm_remove_node(&vc4_state->mm);
1024                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1025
1026         }
1027
1028         drm_atomic_helper_crtc_destroy_state(crtc, state);
1029 }
1030
1031 void vc4_crtc_reset(struct drm_crtc *crtc)
1032 {
1033         struct vc4_crtc_state *vc4_crtc_state;
1034
1035         if (crtc->state)
1036                 vc4_crtc_destroy_state(crtc, crtc->state);
1037
1038         vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
1039         if (!vc4_crtc_state) {
1040                 crtc->state = NULL;
1041                 return;
1042         }
1043
1044         vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
1045         __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
1046 }
1047
1048 static const struct drm_crtc_funcs vc4_crtc_funcs = {
1049         .set_config = drm_atomic_helper_set_config,
1050         .destroy = vc4_crtc_destroy,
1051         .page_flip = vc4_page_flip,
1052         .set_property = NULL,
1053         .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1054         .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1055         .reset = vc4_crtc_reset,
1056         .atomic_duplicate_state = vc4_crtc_duplicate_state,
1057         .atomic_destroy_state = vc4_crtc_destroy_state,
1058         .enable_vblank = vc4_enable_vblank,
1059         .disable_vblank = vc4_disable_vblank,
1060         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1061 };
1062
1063 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1064         .mode_valid = vc4_crtc_mode_valid,
1065         .atomic_check = vc4_crtc_atomic_check,
1066         .atomic_begin = vc4_hvs_atomic_begin,
1067         .atomic_flush = vc4_hvs_atomic_flush,
1068         .atomic_enable = vc4_crtc_atomic_enable,
1069         .atomic_disable = vc4_crtc_atomic_disable,
1070         .get_scanout_position = vc4_crtc_get_scanout_position,
1071 };
1072
1073 static const struct vc4_pv_data bcm2835_pv0_data = {
1074         .base = {
1075                 .hvs_available_channels = BIT(0),
1076                 .hvs_output = 0,
1077         },
1078         .debugfs_name = "crtc0_regs",
1079         .fifo_depth = 64,
1080         .pixels_per_clock = 1,
1081         .encoder_types = {
1082                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1083                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1084         },
1085 };
1086
1087 static const struct vc4_pv_data bcm2835_pv1_data = {
1088         .base = {
1089                 .hvs_available_channels = BIT(2),
1090                 .hvs_output = 2,
1091         },
1092         .debugfs_name = "crtc1_regs",
1093         .fifo_depth = 64,
1094         .pixels_per_clock = 1,
1095         .encoder_types = {
1096                 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1097                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1098         },
1099 };
1100
1101 static const struct vc4_pv_data bcm2835_pv2_data = {
1102         .base = {
1103                 .hvs_available_channels = BIT(1),
1104                 .hvs_output = 1,
1105         },
1106         .debugfs_name = "crtc2_regs",
1107         .fifo_depth = 64,
1108         .pixels_per_clock = 1,
1109         .encoder_types = {
1110                 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
1111                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1112         },
1113 };
1114
1115 static const struct vc4_pv_data bcm2711_pv0_data = {
1116         .base = {
1117                 .hvs_available_channels = BIT(0),
1118                 .hvs_output = 0,
1119         },
1120         .debugfs_name = "crtc0_regs",
1121         .fifo_depth = 64,
1122         .pixels_per_clock = 1,
1123         .encoder_types = {
1124                 [0] = VC4_ENCODER_TYPE_DSI0,
1125                 [1] = VC4_ENCODER_TYPE_DPI,
1126         },
1127 };
1128
1129 static const struct vc4_pv_data bcm2711_pv1_data = {
1130         .base = {
1131                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1132                 .hvs_output = 3,
1133         },
1134         .debugfs_name = "crtc1_regs",
1135         .fifo_depth = 64,
1136         .pixels_per_clock = 1,
1137         .encoder_types = {
1138                 [0] = VC4_ENCODER_TYPE_DSI1,
1139                 [1] = VC4_ENCODER_TYPE_SMI,
1140         },
1141 };
1142
1143 static const struct vc4_pv_data bcm2711_pv2_data = {
1144         .base = {
1145                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1146                 .hvs_output = 4,
1147         },
1148         .debugfs_name = "crtc2_regs",
1149         .fifo_depth = 256,
1150         .pixels_per_clock = 2,
1151         .encoder_types = {
1152                 [0] = VC4_ENCODER_TYPE_HDMI0,
1153         },
1154 };
1155
1156 static const struct vc4_pv_data bcm2711_pv3_data = {
1157         .base = {
1158                 .hvs_available_channels = BIT(1),
1159                 .hvs_output = 1,
1160         },
1161         .debugfs_name = "crtc3_regs",
1162         .fifo_depth = 64,
1163         .pixels_per_clock = 1,
1164         .encoder_types = {
1165                 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1166         },
1167 };
1168
1169 static const struct vc4_pv_data bcm2711_pv4_data = {
1170         .base = {
1171                 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1172                 .hvs_output = 5,
1173         },
1174         .debugfs_name = "crtc4_regs",
1175         .fifo_depth = 64,
1176         .pixels_per_clock = 2,
1177         .encoder_types = {
1178                 [0] = VC4_ENCODER_TYPE_HDMI1,
1179         },
1180 };
1181
1182 static const struct of_device_id vc4_crtc_dt_match[] = {
1183         { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1184         { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1185         { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1186         { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1187         { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1188         { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1189         { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1190         { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1191         {}
1192 };
1193
1194 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1195                                         struct drm_crtc *crtc)
1196 {
1197         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1198         const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1199         const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1200         struct drm_encoder *encoder;
1201
1202         drm_for_each_encoder(encoder, drm) {
1203                 struct vc4_encoder *vc4_encoder;
1204                 int i;
1205
1206                 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1207                         continue;
1208
1209                 vc4_encoder = to_vc4_encoder(encoder);
1210                 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1211                         if (vc4_encoder->type == encoder_types[i]) {
1212                                 vc4_encoder->clock_select = i;
1213                                 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1214                                 break;
1215                         }
1216                 }
1217         }
1218 }
1219
1220 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc,
1221                   const struct drm_crtc_funcs *crtc_funcs,
1222                   const struct drm_crtc_helper_funcs *crtc_helper_funcs)
1223 {
1224         struct vc4_dev *vc4 = to_vc4_dev(drm);
1225         struct drm_crtc *crtc = &vc4_crtc->base;
1226         struct drm_plane *primary_plane;
1227         unsigned int i;
1228
1229         /* For now, we create just the primary and the legacy cursor
1230          * planes.  We should be able to stack more planes on easily,
1231          * but to do that we would need to compute the bandwidth
1232          * requirement of the plane configuration, and reject ones
1233          * that will take too much.
1234          */
1235         primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1236         if (IS_ERR(primary_plane)) {
1237                 dev_err(drm->dev, "failed to construct primary plane\n");
1238                 return PTR_ERR(primary_plane);
1239         }
1240
1241         spin_lock_init(&vc4_crtc->irq_lock);
1242         drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1243                                   crtc_funcs, NULL);
1244         drm_crtc_helper_add(crtc, crtc_helper_funcs);
1245
1246         if (!vc4->is_vc5) {
1247                 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1248
1249                 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1250
1251                 /* We support CTM, but only for one CRTC at a time. It's therefore
1252                  * implemented as private driver state in vc4_kms, not here.
1253                  */
1254                 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1255         }
1256
1257         for (i = 0; i < crtc->gamma_size; i++) {
1258                 vc4_crtc->lut_r[i] = i;
1259                 vc4_crtc->lut_g[i] = i;
1260                 vc4_crtc->lut_b[i] = i;
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1267 {
1268         struct platform_device *pdev = to_platform_device(dev);
1269         struct drm_device *drm = dev_get_drvdata(master);
1270         const struct vc4_pv_data *pv_data;
1271         struct vc4_crtc *vc4_crtc;
1272         struct drm_crtc *crtc;
1273         struct drm_plane *destroy_plane, *temp;
1274         int ret;
1275
1276         vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1277         if (!vc4_crtc)
1278                 return -ENOMEM;
1279         crtc = &vc4_crtc->base;
1280
1281         pv_data = of_device_get_match_data(dev);
1282         if (!pv_data)
1283                 return -ENODEV;
1284         vc4_crtc->data = &pv_data->base;
1285         vc4_crtc->pdev = pdev;
1286
1287         vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1288         if (IS_ERR(vc4_crtc->regs))
1289                 return PTR_ERR(vc4_crtc->regs);
1290
1291         vc4_crtc->regset.base = vc4_crtc->regs;
1292         vc4_crtc->regset.regs = crtc_regs;
1293         vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1294
1295         ret = vc4_crtc_init(drm, vc4_crtc,
1296                             &vc4_crtc_funcs, &vc4_crtc_helper_funcs);
1297         if (ret)
1298                 return ret;
1299         vc4_set_crtc_possible_masks(drm, crtc);
1300
1301         CRTC_WRITE(PV_INTEN, 0);
1302         CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1303         ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1304                                vc4_crtc_irq_handler,
1305                                IRQF_SHARED,
1306                                "vc4 crtc", vc4_crtc);
1307         if (ret)
1308                 goto err_destroy_planes;
1309
1310         platform_set_drvdata(pdev, vc4_crtc);
1311
1312         vc4_debugfs_add_regset32(drm, pv_data->debugfs_name,
1313                                  &vc4_crtc->regset);
1314
1315         return 0;
1316
1317 err_destroy_planes:
1318         list_for_each_entry_safe(destroy_plane, temp,
1319                                  &drm->mode_config.plane_list, head) {
1320                 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc))
1321                     destroy_plane->funcs->destroy(destroy_plane);
1322         }
1323
1324         return ret;
1325 }
1326
1327 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1328                             void *data)
1329 {
1330         struct platform_device *pdev = to_platform_device(dev);
1331         struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1332
1333         vc4_crtc_destroy(&vc4_crtc->base);
1334
1335         CRTC_WRITE(PV_INTEN, 0);
1336
1337         platform_set_drvdata(pdev, NULL);
1338 }
1339
1340 static const struct component_ops vc4_crtc_ops = {
1341         .bind   = vc4_crtc_bind,
1342         .unbind = vc4_crtc_unbind,
1343 };
1344
1345 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1346 {
1347         return component_add(&pdev->dev, &vc4_crtc_ops);
1348 }
1349
1350 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1351 {
1352         component_del(&pdev->dev, &vc4_crtc_ops);
1353         return 0;
1354 }
1355
1356 struct platform_driver vc4_crtc_driver = {
1357         .probe = vc4_crtc_dev_probe,
1358         .remove = vc4_crtc_dev_remove,
1359         .driver = {
1360                 .name = "vc4_crtc",
1361                 .of_match_table = vc4_crtc_dt_match,
1362         },
1363 };