arch/mips/kernel/smp-cps.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2013 Imagination Technologies
   4  * Author: Paul Burton <[email protected]>
   5  */
   6
   7 #include <linux/cpu.h>
   8 #include <linux/delay.h>
   9 #include <linux/io.h>
  10 #include <linux/sched/task_stack.h>
  11 #include <linux/sched/hotplug.h>
  12 #include <linux/slab.h>
  13 #include <linux/smp.h>
  14 #include <linux/types.h>
  15 #include <linux/irq.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/mips-cps.h>
  19 #include <asm/mips_mt.h>
  20 #include <asm/mipsregs.h>
  21 #include <asm/pm-cps.h>
  22 #include <asm/r4kcache.h>
  23 #include <asm/smp.h>
  24 #include <asm/smp-cps.h>
  25 #include <asm/time.h>
  26 #include <asm/uasm.h>
  27
  28 static bool threads_disabled;
  29 static DECLARE_BITMAP(core_power, NR_CPUS);
  30
  31 struct core_boot_config *mips_cps_core_bootcfg;
  32
  33 static int __init setup_nothreads(char *s)
  34 {
  35         threads_disabled = true;
  36         return 0;
  37 }
  38 early_param("nothreads", setup_nothreads);
  39
  40 static unsigned core_vpe_count(unsigned int cluster, unsigned core)
  41 {
  42         if (threads_disabled)
  43                 return 1;
  44
  45         return mips_cps_numvps(cluster, core);
  46 }
  47
  48 static void __init cps_smp_setup(void)
  49 {
  50         unsigned int nclusters, ncores, nvpes, core_vpes;
  51         unsigned long core_entry;
  52         int cl, c, v;
  53
  54         /* Detect & record VPE topology */
  55         nvpes = 0;
  56         nclusters = mips_cps_numclusters();
  57         pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
  58         for (cl = 0; cl < nclusters; cl++) {
  59                 if (cl > 0)
  60                         pr_cont(",");
  61                 pr_cont("{");
  62
  63                 ncores = mips_cps_numcores(cl);
  64                 for (c = 0; c < ncores; c++) {
  65                         core_vpes = core_vpe_count(cl, c);
  66
  67                         if (c > 0)
  68                                 pr_cont(",");
  69                         pr_cont("%u", core_vpes);
  70
  71                         /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
  72                         if (!cl && !c)
  73                                 smp_num_siblings = core_vpes;
  74
  75                         for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
  76                                 cpu_set_cluster(&cpu_data[nvpes + v], cl);
  77                                 cpu_set_core(&cpu_data[nvpes + v], c);
  78                                 cpu_set_vpe_id(&cpu_data[nvpes + v], v);
  79                         }
  80
  81                         nvpes += core_vpes;
  82                 }
  83
  84                 pr_cont("}");
  85         }
  86         pr_cont(" total %u\n", nvpes);
  87
  88         /* Indicate present CPUs (CPU being synonymous with VPE) */
  89         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
  90                 set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
  91                 set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
  92                 __cpu_number_map[v] = v;
  93                 __cpu_logical_map[v] = v;
  94         }
  95
  96         /* Set a coherent default CCA (CWB) */
  97         change_c0_config(CONF_CM_CMASK, 0x5);
  98
  99         /* Core 0 is powered up (we're running on it) */
 100         bitmap_set(core_power, 0, 1);
 101
 102         /* Initialise core 0 */
 103         mips_cps_core_init();
 104
 105         /* Make core 0 coherent with everything */
 106         write_gcr_cl_coherence(0xff);
 107
 108         if (mips_cm_revision() >= CM_REV_CM3) {
 109                 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
 110                 write_gcr_bev_base(core_entry);
 111         }
 112
 113 #ifdef CONFIG_MIPS_MT_FPAFF
 114         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 115         if (cpu_has_fpu)
 116                 cpumask_set_cpu(0, &mt_fpu_cpumask);
 117 #endif /* CONFIG_MIPS_MT_FPAFF */
 118 }
 119
 120 static void __init cps_prepare_cpus(unsigned int max_cpus)
 121 {
 122         unsigned ncores, core_vpes, c, cca;
 123         bool cca_unsuitable, cores_limited;
 124         u32 *entry_code;
 125
 126         mips_mt_set_cpuoptions();
 127
 128         /* Detect whether the CCA is unsuited to multi-core SMP */
 129         cca = read_c0_config() & CONF_CM_CMASK;
 130         switch (cca) {
 131         case 0x4: /* CWBE */
 132         case 0x5: /* CWB */
 133                 /* The CCA is coherent, multi-core is fine */
 134                 cca_unsuitable = false;
 135                 break;
 136
 137         default:
 138                 /* CCA is not coherent, multi-core is not usable */
 139                 cca_unsuitable = true;
 140         }
 141
 142         /* Warn the user if the CCA prevents multi-core */
 143         cores_limited = false;
 144         if (cca_unsuitable || cpu_has_dc_aliases) {
 145                 for_each_present_cpu(c) {
 146                         if (cpus_are_siblings(smp_processor_id(), c))
 147                                 continue;
 148
 149                         set_cpu_present(c, false);
 150                         cores_limited = true;
 151                 }
 152         }
 153         if (cores_limited)
 154                 pr_warn("Using only one core due to %s%s%s\n",
 155                         cca_unsuitable ? "unsuitable CCA" : "",
 156                         (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
 157                         cpu_has_dc_aliases ? "dcache aliasing" : "");
 158
 159         /*
 160          * Patch the start of mips_cps_core_entry to provide:
 161          *
 162          * s0 = kseg0 CCA
 163          */
 164         entry_code = (u32 *)&mips_cps_core_entry;
 165         uasm_i_addiu(&entry_code, 16, 0, cca);
 166         UASM_i_LA(&entry_code, 17, (long)mips_gcr_base);
 167         BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end);
 168         blast_dcache_range((unsigned long)&mips_cps_core_entry,
 169                            (unsigned long)entry_code);
 170         bc_wback_inv((unsigned long)&mips_cps_core_entry,
 171                      (void *)entry_code - (void *)&mips_cps_core_entry);
 172         __sync();
 173
 174         /* Allocate core boot configuration structs */
 175         ncores = mips_cps_numcores(0);
 176         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
 177                                         GFP_KERNEL);
 178         if (!mips_cps_core_bootcfg) {
 179                 pr_err("Failed to allocate boot config for %u cores\n", ncores);
 180                 goto err_out;
 181         }
 182
 183         /* Allocate VPE boot configuration structs */
 184         for (c = 0; c < ncores; c++) {
 185                 core_vpes = core_vpe_count(0, c);
 186                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
 187                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
 188                                 GFP_KERNEL);
 189                 if (!mips_cps_core_bootcfg[c].vpe_config) {
 190                         pr_err("Failed to allocate %u VPE boot configs\n",
 191                                core_vpes);
 192                         goto err_out;
 193                 }
 194         }
 195
 196         /* Mark this CPU as booted */
 197         atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask,
 198                    1 << cpu_vpe_id(&current_cpu_data));
 199
 200         return;
 201 err_out:
 202         /* Clean up allocations */
 203         if (mips_cps_core_bootcfg) {
 204                 for (c = 0; c < ncores; c++)
 205                         kfree(mips_cps_core_bootcfg[c].vpe_config);
 206                 kfree(mips_cps_core_bootcfg);
 207                 mips_cps_core_bootcfg = NULL;
 208         }
 209
 210         /* Effectively disable SMP by declaring CPUs not present */
 211         for_each_possible_cpu(c) {
 212                 if (c == 0)
 213                         continue;
 214                 set_cpu_present(c, false);
 215         }
 216 }
 217
 218 static void boot_core(unsigned int core, unsigned int vpe_id)
 219 {
 220         u32 stat, seq_state;
 221         unsigned timeout;
 222
 223         /* Select the appropriate core */
 224         mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 225
 226         /* Set its reset vector */
 227         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
 228
 229         /* Ensure its coherency is disabled */
 230         write_gcr_co_coherence(0);
 231
 232         /* Start it with the legacy memory map and exception base */
 233         write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
 234
 235         /* Ensure the core can access the GCRs */
 236         set_gcr_access(1 << core);
 237
 238         if (mips_cpc_present()) {
 239                 /* Reset the core */
 240                 mips_cpc_lock_other(core);
 241
 242                 if (mips_cm_revision() >= CM_REV_CM3) {
 243                         /* Run only the requested VP following the reset */
 244                         write_cpc_co_vp_stop(0xf);
 245                         write_cpc_co_vp_run(1 << vpe_id);
 246
 247                         /*
 248                          * Ensure that the VP_RUN register is written before the
 249                          * core leaves reset.
 250                          */
 251                         wmb();
 252                 }
 253
 254                 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
 255
 256                 timeout = 100;
 257                 while (true) {
 258                         stat = read_cpc_co_stat_conf();
 259                         seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
 260                         seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
 261
 262                         /* U6 == coherent execution, ie. the core is up */
 263                         if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
 264                                 break;
 265
 266                         /* Delay a little while before we start warning */
 267                         if (timeout) {
 268                                 timeout--;
 269                                 mdelay(10);
 270                                 continue;
 271                         }
 272
 273                         pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
 274                                 core, stat);
 275                         mdelay(1000);
 276                 }
 277
 278                 mips_cpc_unlock_other();
 279         } else {
 280                 /* Take the core out of reset */
 281                 write_gcr_co_reset_release(0);
 282         }
 283
 284         mips_cm_unlock_other();
 285
 286         /* The core is now powered up */
 287         bitmap_set(core_power, core, 1);
 288 }
 289
 290 static void remote_vpe_boot(void *dummy)
 291 {
 292         unsigned core = cpu_core(&current_cpu_data);
 293         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 294
 295         mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
 296 }
 297
 298 static int cps_boot_secondary(int cpu, struct task_struct *idle)
 299 {
 300         unsigned core = cpu_core(&cpu_data[cpu]);
 301         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 302         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 303         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
 304         unsigned long core_entry;
 305         unsigned int remote;
 306         int err;
 307
 308         /* We don't yet support booting CPUs in other clusters */
 309         if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
 310                 return -ENOSYS;
 311
 312         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
 313         vpe_cfg->sp = __KSTK_TOS(idle);
 314         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
 315
 316         atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
 317
 318         preempt_disable();
 319
 320         if (!test_bit(core, core_power)) {
 321                 /* Boot a VPE on a powered down core */
 322                 boot_core(core, vpe_id);
 323                 goto out;
 324         }
 325
 326         if (cpu_has_vp) {
 327                 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 328                 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
 329                 write_gcr_co_reset_base(core_entry);
 330                 mips_cm_unlock_other();
 331         }
 332
 333         if (!cpus_are_siblings(cpu, smp_processor_id())) {
 334                 /* Boot a VPE on another powered up core */
 335                 for (remote = 0; remote < NR_CPUS; remote++) {
 336                         if (!cpus_are_siblings(cpu, remote))
 337                                 continue;
 338                         if (cpu_online(remote))
 339                                 break;
 340                 }
 341                 if (remote >= NR_CPUS) {
 342                         pr_crit("No online CPU in core %u to start CPU%d\n",
 343                                 core, cpu);
 344                         goto out;
 345                 }
 346
 347                 err = smp_call_function_single(remote, remote_vpe_boot,
 348                                                NULL, 1);
 349                 if (err)
 350                         panic("Failed to call remote CPU\n");
 351                 goto out;
 352         }
 353
 354         BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
 355
 356         /* Boot a VPE on this core */
 357         mips_cps_boot_vpes(core_cfg, vpe_id);
 358 out:
 359         preempt_enable();
 360         return 0;
 361 }
 362
 363 static void cps_init_secondary(void)
 364 {
 365         int core = cpu_core(&current_cpu_data);
 366
 367         /* Disable MT - we only want to run 1 TC per VPE */
 368         if (cpu_has_mipsmt)
 369                 dmt();
 370
 371         if (mips_cm_revision() >= CM_REV_CM3) {
 372                 unsigned int ident = read_gic_vl_ident();
 373
 374                 /*
 375                  * Ensure that our calculation of the VP ID matches up with
 376                  * what the GIC reports, otherwise we'll have configured
 377                  * interrupts incorrectly.
 378                  */
 379                 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
 380         }
 381
 382         if (core > 0 && !read_gcr_cl_coherence())
 383                 pr_warn("Core %u is not in coherent domain\n", core);
 384
 385         if (cpu_has_veic)
 386                 clear_c0_status(ST0_IM);
 387         else
 388                 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
 389                                          STATUSF_IP4 | STATUSF_IP5 |
 390                                          STATUSF_IP6 | STATUSF_IP7);
 391 }
 392
 393 static void cps_smp_finish(void)
 394 {
 395         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 396
 397 #ifdef CONFIG_MIPS_MT_FPAFF
 398         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 399         if (cpu_has_fpu)
 400                 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
 401 #endif /* CONFIG_MIPS_MT_FPAFF */
 402
 403         local_irq_enable();
 404 }
 405
 406 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
 407
 408 enum cpu_death {
 409         CPU_DEATH_HALT,
 410         CPU_DEATH_POWER,
 411 };
 412
 413 static void cps_shutdown_this_cpu(enum cpu_death death)
 414 {
 415         unsigned int cpu, core, vpe_id;
 416
 417         cpu = smp_processor_id();
 418         core = cpu_core(&cpu_data[cpu]);
 419
 420         if (death == CPU_DEATH_HALT) {
 421                 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 422
 423                 pr_debug("Halting core %d VP%d\n", core, vpe_id);
 424                 if (cpu_has_mipsmt) {
 425                         /* Halt this TC */
 426                         write_c0_tchalt(TCHALT_H);
 427                         instruction_hazard();
 428                 } else if (cpu_has_vp) {
 429                         write_cpc_cl_vp_stop(1 << vpe_id);
 430
 431                         /* Ensure that the VP_STOP register is written */
 432                         wmb();
 433                 }
 434         } else {
 435                 if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) {
 436                         pr_debug("Gating power to core %d\n", core);
 437                         /* Power down the core */
 438                         cps_pm_enter_state(CPS_PM_POWER_GATED);
 439                 }
 440         }
 441 }
 442
 443 #ifdef CONFIG_KEXEC
 444
 445 static void cps_kexec_nonboot_cpu(void)
 446 {
 447         if (cpu_has_mipsmt || cpu_has_vp)
 448                 cps_shutdown_this_cpu(CPU_DEATH_HALT);
 449         else
 450                 cps_shutdown_this_cpu(CPU_DEATH_POWER);
 451 }
 452
 453 #endif /* CONFIG_KEXEC */
 454
 455 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
 456
 457 #ifdef CONFIG_HOTPLUG_CPU
 458
 459 static int cps_cpu_disable(void)
 460 {
 461         unsigned cpu = smp_processor_id();
 462         struct core_boot_config *core_cfg;
 463
 464         if (!cps_pm_support_state(CPS_PM_POWER_GATED))
 465                 return -EINVAL;
 466
 467         core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)];
 468         atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
 469         smp_mb__after_atomic();
 470         set_cpu_online(cpu, false);
 471         calculate_cpu_foreign_map();
 472         irq_migrate_all_off_this_cpu();
 473
 474         return 0;
 475 }
 476
 477 static unsigned cpu_death_sibling;
 478 static enum cpu_death cpu_death;
 479
 480 void play_dead(void)
 481 {
 482         unsigned int cpu;
 483
 484         local_irq_disable();
 485         idle_task_exit();
 486         cpu = smp_processor_id();
 487         cpu_death = CPU_DEATH_POWER;
 488
 489         pr_debug("CPU%d going offline\n", cpu);
 490
 491         if (cpu_has_mipsmt || cpu_has_vp) {
 492                 /* Look for another online VPE within the core */
 493                 for_each_online_cpu(cpu_death_sibling) {
 494                         if (!cpus_are_siblings(cpu, cpu_death_sibling))
 495                                 continue;
 496
 497                         /*
 498                          * There is an online VPE within the core. Just halt
 499                          * this TC and leave the core alone.
 500                          */
 501                         cpu_death = CPU_DEATH_HALT;
 502                         break;
 503                 }
 504         }
 505
 506         /* This CPU has chosen its way out */
 507         (void)cpu_report_death();
 508
 509         cps_shutdown_this_cpu(cpu_death);
 510
 511         /* This should never be reached */
 512         panic("Failed to offline CPU %u", cpu);
 513 }
 514
 515 static void wait_for_sibling_halt(void *ptr_cpu)
 516 {
 517         unsigned cpu = (unsigned long)ptr_cpu;
 518         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 519         unsigned halted;
 520         unsigned long flags;
 521
 522         do {
 523                 local_irq_save(flags);
 524                 settc(vpe_id);
 525                 halted = read_tc_c0_tchalt();
 526                 local_irq_restore(flags);
 527         } while (!(halted & TCHALT_H));
 528 }
 529
 530 static void cps_cpu_die(unsigned int cpu)
 531 {
 532         unsigned core = cpu_core(&cpu_data[cpu]);
 533         unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 534         ktime_t fail_time;
 535         unsigned stat;
 536         int err;
 537
 538         /* Wait for the cpu to choose its way out */
 539         if (!cpu_wait_death(cpu, 5)) {
 540                 pr_err("CPU%u: didn't offline\n", cpu);
 541                 return;
 542         }
 543
 544         /*
 545          * Now wait for the CPU to actually offline. Without doing this that
 546          * offlining may race with one or more of:
 547          *
 548          *   - Onlining the CPU again.
 549          *   - Powering down the core if another VPE within it is offlined.
 550          *   - A sibling VPE entering a non-coherent state.
 551          *
 552          * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
 553          * with which we could race, so do nothing.
 554          */
 555         if (cpu_death == CPU_DEATH_POWER) {
 556                 /*
 557                  * Wait for the core to enter a powered down or clock gated
 558                  * state, the latter happening when a JTAG probe is connected
 559                  * in which case the CPC will refuse to power down the core.
 560                  */
 561                 fail_time = ktime_add_ms(ktime_get(), 2000);
 562                 do {
 563                         mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 564                         mips_cpc_lock_other(core);
 565                         stat = read_cpc_co_stat_conf();
 566                         stat &= CPC_Cx_STAT_CONF_SEQSTATE;
 567                         stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
 568                         mips_cpc_unlock_other();
 569                         mips_cm_unlock_other();
 570
 571                         if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
 572                             stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
 573                             stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
 574                                 break;
 575
 576                         /*
 577                          * The core ought to have powered down, but didn't &
 578                          * now we don't really know what state it's in. It's
 579                          * likely that its _pwr_up pin has been wired to logic
 580                          * 1 & it powered back up as soon as we powered it
 581                          * down...
 582                          *
 583                          * The best we can do is warn the user & continue in
 584                          * the hope that the core is doing nothing harmful &
 585                          * might behave properly if we online it later.
 586                          */
 587                         if (WARN(ktime_after(ktime_get(), fail_time),
 588                                  "CPU%u hasn't powered down, seq. state %u\n",
 589                                  cpu, stat))
 590                                 break;
 591                 } while (1);
 592
 593                 /* Indicate the core is powered off */
 594                 bitmap_clear(core_power, core, 1);
 595         } else if (cpu_has_mipsmt) {
 596                 /*
 597                  * Have a CPU with access to the offlined CPUs registers wait
 598                  * for its TC to halt.
 599                  */
 600                 err = smp_call_function_single(cpu_death_sibling,
 601                                                wait_for_sibling_halt,
 602                                                (void *)(unsigned long)cpu, 1);
 603                 if (err)
 604                         panic("Failed to call remote sibling CPU\n");
 605         } else if (cpu_has_vp) {
 606                 do {
 607                         mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 608                         stat = read_cpc_co_vp_running();
 609                         mips_cm_unlock_other();
 610                 } while (stat & (1 << vpe_id));
 611         }
 612 }
 613
 614 #endif /* CONFIG_HOTPLUG_CPU */
 615
 616 static const struct plat_smp_ops cps_smp_ops = {
 617         .smp_setup              = cps_smp_setup,
 618         .prepare_cpus           = cps_prepare_cpus,
 619         .boot_secondary         = cps_boot_secondary,
 620         .init_secondary         = cps_init_secondary,
 621         .smp_finish             = cps_smp_finish,
 622         .send_ipi_single        = mips_smp_send_ipi_single,
 623         .send_ipi_mask          = mips_smp_send_ipi_mask,
 624 #ifdef CONFIG_HOTPLUG_CPU
 625         .cpu_disable            = cps_cpu_disable,
 626         .cpu_die                = cps_cpu_die,
 627 #endif
 628 #ifdef CONFIG_KEXEC
 629         .kexec_nonboot_cpu      = cps_kexec_nonboot_cpu,
 630 #endif
 631 };
 632
 633 bool mips_cps_smp_in_use(void)
 634 {
 635         extern const struct plat_smp_ops *mp_ops;
 636         return mp_ops == &cps_smp_ops;
 637 }
 638
 639 int register_cps_smp_ops(void)
 640 {
 641         if (!mips_cm_present()) {
 642                 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
 643                 return -ENODEV;
 644         }
 645
 646         /* check we have a GIC - we need one for IPIs */
 647         if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
 648                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
 649                 return -ENODEV;
 650         }
 651
 652         register_smp_ops(&cps_smp_ops);
 653         return 0;
 654 }