CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true);
+ return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen2_clk_disable(struct clk *clk)
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false);
+ return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
static ulong gen2_clk_get_rate(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true);
+ return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen3_clk_disable(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false);
+ return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
static u64 gen3_clk_get_rate64(struct clk *clk)
return 0;
}
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
+int renesas_clk_endisable(struct clk *clk, void __iomem *base,
+ struct cpg_mssr_info *info, bool enable)
{
const unsigned long clkid = clk->id & 0xffff;
const unsigned int reg = clkid / 100;
const struct cpg_core_clk **core);
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
struct clk *parent);
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
+int renesas_clk_endisable(struct clk *clk, void __iomem *base,
+ struct cpg_mssr_info *info, bool enable);
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */