clk: k210: Fix PLLs not being enabled

After starting or setting the rate of a PLL, the enable bit must be set.

This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.

Signed-off-by: Sean Anderson <[email protected]>
Reviewed-by: Damien Le Moal <[email protected]>

diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
index ab6d75d585abdc89ffcf13c57f0cbbd2e44e02ec..f198920113119459c6950102fea1aab1da2771c9 100644 (file)
--- a/drivers/clk/kendryte/pll.c
+++ b/drivers/clk/kendryte/pll.c
@@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk)
        k210_pll_waitfor_lock(pll);
 
        reg &= ~K210_PLL_BYPASS;
+       reg |= K210_PLL_EN;
        writel(reg, pll->reg);
 
        return 0;
@@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk)
        writel(reg, pll->reg);
 
        reg &= ~K210_PLL_PWRD;
+       reg &= ~K210_PLL_EN;
        writel(reg, pll->reg);
        return 0;
 }