arm: socfpga: reset: Add function to reset FPGA bridges

Add function to enable and disable FPGA bridges. This code is used
by the FPGA manager to disable the bridges before programming the
FPGA and will later be also used by the initialization code for the
chip to put the chip into well defined state during startup.

Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
Cc: Albert Aribaud <[email protected]>
Cc: Tom Rini <[email protected]>
Cc: Wolfgang Denk <[email protected]>
Cc: Pavel Machek <[email protected]>
Acked-by: Pavel Machek <[email protected]>

diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index badc569582046294ed4576e9072232452e66c9ad..1d3a95d0c8e73cef22666f5f8adf42ba77e4f471 100644 (file)
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -8,6 +8,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/reset_manager.h>
+#include <asm/arch/fpga_manager.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -50,6 +51,43 @@ void reset_deassert_peripherals_handoff(void)
        writel(0, &reset_manager_base->per_mod_reset);
 }
 
+#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
+void socfpga_bridges_reset(int enable)
+{
+       /* For SoCFPGA-VT, this is NOP. */
+}
+#else
+
+#define L3REGS_REMAP_LWHPS2FPGA_MASK   0x10
+#define L3REGS_REMAP_HPS2FPGA_MASK     0x08
+#define L3REGS_REMAP_OCRAM_MASK                0x01
+
+void socfpga_bridges_reset(int enable)
+{
+       const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
+                               L3REGS_REMAP_HPS2FPGA_MASK |
+                               L3REGS_REMAP_OCRAM_MASK;
+
+       if (enable) {
+               /* brdmodrst */
+               writel(0xffffffff, &reset_manager_base->brg_mod_reset);
+       } else {
+               /* Check signal from FPGA. */
+               if (fpgamgr_poll_fpga_ready()) {
+                       /* FPGA not ready. Wait for watchdog timeout. */
+                       printf("%s: fpga not ready, hanging.\n", __func__);
+                       hang();
+               }
+
+               /* brdmodrst */
+               writel(0, &reset_manager_base->brg_mod_reset);
+
+               /* Remap the bridges into memory map */
+               writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
+       }
+}
+#endif
+
 /* Change the reset state for EMAC 0 and EMAC 1 */
 void socfpga_emac_reset(int enable)
 {

diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 3c5ab401e1ed94a8e896e5120e00ebdd5cff697f..1857b80b3e44005bfb13b3fb50054d01734fb7ab 100644 (file)
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -10,6 +10,8 @@
 void reset_cpu(ulong addr);
 void reset_deassert_peripherals_handoff(void);
 
+void socfpga_bridges_reset(int enable);
+
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);