armv8/mmu: Clean up TCR programming

Use the inner shareable attribute for memory, which makes more sense
considering that this code is called when caches are being enabled.

Cc: Albert Aribaud <[email protected]>
Cc: Marc Zyngier <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 0c928d40e7ebe6e35a2a51f3745dd923fbe3e4b4..a1c3c065399b3636067f6c8e9ccb03a027e1b382 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -103,9 +103,9 @@
 #define TCR_EL2_IPS_BITS       (3 << 16)       /* 42 bits physical address */
 #define TCR_EL3_IPS_BITS       (3 << 16)       /* 42 bits physical address */
 
-/* PTWs cacheable, inner/outer WBWA and non-shareable */
+/* PTWs cacheable, inner/outer WBWA and inner shareable */
 #define TCR_FLAGS              (TCR_TG0_64K |          \
-                               TCR_SHARED_NON |        \
+                               TCR_SHARED_INNER |      \
                                TCR_ORGN_WBWA |         \
                                TCR_IRGN_WBWA |         \
                                TCR_T0SZ(VA_BITS))