arm64: dts: imx8mp: rename DHCOM SoM overlays to .dtso

Distinguish more clearly between source files meant for producing .dtb
from those meant for producing .dtbo. No functional change, as we
currently have rules for producing a foo.dtbo from either foo.dts or
foo.dtso.

Note that in the linux tree, all device tree overlay sources have been
renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit
81d362732bac). So this is also a step towards staying closer to linux
with respect to both Kbuild and device tree sources.

Cc: Marek Vasut <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts
deleted file mode 100644 (file)
index 3b39777..0000000
--- a/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2023 Marek Vasut <[email protected]>
- */
-/dts-v1/;
-/plugin/;
-
-&ethphypdk {   /* Micrel KSZ9131RNXI */
-       status = "disabled";
-};

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso
new file mode 100644 (file)
index 0000000..3b39777
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-pdk-overlay-eth2xfast.dtso
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <[email protected]>
+ */
+/dts-v1/;
+/plugin/;
+
+&ethphypdk {   /* Micrel KSZ9131RNXI */
+       status = "disabled";
+};

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts
deleted file mode 100644 (file)
index f27e642..0000000
--- a/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dts
+++ /dev/null
@@ -1,10 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2023 Marek Vasut <[email protected]>
- */
-/dts-v1/;
-/plugin/;
-
-&ethphy0g {
-       reg = <7>;
-};

diff --git a/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtso b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtso
new file mode 100644 (file)
index 0000000..f27e642
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-pdk3-overlay-rev100.dtso
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <[email protected]>
+ */
+/dts-v1/;
+/plugin/;
+
+&ethphy0g {
+       reg = <7>;
+};

diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts
deleted file mode 100644 (file)
index bb5a2b6..0000000
--- a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dts
+++ /dev/null
@@ -1,43 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2023 Marek Vasut <[email protected]>
- */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/clock/imx8mp-clock.h>
-
-&eqos {        /* First ethernet */
-       pinctrl-0 = <&pinctrl_eqos_rmii>;
-       phy-handle = <&ethphy0f>;
-       phy-mode = "rmii";
-
-       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
-                                <&clk IMX8MP_SYS_PLL2_100M>,
-                                <&clk IMX8MP_SYS_PLL2_50M>;
-       assigned-clock-rates = <0>, <100000000>, <50000000>;
-};
-
-&ethphy0g {    /* Micrel KSZ9131RNXI */
-       status = "disabled";
-};
-
-&ethphy0f {    /* SMSC LAN8740Ai */
-       status = "okay";
-};
-
-&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */
-       status = "disabled";
-};
-
-/* No WiFi/BT chipset on this SoM variant. */
-
-&uart2 {
-       bluetooth {
-               status = "disabled";
-       };
-};
-
-&usdhc1 {
-       status = "disabled";
-};

diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dtso b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dtso
new file mode 100644 (file)
index 0000000..bb5a2b6
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth1xfast.dtso
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <[email protected]>
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8mp-clock.h>
+
+&eqos {        /* First ethernet */
+       pinctrl-0 = <&pinctrl_eqos_rmii>;
+       phy-handle = <&ethphy0f>;
+       phy-mode = "rmii";
+
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+                                <&clk IMX8MP_SYS_PLL2_100M>,
+                                <&clk IMX8MP_SYS_PLL2_50M>;
+       assigned-clock-rates = <0>, <100000000>, <50000000>;
+};
+
+&ethphy0g {    /* Micrel KSZ9131RNXI */
+       status = "disabled";
+};
+
+&ethphy0f {    /* SMSC LAN8740Ai */
+       status = "okay";
+};
+
+&fec { /* Second ethernet -- HS connector not populated on 1x RMII PHY SoM */
+       status = "disabled";
+};
+
+/* No WiFi/BT chipset on this SoM variant. */
+
+&uart2 {
+       bluetooth {
+               status = "disabled";
+       };
+};
+
+&usdhc1 {
+       status = "disabled";
+};

diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts
deleted file mode 100644 (file)
index 82dadce..0000000
--- a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dts
+++ /dev/null
@@ -1,24 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2023 Marek Vasut <[email protected]>
- */
-#include "imx8mp-dhcom-som-overlay-eth1xfast.dts"
-
-/* Dual RMII 100/Full Fast ethernet on this SoM variant. */
-
-&fec { /* Second ethernet */
-       pinctrl-0 = <&pinctrl_fec_rmii>;
-       phy-handle = <&ethphy1f>;
-       phy-mode = "rmii";
-       status = "okay";
-
-       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
-                                <&clk IMX8MP_SYS_PLL2_100M>,
-                                <&clk IMX8MP_SYS_PLL2_50M>,
-                                <&clk IMX8MP_SYS_PLL2_50M>;
-       assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
-};
-
-&ethphy1f {    /* SMSC LAN8740Ai */
-       status = "okay";
-};

diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dtso b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dtso
new file mode 100644 (file)
index 0000000..f2d768c
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-eth2xfast.dtso
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <[email protected]>
+ */
+#include "imx8mp-dhcom-som-overlay-eth1xfast.dtso"
+
+/* Dual RMII 100/Full Fast ethernet on this SoM variant. */
+
+&fec { /* Second ethernet */
+       pinctrl-0 = <&pinctrl_fec_rmii>;
+       phy-handle = <&ethphy1f>;
+       phy-mode = "rmii";
+       status = "okay";
+
+       assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
+                                <&clk IMX8MP_SYS_PLL2_100M>,
+                                <&clk IMX8MP_SYS_PLL2_50M>,
+                                <&clk IMX8MP_SYS_PLL2_50M>;
+       assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
+};
+
+&ethphy1f {    /* SMSC LAN8740Ai */
+       status = "okay";
+};

diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
deleted file mode 100644 (file)
index b2154d5..0000000
--- a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dts
+++ /dev/null
@@ -1,133 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2023 Marek Vasut <[email protected]>
- */
-/dts-v1/;
-/plugin/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-#include "imx8mp-pinfunc.h"
-
-&brcmf {
-       reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
-};
-
-&eeprom0 {     /* EEPROM with EQoS MAC address */
-       compatible = "atmel,24c02";
-       pagesize = <16>;
-};
-
-&eeprom1 {     /* EEPROM with FEC MAC address */
-       compatible = "atmel,24c02";
-       pagesize = <16>;
-};
-
-&eeprom0wl {
-       status = "disabled";
-};
-
-&eeprom1wl {
-       status = "disabled";
-};
-
-&ethphy0f { /* SMSC LAN8740Ai */
-       pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
-       reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
-       reg = <0>;
-};
-
-&ethphy0g { /* Micrel KSZ9131RNXI */
-       pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
-       reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
-};
-
-&ethphy1f { /* SMSC LAN8740Ai */
-       reg = <1>;
-};
-
-&i2c3 {
-       adc@48 {
-               compatible = "ti,tla2024";
-               interrupts-extended;
-       };
-};
-
-&ioexp {
-       status = "disabled";
-};
-
-&reg_eth_vio {
-       gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
-       pinctrl-0 = <&pinctrl_enet_vio>;
-       pinctrl-names = "default";
-};
-
-&rv3032 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_rtc>;
-       interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
-};
-
-&uart2 {
-       bluetooth {
-               pinctrl-names = "default";
-               pinctrl-0 = <&pinctrl_uart2_bt>;
-               shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
-       };
-};
-
-&usb_dwc3_0 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usb0_vbus>;
-};
-
-&usdhc1 {
-       pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>;
-       pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>;
-       pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>;
-};
-
-&iomuxc {
-       pinctrl-0 = <&pinctrl_hog_base
-                    &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
-                    &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
-                    &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
-                    &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
-                    /* GPIO_M is connected to CLKOUT2 */
-                    &pinctrl_dhcom_int>;
-
-       pinctrl_enet_vio: dhcom-enet-vio-grp {
-               fsl,pins = <
-                       MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10            0x22
-               >;
-       };
-
-       pinctrl_rtc: dhcom-rtc-grp {
-               fsl,pins = <
-                       /* RTC_#INT Interrupt */
-                       MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05          0x400001c6
-               >;
-       };
-
-       pinctrl_uart2_bt: dhcom-uart2-bt-grp {
-               fsl,pins = <
-                       /* BT_REG_EN */
-                       MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12             0x144
-               >;
-       };
-
-       pinctrl_usb0_vbus: dhcom-usb0-grp {
-               fsl,pins = <
-                       MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID            0x0
-               >;
-       };
-
-       pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp {
-               fsl,pins = <
-                       /* WL_REG_EN */
-                       MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13             0x144
-               >;
-       };
-};

diff --git a/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dtso b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dtso
new file mode 100644 (file)
index 0000000..b2154d5
--- /dev/null
+++ b/arch/arm/dts/imx8mp-dhcom-som-overlay-rev100.dtso
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2023 Marek Vasut <[email protected]>
+ */
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#include "imx8mp-pinfunc.h"
+
+&brcmf {
+       reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+};
+
+&eeprom0 {     /* EEPROM with EQoS MAC address */
+       compatible = "atmel,24c02";
+       pagesize = <16>;
+};
+
+&eeprom1 {     /* EEPROM with FEC MAC address */
+       compatible = "atmel,24c02";
+       pagesize = <16>;
+};
+
+&eeprom0wl {
+       status = "disabled";
+};
+
+&eeprom1wl {
+       status = "disabled";
+};
+
+&ethphy0f { /* SMSC LAN8740Ai */
+       pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
+       reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+       reg = <0>;
+};
+
+&ethphy0g { /* Micrel KSZ9131RNXI */
+       pinctrl-0 = <&pinctrl_ethphy0 &pinctrl_ioexp>;
+       reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
+};
+
+&ethphy1f { /* SMSC LAN8740Ai */
+       reg = <1>;
+};
+
+&i2c3 {
+       adc@48 {
+               compatible = "ti,tla2024";
+               interrupts-extended;
+       };
+};
+
+&ioexp {
+       status = "disabled";
+};
+
+&reg_eth_vio {
+       gpio = <&gpio2 10 GPIO_ACTIVE_LOW>;
+       pinctrl-0 = <&pinctrl_enet_vio>;
+       pinctrl-names = "default";
+};
+
+&rv3032 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_rtc>;
+       interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
+};
+
+&uart2 {
+       bluetooth {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_uart2_bt>;
+               shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+       };
+};
+
+&usb_dwc3_0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usb0_vbus>;
+};
+
+&usdhc1 {
+       pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_wl_reg_en>;
+       pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_usdhc1_wl_reg_en>;
+       pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_usdhc1_wl_reg_en>;
+};
+
+&iomuxc {
+       pinctrl-0 = <&pinctrl_hog_base
+                    &pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
+                    &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
+                    &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i
+                    &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l
+                    /* GPIO_M is connected to CLKOUT2 */
+                    &pinctrl_dhcom_int>;
+
+       pinctrl_enet_vio: dhcom-enet-vio-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10            0x22
+               >;
+       };
+
+       pinctrl_rtc: dhcom-rtc-grp {
+               fsl,pins = <
+                       /* RTC_#INT Interrupt */
+                       MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05          0x400001c6
+               >;
+       };
+
+       pinctrl_uart2_bt: dhcom-uart2-bt-grp {
+               fsl,pins = <
+                       /* BT_REG_EN */
+                       MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12             0x144
+               >;
+       };
+
+       pinctrl_usb0_vbus: dhcom-usb0-grp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID            0x0
+               >;
+       };
+
+       pinctrl_usdhc1_wl_reg_en: dhcom-usdhc1-wl-reg-en-grp {
+               fsl,pins = <
+                       /* WL_REG_EN */
+                       MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13             0x144
+               >;
+       };
+};