include/configs/TQM834x.h

   1 /*
   2  * (C) Copyright 2005
   3  * Wolfgang Denk, DENX Software Engineering, [email protected].
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * TQM8349 board configuration file
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 #define CONFIG_SYS_GENERIC_BOARD
  16 #define CONFIG_DISPLAY_BOARDINFO
  17
  18 /*
  19  * High Level Configuration Options
  20  */
  21 #define CONFIG_E300             1       /* E300 Family */
  22 #define CONFIG_MPC834x          1       /* MPC834x specific */
  23 #define CONFIG_MPC8349          1       /* MPC8349 specific */
  24 #define CONFIG_TQM834X          1       /* TQM834X board specific */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0x80000000
  27
  28 /* IMMR Base Address Register, use Freescale default: 0xff400000 */
  29 #define CONFIG_SYS_IMMR         0xff400000
  30
  31 /* System clock. Primary input clock when in PCI host mode */
  32 #define CONFIG_83XX_CLKIN       66666000        /* 66,666 MHz */
  33
  34 /*
  35  * Local Bus LCRR
  36  *    LCRR:  DLL bypass, Clock divider is 8
  37  *
  38  *    for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
  39  *
  40  * External Local Bus rate is
  41  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
  42  */
  43 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
  44 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_8
  45
  46 /* board pre init: do not call, nothing to do */
  47 #undef CONFIG_BOARD_EARLY_INIT_F
  48
  49 /* detect the number of flash banks */
  50 #define CONFIG_BOARD_EARLY_INIT_R
  51
  52 /*
  53  * DDR Setup
  54  */
  55                                 /* DDR is system memory*/
  56 #define CONFIG_SYS_DDR_BASE     0x00000000
  57 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  58 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  59 #define DDR_CASLAT_25           /* CASLAT set to 2.5 */
  60 #undef CONFIG_DDR_ECC           /* only for ECC DDR module */
  61 #undef CONFIG_SPD_EEPROM        /* do not use SPD EEPROM for DDR setup */
  62
  63 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  64 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  65 #define CONFIG_SYS_MEMTEST_END          0x00100000
  66
  67 /*
  68  * FLASH on the Local Bus
  69  */
  70 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
  71 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
  72 #undef CONFIG_SYS_FLASH_CHECKSUM
  73 #define CONFIG_SYS_FLASH_BASE           0x80000000      /* start of FLASH   */
  74 #define CONFIG_SYS_FLASH_SIZE           8               /* FLASH size in MB */
  75 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sectors */
  76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  77
  78 /*
  79  * FLASH bank number detection
  80  */
  81
  82 /*
  83  * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
  84  * Flash banks has to be determined at runtime and stored in a gloabl variable
  85  * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
  86  * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
  87  * flash_info, and should be made sufficiently large to accomodate the number
  88  * of banks that might actually be detected.  Since most (all?) Flash related
  89  * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
  90  * the board, it is defined as tqm834x_num_flash_banks.
  91  */
  92 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT       2
  93
  94 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max sectors per device */
  95
  96 /* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
  97 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_FLASH_BASE & BR_BA) \
  98                                 | BR_MS_GPCM \
  99                                 | BR_PS_32 \
 100                                 | BR_V)
 101
 102 /* FLASH timing (0x0000_0c54) */
 103 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_GPCM_CSNT \
 104                                         | OR_GPCM_ACS_DIV4 \
 105                                         | OR_GPCM_SCY_5 \
 106                                         | OR_GPCM_TRLX)
 107
 108 #define CONFIG_SYS_PRELIM_OR_AM         OR_AM_1GB /* OR addr mask: 1 GiB */
 109
 110 #define CONFIG_SYS_OR0_PRELIM           (CONFIG_SYS_PRELIM_OR_AM  \
 111                                         | CONFIG_SYS_OR_TIMING_FLASH)
 112
 113 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_1GB)
 114
 115                                         /* Window base at flash base */
 116 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 117
 118 /* disable remaining mappings */
 119 #define CONFIG_SYS_BR1_PRELIM           0x00000000
 120 #define CONFIG_SYS_OR1_PRELIM           0x00000000
 121 #define CONFIG_SYS_LBLAWBAR1_PRELIM     0x00000000
 122 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x00000000
 123
 124 #define CONFIG_SYS_BR2_PRELIM           0x00000000
 125 #define CONFIG_SYS_OR2_PRELIM           0x00000000
 126 #define CONFIG_SYS_LBLAWBAR2_PRELIM     0x00000000
 127 #define CONFIG_SYS_LBLAWAR2_PRELIM      0x00000000
 128
 129 #define CONFIG_SYS_BR3_PRELIM           0x00000000
 130 #define CONFIG_SYS_OR3_PRELIM           0x00000000
 131 #define CONFIG_SYS_LBLAWBAR3_PRELIM     0x00000000
 132 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x00000000
 133
 134 /*
 135  * Monitor config
 136  */
 137 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 138
 139 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 140 # define CONFIG_SYS_RAMBOOT
 141 #else
 142 # undef  CONFIG_SYS_RAMBOOT
 143 #endif
 144
 145 #define CONFIG_SYS_INIT_RAM_LOCK        1
 146 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000 /* Initial RAM address */
 147 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM*/
 148
 149 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 150                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 151 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 152
 153                                 /* Reserve 384 kB = 3 sect. for Mon */
 154 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024)
 155                                 /* Reserve 512 kB for malloc */
 156 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024)
 157
 158 /*
 159  * Serial Port
 160  */
 161 #define CONFIG_CONS_INDEX       1
 162 #define CONFIG_SYS_NS16550
 163 #define CONFIG_SYS_NS16550_SERIAL
 164 #define CONFIG_SYS_NS16550_REG_SIZE     1
 165 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 166
 167 #define CONFIG_SYS_BAUDRATE_TABLE  \
 168                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 169
 170 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 171 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 172
 173 /*
 174  * I2C
 175  */
 176 #define CONFIG_SYS_I2C
 177 #define CONFIG_SYS_I2C_FSL
 178 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 179 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 180 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 181
 182 /* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
 183 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16 bit */
 185 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32 bytes/write */
 186 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   12      /* 10ms +/- 20% */
 187 #define CONFIG_SYS_I2C_MULTI_EEPROMS            /* more than one eeprom */
 188
 189 /* I2C RTC */
 190 #define CONFIG_RTC_DS1337                       /* use ds1337 rtc via i2c */
 191 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68 */
 192
 193 /* I2C SYSMON (LM75) */
 194 #define CONFIG_DTT_LM75                 1       /* ON Semi's LM75 */
 195 #define CONFIG_DTT_SENSORS              {0}     /* Sensor addresses */
 196 #define CONFIG_SYS_DTT_MAX_TEMP         70
 197 #define CONFIG_SYS_DTT_LOW_TEMP         -30
 198 #define CONFIG_SYS_DTT_HYSTERESIS       3
 199
 200 /*
 201  * TSEC
 202  */
 203 #define CONFIG_TSEC_ENET                /* tsec ethernet support */
 204 #define CONFIG_MII
 205
 206 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 207 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 208 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 209 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
 210
 211 #if defined(CONFIG_TSEC_ENET)
 212
 213 #define CONFIG_TSEC1            1
 214 #define CONFIG_TSEC1_NAME       "TSEC0"
 215 #define CONFIG_TSEC2            1
 216 #define CONFIG_TSEC2_NAME       "TSEC1"
 217 #define TSEC1_PHY_ADDR          2
 218 #define TSEC2_PHY_ADDR          1
 219 #define TSEC1_PHYIDX            0
 220 #define TSEC2_PHYIDX            0
 221 #define TSEC1_FLAGS             TSEC_GIGABIT
 222 #define TSEC2_FLAGS             TSEC_GIGABIT
 223
 224 /* Options are: TSEC[0-1] */
 225 #define CONFIG_ETHPRIME         "TSEC0"
 226
 227 #endif  /* CONFIG_TSEC_ENET */
 228
 229 /*
 230  * General PCI
 231  * Addresses are mapped 1-1.
 232  */
 233 #define CONFIG_PCI
 234
 235 #if defined(CONFIG_PCI)
 236
 237 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 238 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 239
 240 /* PCI1 host bridge */
 241 #define CONFIG_SYS_PCI1_MEM_BASE        0x90000000
 242 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 243 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 244 #define CONFIG_SYS_PCI1_MMIO_BASE       \
 245                         (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
 246 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 247 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 248 #define CONFIG_SYS_PCI1_IO_BASE         0xe2000000
 249 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 250 #define CONFIG_SYS_PCI1_IO_SIZE         0x1000000       /* 16M */
 251
 252 #undef CONFIG_EEPRO100
 253 #define CONFIG_EEPRO100
 254 #undef CONFIG_TULIP
 255
 256 #if !defined(CONFIG_PCI_PNP)
 257         #define PCI_ENET0_IOADDR        CONFIG_SYS_PCI1_IO_BASE
 258         #define PCI_ENET0_MEMADDR       CONFIG_SYS_PCI1_MEM_BASE
 259         #define PCI_IDSEL_NUMBER        0x1c    /* slot0 (IDSEL) = 28 */
 260 #endif
 261
 262 #define CONFIG_SYS_PCI_SUBSYS_VENDORID          0x1957  /* Freescale */
 263
 264 #endif  /* CONFIG_PCI */
 265
 266 /*
 267  * Environment
 268  */
 269 #define CONFIG_ENV_IS_IN_FLASH  1
 270 #define CONFIG_ENV_ADDR         \
 271                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 272 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) for env */
 273 #define CONFIG_ENV_SIZE         0x8000  /*  32K max size */
 274 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 275 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 276
 277 #define CONFIG_LOADS_ECHO               1 /* echo on for serial download */
 278 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1 /* allow baudrate change */
 279
 280 /*
 281  * BOOTP options
 282  */
 283 #define CONFIG_BOOTP_BOOTFILESIZE
 284 #define CONFIG_BOOTP_BOOTPATH
 285 #define CONFIG_BOOTP_GATEWAY
 286 #define CONFIG_BOOTP_HOSTNAME
 287
 288
 289 /*
 290  * Command line configuration.
 291  */
 292 #include <config_cmd_default.h>
 293
 294 #define CONFIG_CMD_ASKENV
 295 #define CONFIG_CMD_DATE
 296 #define CONFIG_CMD_DHCP
 297 #define CONFIG_CMD_DTT
 298 #define CONFIG_CMD_EEPROM
 299 #define CONFIG_CMD_I2C
 300 #define CONFIG_CMD_NFS
 301 #define CONFIG_CMD_JFFS2
 302 #define CONFIG_CMD_MII
 303 #define CONFIG_CMD_PING
 304 #define CONFIG_CMD_REGINFO
 305 #define CONFIG_CMD_SNTP
 306
 307 #if defined(CONFIG_PCI)
 308     #define CONFIG_CMD_PCI
 309 #endif
 310
 311 #if defined(CONFIG_SYS_RAMBOOT)
 312     #undef CONFIG_CMD_SAVEENV
 313     #undef CONFIG_CMD_LOADS
 314 #endif
 315
 316 /*
 317  * Miscellaneous configurable options
 318  */
 319 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 320 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 321
 322 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 323 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 324
 325 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser */
 326
 327 #if defined(CONFIG_CMD_KGDB)
 328         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 329 #else
 330         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 331 #endif
 332
 333                                 /* Print Buffer Size */
 334 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 335 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 336                                 /* Boot Argument Buffer Size */
 337 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 338
 339 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 340
 341 /* pass open firmware flat tree */
 342 #define CONFIG_OF_LIBFDT        1
 343 #define CONFIG_OF_BOARD_SETUP   1
 344 #define CONFIG_OF_STDOUT_VIA_ALIAS      1
 345
 346 /*
 347  * For booting Linux, the board info and command line data
 348  * have to be in the first 256 MB of memory, since this is
 349  * the maximum mapped by the Linux kernel during initialization.
 350  */
 351                                 /* Initial Memory map for Linux */
 352 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 353
 354 #define CONFIG_SYS_HRCW_LOW (\
 355         HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
 356         HRCWL_DDR_TO_SCB_CLK_1X1 |\
 357         HRCWL_CSB_TO_CLKIN_4X1 |\
 358         HRCWL_VCO_1X2 |\
 359         HRCWL_CORE_TO_CSB_2X1)
 360
 361 #if defined(PCI_64BIT)
 362 #define CONFIG_SYS_HRCW_HIGH (\
 363         HRCWH_PCI_HOST |\
 364         HRCWH_64_BIT_PCI |\
 365         HRCWH_PCI1_ARBITER_ENABLE |\
 366         HRCWH_PCI2_ARBITER_DISABLE |\
 367         HRCWH_CORE_ENABLE |\
 368         HRCWH_FROM_0X00000100 |\
 369         HRCWH_BOOTSEQ_DISABLE |\
 370         HRCWH_SW_WATCHDOG_DISABLE |\
 371         HRCWH_ROM_LOC_LOCAL_16BIT |\
 372         HRCWH_TSEC1M_IN_GMII |\
 373         HRCWH_TSEC2M_IN_GMII)
 374 #else
 375 #define CONFIG_SYS_HRCW_HIGH (\
 376         HRCWH_PCI_HOST |\
 377         HRCWH_32_BIT_PCI |\
 378         HRCWH_PCI1_ARBITER_ENABLE |\
 379         HRCWH_PCI2_ARBITER_DISABLE |\
 380         HRCWH_CORE_ENABLE |\
 381         HRCWH_FROM_0X00000100 |\
 382         HRCWH_BOOTSEQ_DISABLE |\
 383         HRCWH_SW_WATCHDOG_DISABLE |\
 384         HRCWH_ROM_LOC_LOCAL_16BIT |\
 385         HRCWH_TSEC1M_IN_GMII |\
 386         HRCWH_TSEC2M_IN_GMII)
 387 #endif
 388
 389 /* System IO Config */
 390 #define CONFIG_SYS_SICRH        0
 391 #define CONFIG_SYS_SICRL        SICRL_LDP_A
 392
 393 /* i-cache and d-cache disabled */
 394 #define CONFIG_SYS_HID0_INIT    0x000000000
 395 #define CONFIG_SYS_HID0_FINAL   (CONFIG_SYS_HID0_INIT | \
 396                                  HID0_ENABLE_INSTRUCTION_CACHE)
 397 #define CONFIG_SYS_HID2 HID2_HBE
 398
 399 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 400
 401 /* DDR 0 - 512M */
 402 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 403                                 | BATL_PP_RW \
 404                                 | BATL_MEMCOHERENCE)
 405 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 406                                 | BATU_BL_256M \
 407                                 | BATU_VS \
 408                                 | BATU_VP)
 409 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 410                                 | BATL_PP_RW \
 411                                 | BATL_MEMCOHERENCE)
 412 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
 413                                 | BATU_BL_256M \
 414                                 | BATU_VS \
 415                                 | BATU_VP)
 416
 417 /* stack in DCACHE @ 512M (no backing mem) */
 418 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_INIT_RAM_ADDR \
 419                                 | BATL_PP_RW \
 420                                 | BATL_MEMCOHERENCE)
 421 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_INIT_RAM_ADDR \
 422                                 | BATU_BL_128K \
 423                                 | BATU_VS \
 424                                 | BATU_VP)
 425
 426 /* PCI */
 427 #ifdef CONFIG_PCI
 428 #define CONFIG_PCI_INDIRECT_BRIDGE
 429 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_PCI1_MEM_BASE \
 430                                 | BATL_PP_RW \
 431                                 | BATL_MEMCOHERENCE)
 432 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_PCI1_MEM_BASE \
 433                                 | BATU_BL_256M \
 434                                 | BATU_VS \
 435                                 | BATU_VP)
 436 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_PCI1_MMIO_BASE \
 437                                 | BATL_PP_RW \
 438                                 | BATL_MEMCOHERENCE \
 439                                 | BATL_GUARDEDSTORAGE)
 440 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_PCI1_MMIO_BASE \
 441                                 | BATU_BL_256M \
 442                                 | BATU_VS \
 443                                 | BATU_VP)
 444 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_IO_BASE \
 445                                 | BATL_PP_RW \
 446                                 | BATL_CACHEINHIBIT \
 447                                 | BATL_GUARDEDSTORAGE)
 448 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_IO_BASE \
 449                                 | BATU_BL_16M \
 450                                 | BATU_VS \
 451                                 | BATU_VP)
 452 #else
 453 #define CONFIG_SYS_IBAT3L       (0)
 454 #define CONFIG_SYS_IBAT3U       (0)
 455 #define CONFIG_SYS_IBAT4L       (0)
 456 #define CONFIG_SYS_IBAT4U       (0)
 457 #define CONFIG_SYS_IBAT5L       (0)
 458 #define CONFIG_SYS_IBAT5U       (0)
 459 #endif
 460
 461 /* IMMRBAR */
 462 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_IMMR \
 463                                 | BATL_PP_RW \
 464                                 | BATL_CACHEINHIBIT \
 465                                 | BATL_GUARDEDSTORAGE)
 466 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_IMMR \
 467                                 | BATU_BL_1M \
 468                                 | BATU_VS \
 469                                 | BATU_VP)
 470
 471 /* FLASH */
 472 #define CONFIG_SYS_IBAT7L       (CONFIG_SYS_FLASH_BASE \
 473                                 | BATL_PP_RW \
 474                                 | BATL_CACHEINHIBIT \
 475                                 | BATL_GUARDEDSTORAGE)
 476 #define CONFIG_SYS_IBAT7U       (CONFIG_SYS_FLASH_BASE \
 477                                 | BATU_BL_256M \
 478                                 | BATU_VS \
 479                                 | BATU_VP)
 480
 481 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 482 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 483 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 484 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 485 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 486 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 487 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 488 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 489 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 490 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 491 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 492 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 493 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 494 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 495 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 496 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 497
 498 #if defined(CONFIG_CMD_KGDB)
 499 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 500 #endif
 501
 502 /*
 503  * Environment Configuration
 504  */
 505
 506                                 /* default location for tftp and bootm */
 507 #define CONFIG_LOADADDR         400000
 508
 509 #define CONFIG_BOOTDELAY        6       /* -1 disables auto-boot */
 510 #undef  CONFIG_BOOTARGS         /* the boot command will set bootargs */
 511
 512 #define CONFIG_BAUDRATE         115200
 513
 514 #define CONFIG_PREBOOT  "echo;" \
 515         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 516         "echo"
 517
 518 #undef  CONFIG_BOOTARGS
 519
 520 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 521         "netdev=eth0\0"                                                 \
 522         "hostname=tqm834x\0"                                            \
 523         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 524                 "nfsroot=${serverip}:${rootpath}\0"                     \
 525         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 526         "addip=setenv bootargs ${bootargs} "                            \
 527                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 528                 ":${hostname}:${netdev}:off panic=1\0"                  \
 529         "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
 530         "flash_nfs_old=run nfsargs addip addcons;"                      \
 531                 "bootm ${kernel_addr}\0"                                \
 532         "flash_nfs=run nfsargs addip addcons;"                          \
 533                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 534         "flash_self_old=run ramargs addip addcons;"                     \
 535                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 536         "flash_self=run ramargs addip addcons;"                         \
 537                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 538         "net_nfs_old=tftp 400000 ${bootfile};"                          \
 539                 "run nfsargs addip addcons;bootm\0"                     \
 540         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 541                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 542                 "run nfsargs addip addcons; "                           \
 543                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 544         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 545         "bootfile=tqm834x/uImage\0"                                     \
 546         "fdtfile=tqm834x/tqm834x.dtb\0"                                 \
 547         "kernel_addr_r=400000\0"                                        \
 548         "fdt_addr_r=600000\0"                                           \
 549         "ramdisk_addr_r=800000\0"                                       \
 550         "kernel_addr=800C0000\0"                                        \
 551         "fdt_addr=800A0000\0"                                           \
 552         "ramdisk_addr=80300000\0"                                       \
 553         "u-boot=tqm834x/u-boot.bin\0"                                   \
 554         "load=tftp 200000 ${u-boot}\0"                                  \
 555         "update=protect off 80000000 +${filesize};"                     \
 556                 "era 80000000 +${filesize};"                            \
 557                 "cp.b 200000 80000000 ${filesize}\0"                    \
 558         "upd=run load update\0"                                         \
 559         ""
 560
 561 #define CONFIG_BOOTCOMMAND      "run flash_self"
 562
 563 /*
 564  * JFFS2 partitions
 565  */
 566 /* mtdparts command line support */
 567 #define CONFIG_CMD_MTDPARTS
 568 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 569 #define CONFIG_FLASH_CFI_MTD
 570 #define MTDIDS_DEFAULT          "nor0=TQM834x-0"
 571
 572 /* default mtd partition table */
 573 #define MTDPARTS_DEFAULT        "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
 574                                                 "1m(kernel),2m(initrd)," \
 575                                                 "-(user);" \
 576
 577 #endif  /* __CONFIG_H */