drivers/i2c/designware_i2c.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Vipin Kumar, ST Micoelectronics, [email protected].
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <pci.h>
  14 #include <reset.h>
  15 #include <asm/io.h>
  16 #include "designware_i2c.h"
  17 #include <dm/device_compat.h>
  18 #include <linux/err.h>
  19
  20 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  21 static int  dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  22 {
  23         u32 ena = enable ? IC_ENABLE_0B : 0;
  24
  25         writel(ena, &i2c_base->ic_enable);
  26
  27         return 0;
  28 }
  29 #else
  30 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  31 {
  32         u32 ena = enable ? IC_ENABLE_0B : 0;
  33         int timeout = 100;
  34
  35         do {
  36                 writel(ena, &i2c_base->ic_enable);
  37                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  38                         return 0;
  39
  40                 /*
  41                  * Wait 10 times the signaling period of the highest I2C
  42                  * transfer supported by the driver (for 400KHz this is
  43                  * 25us) as described in the DesignWare I2C databook.
  44                  */
  45                 udelay(25);
  46         } while (timeout--);
  47         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  48
  49         return -ETIMEDOUT;
  50 }
  51 #endif
  52
  53 /* High and low times in different speed modes (in ns) */
  54 enum {
  55         /* SDA Hold Time */
  56         DEFAULT_SDA_HOLD_TIME           = 300,
  57 };
  58
  59 /**
  60  * calc_counts() - Convert a period to a number of IC clk cycles
  61  *
  62  * @ic_clk: Input clock in Hz
  63  * @period_ns: Period to represent, in ns
  64  * @return calculated count
  65  */
  66 static uint calc_counts(uint ic_clk, uint period_ns)
  67 {
  68         return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO);
  69 }
  70
  71 /**
  72  * struct i2c_mode_info - Information about an I2C speed mode
  73  *
  74  * Each speed mode has its own characteristics. This struct holds these to aid
  75  * calculations in dw_i2c_calc_timing().
  76  *
  77  * @speed: Speed in Hz
  78  * @min_scl_lowtime_ns: Minimum value for SCL low period in ns
  79  * @min_scl_hightime_ns: Minimum value for SCL high period in ns
  80  * @def_rise_time_ns: Default rise time in ns
  81  * @def_fall_time_ns: Default fall time in ns
  82  */
  83 struct i2c_mode_info {
  84         int speed;
  85         int min_scl_hightime_ns;
  86         int min_scl_lowtime_ns;
  87         int def_rise_time_ns;
  88         int def_fall_time_ns;
  89 };
  90
  91 static const struct i2c_mode_info info_for_mode[] = {
  92         [IC_SPEED_MODE_STANDARD] = {
  93                 I2C_SPEED_STANDARD_RATE,
  94                 MIN_SS_SCL_HIGHTIME,
  95                 MIN_SS_SCL_LOWTIME,
  96                 1000,
  97                 300,
  98         },
  99         [IC_SPEED_MODE_FAST] = {
 100                 I2C_SPEED_FAST_RATE,
 101                 MIN_FS_SCL_HIGHTIME,
 102                 MIN_FS_SCL_LOWTIME,
 103                 300,
 104                 300,
 105         },
 106         [IC_SPEED_MODE_FAST_PLUS] = {
 107                 I2C_SPEED_FAST_PLUS_RATE,
 108                 MIN_FP_SCL_HIGHTIME,
 109                 MIN_FP_SCL_LOWTIME,
 110                 260,
 111                 500,
 112         },
 113         [IC_SPEED_MODE_HIGH] = {
 114                 I2C_SPEED_HIGH_RATE,
 115                 MIN_HS_SCL_HIGHTIME,
 116                 MIN_HS_SCL_LOWTIME,
 117                 120,
 118                 120,
 119         },
 120 };
 121
 122 /**
 123  * dw_i2c_calc_timing() - Calculate the timings to use for a bus
 124  *
 125  * @priv: Bus private information (NULL if not using driver model)
 126  * @mode: Speed mode to use
 127  * @ic_clk: IC clock speed in Hz
 128  * @spk_cnt: Spike-suppression count
 129  * @config: Returns value to use
 130  * @return 0 if OK, -EINVAL if the calculation failed due to invalid data
 131  */
 132 static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode,
 133                               int ic_clk, int spk_cnt,
 134                               struct dw_i2c_speed_config *config)
 135 {
 136         int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt;
 137         int hcnt, lcnt, period_cnt, diff, tot;
 138         int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
 139         const struct i2c_mode_info *info;
 140
 141         /*
 142          * Find the period, rise, fall, min tlow, and min thigh in terms of
 143          * counts of the IC clock
 144          */
 145         info = &info_for_mode[mode];
 146         period_cnt = ic_clk / info->speed;
 147         scl_rise_time_ns = priv && priv->scl_rise_time_ns ?
 148                  priv->scl_rise_time_ns : info->def_rise_time_ns;
 149         scl_fall_time_ns = priv && priv->scl_fall_time_ns ?
 150                  priv->scl_fall_time_ns : info->def_fall_time_ns;
 151         rise_cnt = calc_counts(ic_clk, scl_rise_time_ns);
 152         fall_cnt = calc_counts(ic_clk, scl_fall_time_ns);
 153         min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns);
 154         min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns);
 155
 156         debug("dw_i2c: period %d rise %d fall %d tlow %d thigh %d spk %d\n",
 157               period_cnt, rise_cnt, fall_cnt, min_tlow_cnt, min_thigh_cnt,
 158               spk_cnt);
 159
 160         /*
 161          * Back-solve for hcnt and lcnt according to the following equations:
 162          * SCL_High_time = [(HCNT + IC_*_SPKLEN + 7) * ic_clk] + SCL_Fall_time
 163          * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time
 164          */
 165         hcnt = min_thigh_cnt - fall_cnt - 7 - spk_cnt;
 166         lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1;
 167
 168         if (hcnt < 0 || lcnt < 0) {
 169                 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt);
 170                 return -EINVAL;
 171         }
 172
 173         /*
 174          * Now add things back up to ensure the period is hit. If it is off,
 175          * split the difference and bias to lcnt for remainder
 176          */
 177         tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 178
 179         if (tot < period_cnt) {
 180                 diff = (period_cnt - tot) / 2;
 181                 hcnt += diff;
 182                 lcnt += diff;
 183                 tot = hcnt + lcnt + 7 + spk_cnt + rise_cnt + 1;
 184                 lcnt += period_cnt - tot;
 185         }
 186
 187         config->scl_lcnt = lcnt;
 188         config->scl_hcnt = hcnt;
 189
 190         /* Use internal default unless other value is specified */
 191         sda_hold_time_ns = priv && priv->sda_hold_time_ns ?
 192                  priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME;
 193         config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns);
 194
 195         debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt,
 196               config->sda_hold);
 197
 198         return 0;
 199 }
 200
 201 static int calc_bus_speed(struct dw_i2c *priv, int speed, ulong bus_clk,
 202                           struct dw_i2c_speed_config *config)
 203 {
 204         const struct dw_scl_sda_cfg *scl_sda_cfg = NULL;
 205         struct i2c_regs *regs = priv->regs;
 206         enum i2c_speed_mode i2c_spd;
 207         u32 comp_param1;
 208         int spk_cnt;
 209         int ret;
 210
 211         comp_param1 = readl(&regs->comp_param1);
 212
 213         if (priv)
 214                 scl_sda_cfg = priv->scl_sda_cfg;
 215         /* Allow high speed if there is no config, or the config allows it */
 216         if (speed >= I2C_SPEED_HIGH_RATE)
 217                 i2c_spd = IC_SPEED_MODE_HIGH;
 218         else if (speed >= I2C_SPEED_FAST_PLUS_RATE)
 219                 i2c_spd = IC_SPEED_MODE_FAST_PLUS;
 220         else if (speed >= I2C_SPEED_FAST_RATE)
 221                 i2c_spd = IC_SPEED_MODE_FAST;
 222         else
 223                 i2c_spd = IC_SPEED_MODE_STANDARD;
 224
 225         /* Check is high speed possible and fall back to fast mode if not */
 226         if (i2c_spd == IC_SPEED_MODE_HIGH) {
 227                 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
 228                                 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH)
 229                         i2c_spd = IC_SPEED_MODE_FAST;
 230         }
 231
 232         /* Get the proper spike-suppression count based on target speed */
 233         if (!priv || !priv->has_spk_cnt)
 234                 spk_cnt = 0;
 235         else if (i2c_spd >= IC_SPEED_MODE_HIGH)
 236                 spk_cnt = readl(&regs->hs_spklen);
 237         else
 238                 spk_cnt = readl(&regs->fs_spklen);
 239         if (scl_sda_cfg) {
 240                 config->sda_hold = scl_sda_cfg->sda_hold;
 241                 if (i2c_spd == IC_SPEED_MODE_STANDARD) {
 242                         config->scl_hcnt = scl_sda_cfg->ss_hcnt;
 243                         config->scl_lcnt = scl_sda_cfg->ss_lcnt;
 244                 } else if (i2c_spd == IC_SPEED_MODE_HIGH) {
 245                         config->scl_hcnt = scl_sda_cfg->hs_hcnt;
 246                         config->scl_lcnt = scl_sda_cfg->hs_lcnt;
 247                 } else {
 248                         config->scl_hcnt = scl_sda_cfg->fs_hcnt;
 249                         config->scl_lcnt = scl_sda_cfg->fs_lcnt;
 250                 }
 251         } else {
 252                 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt,
 253                                          config);
 254                 if (ret)
 255                         return log_msg_ret("gen_confg", ret);
 256         }
 257         config->speed_mode = i2c_spd;
 258
 259         return 0;
 260 }
 261
 262 /*
 263  * _dw_i2c_set_bus_speed - Set the i2c speed
 264  * @speed:      required i2c speed
 265  *
 266  * Set the i2c speed.
 267  */
 268 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base,
 269                                  unsigned int speed, unsigned int bus_clk)
 270 {
 271         struct dw_i2c_speed_config config;
 272         unsigned int cntl;
 273         unsigned int ena;
 274         int ret;
 275
 276         ret = calc_bus_speed(priv, speed, bus_clk, &config);
 277         if (ret)
 278                 return ret;
 279
 280         /* Get enable setting for restore later */
 281         ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
 282
 283         /* to set speed cltr must be disabled */
 284         dw_i2c_enable(i2c_base, false);
 285
 286         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
 287
 288         switch (config.speed_mode) {
 289         case IC_SPEED_MODE_HIGH:
 290                 cntl |= IC_CON_SPD_HS;
 291                 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt);
 292                 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt);
 293                 break;
 294         case IC_SPEED_MODE_STANDARD:
 295                 cntl |= IC_CON_SPD_SS;
 296                 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt);
 297                 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt);
 298                 break;
 299         case IC_SPEED_MODE_FAST_PLUS:
 300         case IC_SPEED_MODE_FAST:
 301         default:
 302                 cntl |= IC_CON_SPD_FS;
 303                 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt);
 304                 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt);
 305                 break;
 306         }
 307
 308         writel(cntl, &i2c_base->ic_con);
 309
 310         /* Configure SDA Hold Time if required */
 311         if (config.sda_hold)
 312                 writel(config.sda_hold, &i2c_base->ic_sda_hold);
 313
 314         /* Restore back i2c now speed set */
 315         if (ena == IC_ENABLE_0B)
 316                 dw_i2c_enable(i2c_base, true);
 317
 318         return 0;
 319 }
 320
 321 /*
 322  * i2c_setaddress - Sets the target slave address
 323  * @i2c_addr:   target i2c address
 324  *
 325  * Sets the target slave address.
 326  */
 327 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 328 {
 329         /* Disable i2c */
 330         dw_i2c_enable(i2c_base, false);
 331
 332         writel(i2c_addr, &i2c_base->ic_tar);
 333
 334         /* Enable i2c */
 335         dw_i2c_enable(i2c_base, true);
 336 }
 337
 338 /*
 339  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 340  *
 341  * Flushes the i2c RX FIFO
 342  */
 343 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 344 {
 345         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 346                 readl(&i2c_base->ic_cmd_data);
 347 }
 348
 349 /*
 350  * i2c_wait_for_bb - Waits for bus busy
 351  *
 352  * Waits for bus busy
 353  */
 354 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 355 {
 356         unsigned long start_time_bb = get_timer(0);
 357
 358         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 359                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 360
 361                 /* Evaluate timeout */
 362                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 363                         return 1;
 364         }
 365
 366         return 0;
 367 }
 368
 369 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 370                          int alen)
 371 {
 372         if (i2c_wait_for_bb(i2c_base))
 373                 return 1;
 374
 375         i2c_setaddress(i2c_base, chip);
 376         while (alen) {
 377                 alen--;
 378                 /* high byte address going out first */
 379                 writel((addr >> (alen * 8)) & 0xff,
 380                        &i2c_base->ic_cmd_data);
 381         }
 382         return 0;
 383 }
 384
 385 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 386 {
 387         ulong start_stop_det = get_timer(0);
 388
 389         while (1) {
 390                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 391                         readl(&i2c_base->ic_clr_stop_det);
 392                         break;
 393                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 394                         break;
 395                 }
 396         }
 397
 398         if (i2c_wait_for_bb(i2c_base)) {
 399                 printf("Timed out waiting for bus\n");
 400                 return 1;
 401         }
 402
 403         i2c_flush_rxfifo(i2c_base);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * i2c_read - Read from i2c memory
 410  * @chip:       target i2c address
 411  * @addr:       address to read from
 412  * @alen:
 413  * @buffer:     buffer for read data
 414  * @len:        no of bytes to be read
 415  *
 416  * Read from i2c memory.
 417  */
 418 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 419                          int alen, u8 *buffer, int len)
 420 {
 421         unsigned long start_time_rx;
 422         unsigned int active = 0;
 423
 424 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 425         /*
 426          * EEPROM chips that implement "address overflow" are ones
 427          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 428          * address and the extra bits end up in the "chip address"
 429          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 430          * four 256 byte chips.
 431          *
 432          * Note that we consider the length of the address field to
 433          * still be one byte because the extra address bits are
 434          * hidden in the chip address.
 435          */
 436         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 437         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 438
 439         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 440               addr);
 441 #endif
 442
 443         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 444                 return 1;
 445
 446         start_time_rx = get_timer(0);
 447         while (len) {
 448                 if (!active) {
 449                         /*
 450                          * Avoid writing to ic_cmd_data multiple times
 451                          * in case this loop spins too quickly and the
 452                          * ic_status RFNE bit isn't set after the first
 453                          * write. Subsequent writes to ic_cmd_data can
 454                          * trigger spurious i2c transfer.
 455                          */
 456                         if (len == 1)
 457                                 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 458                         else
 459                                 writel(IC_CMD, &i2c_base->ic_cmd_data);
 460                         active = 1;
 461                 }
 462
 463                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 464                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 465                         len--;
 466                         start_time_rx = get_timer(0);
 467                         active = 0;
 468                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 469                         return 1;
 470                 }
 471         }
 472
 473         return i2c_xfer_finish(i2c_base);
 474 }
 475
 476 /*
 477  * i2c_write - Write to i2c memory
 478  * @chip:       target i2c address
 479  * @addr:       address to read from
 480  * @alen:
 481  * @buffer:     buffer for read data
 482  * @len:        no of bytes to be read
 483  *
 484  * Write to i2c memory.
 485  */
 486 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 487                           int alen, u8 *buffer, int len)
 488 {
 489         int nb = len;
 490         unsigned long start_time_tx;
 491
 492 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 493         /*
 494          * EEPROM chips that implement "address overflow" are ones
 495          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 496          * address and the extra bits end up in the "chip address"
 497          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 498          * four 256 byte chips.
 499          *
 500          * Note that we consider the length of the address field to
 501          * still be one byte because the extra address bits are
 502          * hidden in the chip address.
 503          */
 504         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 505         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 506
 507         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 508               addr);
 509 #endif
 510
 511         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 512                 return 1;
 513
 514         start_time_tx = get_timer(0);
 515         while (len) {
 516                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 517                         if (--len == 0) {
 518                                 writel(*buffer | IC_STOP,
 519                                        &i2c_base->ic_cmd_data);
 520                         } else {
 521                                 writel(*buffer, &i2c_base->ic_cmd_data);
 522                         }
 523                         buffer++;
 524                         start_time_tx = get_timer(0);
 525
 526                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 527                                 printf("Timed out. i2c write Failed\n");
 528                                 return 1;
 529                 }
 530         }
 531
 532         return i2c_xfer_finish(i2c_base);
 533 }
 534
 535 /*
 536  * __dw_i2c_init - Init function
 537  * @speed:      required i2c speed
 538  * @slaveaddr:  slave address for the device
 539  *
 540  * Initialization function.
 541  */
 542 static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 543 {
 544         int ret;
 545
 546         /* Disable i2c */
 547         ret = dw_i2c_enable(i2c_base, false);
 548         if (ret)
 549                 return ret;
 550
 551         writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
 552                &i2c_base->ic_con);
 553         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 554         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 555         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 556 #ifndef CONFIG_DM_I2C
 557         _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK);
 558         writel(slaveaddr, &i2c_base->ic_sar);
 559 #endif
 560
 561         /* Enable i2c */
 562         ret = dw_i2c_enable(i2c_base, true);
 563         if (ret)
 564                 return ret;
 565
 566         return 0;
 567 }
 568
 569 #ifndef CONFIG_DM_I2C
 570 /*
 571  * The legacy I2C functions. These need to get removed once
 572  * all users of this driver are converted to DM.
 573  */
 574 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 575 {
 576         switch (adap->hwadapnr) {
 577 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 578         case 3:
 579                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 580 #endif
 581 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 582         case 2:
 583                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 584 #endif
 585 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 586         case 1:
 587                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 588 #endif
 589         case 0:
 590                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 591         default:
 592                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 593         }
 594
 595         return NULL;
 596 }
 597
 598 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 599                                          unsigned int speed)
 600 {
 601         adap->speed = speed;
 602         return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK);
 603 }
 604
 605 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 606 {
 607         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 608 }
 609
 610 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 611                        int alen, u8 *buffer, int len)
 612 {
 613         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 614 }
 615
 616 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 617                         int alen, u8 *buffer, int len)
 618 {
 619         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 620 }
 621
 622 /* dw_i2c_probe - Probe the i2c chip */
 623 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 624 {
 625         struct i2c_regs *i2c_base = i2c_get_base(adap);
 626         u32 tmp;
 627         int ret;
 628
 629         /*
 630          * Try to read the first location of the chip.
 631          */
 632         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 633         if (ret)
 634                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 635
 636         return ret;
 637 }
 638
 639 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 640                          dw_i2c_write, dw_i2c_set_bus_speed,
 641                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 642
 643 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 644 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 645                          dw_i2c_write, dw_i2c_set_bus_speed,
 646                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 647 #endif
 648
 649 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 650 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 651                          dw_i2c_write, dw_i2c_set_bus_speed,
 652                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 653 #endif
 654
 655 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 656 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 657                          dw_i2c_write, dw_i2c_set_bus_speed,
 658                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 659 #endif
 660
 661 #else /* CONFIG_DM_I2C */
 662 /* The DM I2C functions */
 663
 664 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 665                                int nmsgs)
 666 {
 667         struct dw_i2c *i2c = dev_get_priv(bus);
 668         int ret;
 669
 670         debug("i2c_xfer: %d messages\n", nmsgs);
 671         for (; nmsgs > 0; nmsgs--, msg++) {
 672                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 673                 if (msg->flags & I2C_M_RD) {
 674                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 675                                             msg->buf, msg->len);
 676                 } else {
 677                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 678                                              msg->buf, msg->len);
 679                 }
 680                 if (ret) {
 681                         debug("i2c_write: error sending\n");
 682                         return -EREMOTEIO;
 683                 }
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 690 {
 691         struct dw_i2c *i2c = dev_get_priv(bus);
 692         ulong rate;
 693
 694 #if CONFIG_IS_ENABLED(CLK)
 695         rate = clk_get_rate(&i2c->clk);
 696         if (IS_ERR_VALUE(rate))
 697                 return -EINVAL;
 698 #else
 699         rate = IC_CLK;
 700 #endif
 701         return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate);
 702 }
 703
 704 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 705                                      uint chip_flags)
 706 {
 707         struct dw_i2c *i2c = dev_get_priv(bus);
 708         struct i2c_regs *i2c_base = i2c->regs;
 709         u32 tmp;
 710         int ret;
 711
 712         /* Try to read the first location of the chip */
 713         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 714         if (ret)
 715                 __dw_i2c_init(i2c_base, 0, 0);
 716
 717         return ret;
 718 }
 719
 720 int designware_i2c_ofdata_to_platdata(struct udevice *bus)
 721 {
 722         struct dw_i2c *priv = dev_get_priv(bus);
 723         int ret;
 724
 725         if (!priv->regs)
 726                 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
 727         dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns);
 728         dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns);
 729         dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns);
 730
 731         ret = reset_get_bulk(bus, &priv->resets);
 732         if (ret)
 733                 dev_warn(bus, "Can't get reset: %d\n", ret);
 734         else
 735                 reset_deassert_bulk(&priv->resets);
 736
 737 #if CONFIG_IS_ENABLED(CLK)
 738         ret = clk_get_by_index(bus, 0, &priv->clk);
 739         if (ret)
 740                 return ret;
 741
 742         ret = clk_enable(&priv->clk);
 743         if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
 744                 clk_free(&priv->clk);
 745                 dev_err(bus, "failed to enable clock\n");
 746                 return ret;
 747         }
 748 #endif
 749
 750         return 0;
 751 }
 752
 753 int designware_i2c_probe(struct udevice *bus)
 754 {
 755         struct dw_i2c *priv = dev_get_priv(bus);
 756
 757         return __dw_i2c_init(priv->regs, 0, 0);
 758 }
 759
 760 int designware_i2c_remove(struct udevice *dev)
 761 {
 762         struct dw_i2c *priv = dev_get_priv(dev);
 763
 764 #if CONFIG_IS_ENABLED(CLK)
 765         clk_disable(&priv->clk);
 766         clk_free(&priv->clk);
 767 #endif
 768
 769         return reset_release_bulk(&priv->resets);
 770 }
 771
 772 const struct dm_i2c_ops designware_i2c_ops = {
 773         .xfer           = designware_i2c_xfer,
 774         .probe_chip     = designware_i2c_probe_chip,
 775         .set_bus_speed  = designware_i2c_set_bus_speed,
 776 };
 777
 778 static const struct udevice_id designware_i2c_ids[] = {
 779         { .compatible = "snps,designware-i2c" },
 780         { }
 781 };
 782
 783 U_BOOT_DRIVER(i2c_designware) = {
 784         .name   = "i2c_designware",
 785         .id     = UCLASS_I2C,
 786         .of_match = designware_i2c_ids,
 787         .ofdata_to_platdata = designware_i2c_ofdata_to_platdata,
 788         .probe  = designware_i2c_probe,
 789         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 790         .remove = designware_i2c_remove,
 791         .flags  = DM_FLAG_OS_PREPARE,
 792         .ops    = &designware_i2c_ops,
 793 };
 794
 795 #endif /* CONFIG_DM_I2C */