board/freescale/ls1021atwr/ls1021atwr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  * Copyright 2019 NXP
   5  */
   6
   7 #include <common.h>
   8 #include <clock_legacy.h>
   9 #include <fdt_support.h>
  10 #include <i2c.h>
  11 #include <init.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/immap_ls102xa.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/ls102xa_devdis.h>
  17 #include <asm/arch/ls102xa_soc.h>
  18 #include <hwconfig.h>
  19 #include <mmc.h>
  20 #include <fsl_csu.h>
  21 #include <fsl_ifc.h>
  22 #include <fsl_immap.h>
  23 #include <netdev.h>
  24 #include <fsl_mdio.h>
  25 #include <tsec.h>
  26 #include <fsl_sec.h>
  27 #include <fsl_devdis.h>
  28 #include <spl.h>
  29 #include "../common/sleep.h"
  30 #ifdef CONFIG_U_QE
  31 #include <fsl_qe.h>
  32 #endif
  33 #include <fsl_validate.h>
  34
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define VERSION_MASK            0x00FF
  39 #define BANK_MASK               0x0001
  40 #define CONFIG_RESET            0x1
  41 #define INIT_RESET              0x1
  42
  43 #define CPLD_SET_MUX_SERDES     0x20
  44 #define CPLD_SET_BOOT_BANK      0x40
  45
  46 #define BOOT_FROM_UPPER_BANK    0x0
  47 #define BOOT_FROM_LOWER_BANK    0x1
  48
  49 #define LANEB_SATA              (0x01)
  50 #define LANEB_SGMII1            (0x02)
  51 #define LANEC_SGMII1            (0x04)
  52 #define LANEC_PCIEX1            (0x08)
  53 #define LANED_PCIEX2            (0x10)
  54 #define LANED_SGMII2            (0x20)
  55
  56 #define MASK_LANE_B             0x1
  57 #define MASK_LANE_C             0x2
  58 #define MASK_LANE_D             0x4
  59 #define MASK_SGMII              0x8
  60
  61 #define KEEP_STATUS             0x0
  62 #define NEED_RESET              0x1
  63
  64 #define SOFT_MUX_ON_I2C3_IFC    0x2
  65 #define SOFT_MUX_ON_CAN3_USB2   0x8
  66 #define SOFT_MUX_ON_QE_LCD      0x10
  67
  68 #define PIN_I2C3_IFC_MUX_I2C3   0x0
  69 #define PIN_I2C3_IFC_MUX_IFC    0x1
  70 #define PIN_CAN3_USB2_MUX_USB2  0x0
  71 #define PIN_CAN3_USB2_MUX_CAN3  0x1
  72 #define PIN_QE_LCD_MUX_LCD      0x0
  73 #define PIN_QE_LCD_MUX_QE       0x1
  74
  75 struct cpld_data {
  76         u8 cpld_ver;            /* cpld revision */
  77         u8 cpld_ver_sub;        /* cpld sub revision */
  78         u8 pcba_ver;            /* pcb revision number */
  79         u8 system_rst;          /* reset system by cpld */
  80         u8 soft_mux_on;         /* CPLD override physical switches Enable */
  81         u8 cfg_rcw_src1;        /* Reset config word 1 */
  82         u8 cfg_rcw_src2;        /* Reset config word 2 */
  83         u8 vbank;               /* Flash bank selection Control */
  84         u8 gpio;                /* GPIO for TWR-ELEV */
  85         u8 i2c3_ifc_mux;
  86         u8 mux_spi2;
  87         u8 can3_usb2_mux;       /* CAN3 and USB2 Selection */
  88         u8 qe_lcd_mux;          /* QE and LCD Selection */
  89         u8 serdes_mux;          /* Multiplexed pins for SerDes Lanes */
  90         u8 global_rst;          /* reset with init CPLD reg to default */
  91         u8 rev1;                /* Reserved */
  92         u8 rev2;                /* Reserved */
  93 };
  94
  95 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  96 static void cpld_show(void)
  97 {
  98         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  99
 100         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\nVBank: %d\n",
 101                in_8(&cpld_data->cpld_ver) & VERSION_MASK,
 102                in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK,
 103                in_8(&cpld_data->pcba_ver) & VERSION_MASK,
 104                in_8(&cpld_data->vbank) & BANK_MASK);
 105
 106 #ifdef CONFIG_DEBUG
 107         printf("soft_mux_on =%x\n",
 108                in_8(&cpld_data->soft_mux_on));
 109         printf("cfg_rcw_src1 =%x\n",
 110                in_8(&cpld_data->cfg_rcw_src1));
 111         printf("cfg_rcw_src2 =%x\n",
 112                in_8(&cpld_data->cfg_rcw_src2));
 113         printf("vbank =%x\n",
 114                in_8(&cpld_data->vbank));
 115         printf("gpio =%x\n",
 116                in_8(&cpld_data->gpio));
 117         printf("i2c3_ifc_mux =%x\n",
 118                in_8(&cpld_data->i2c3_ifc_mux));
 119         printf("mux_spi2 =%x\n",
 120                in_8(&cpld_data->mux_spi2));
 121         printf("can3_usb2_mux =%x\n",
 122                in_8(&cpld_data->can3_usb2_mux));
 123         printf("qe_lcd_mux =%x\n",
 124                in_8(&cpld_data->qe_lcd_mux));
 125         printf("serdes_mux =%x\n",
 126                in_8(&cpld_data->serdes_mux));
 127 #endif
 128 }
 129 #endif
 130
 131 int checkboard(void)
 132 {
 133         puts("Board: LS1021ATWR\n");
 134 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 135         cpld_show();
 136 #endif
 137
 138         return 0;
 139 }
 140
 141 void ddrmc_init(void)
 142 {
 143         struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
 144         u32 temp_sdram_cfg, tmp;
 145
 146         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
 147
 148         out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
 149         out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
 150
 151         out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
 152         out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
 153         out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
 154         out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
 155         out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
 156         out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
 157
 158 #ifdef CONFIG_DEEP_SLEEP
 159         if (is_warm_boot()) {
 160                 out_be32(&ddr->sdram_cfg_2,
 161                          DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
 162                 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
 163                 out_be32(&ddr->init_ext_addr, (1 << 31));
 164
 165                 /* DRAM VRef will not be trained */
 166                 out_be32(&ddr->ddr_cdr2,
 167                          DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
 168         } else
 169 #endif
 170         {
 171                 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
 172                 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
 173         }
 174
 175         out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
 176         out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
 177
 178         out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
 179
 180         out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
 181
 182         out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
 183         out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
 184
 185         out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
 186
 187         out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
 188         out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
 189
 190         out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
 191
 192         /* DDR erratum A-009942 */
 193         tmp = in_be32(&ddr->debug[28]);
 194         out_be32(&ddr->debug[28], tmp | 0x0070006f);
 195
 196         udelay(1);
 197
 198 #ifdef CONFIG_DEEP_SLEEP
 199         if (is_warm_boot()) {
 200                 /* enter self-refresh */
 201                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 202                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 203                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 204
 205                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
 206         } else
 207 #endif
 208                 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
 209
 210         out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
 211
 212 #ifdef CONFIG_DEEP_SLEEP
 213         if (is_warm_boot()) {
 214                 /* exit self-refresh */
 215                 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
 216                 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
 217                 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
 218         }
 219 #endif
 220 }
 221
 222 int dram_init(void)
 223 {
 224 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 225         ddrmc_init();
 226 #endif
 227
 228         erratum_a008850_post();
 229
 230         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 231
 232 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
 233         fsl_dp_resume();
 234 #endif
 235
 236         return 0;
 237 }
 238
 239 int board_eth_init(bd_t *bis)
 240 {
 241         return pci_eth_init(bis);
 242 }
 243
 244 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 245 static void convert_serdes_mux(int type, int need_reset)
 246 {
 247         char current_serdes;
 248         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 249
 250         current_serdes = cpld_data->serdes_mux;
 251
 252         switch (type) {
 253         case LANEB_SATA:
 254                 current_serdes &= ~MASK_LANE_B;
 255                 break;
 256         case LANEB_SGMII1:
 257                 current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 258                 break;
 259         case LANEC_SGMII1:
 260                 current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C);
 261                 break;
 262         case LANED_SGMII2:
 263                 current_serdes |= MASK_LANE_D;
 264                 break;
 265         case LANEC_PCIEX1:
 266                 current_serdes |= MASK_LANE_C;
 267                 break;
 268         case (LANED_PCIEX2 | LANEC_PCIEX1):
 269                 current_serdes |= MASK_LANE_C;
 270                 current_serdes &= ~MASK_LANE_D;
 271                 break;
 272         default:
 273                 printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type);
 274                 return;
 275         }
 276
 277         cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES;
 278         cpld_data->serdes_mux = current_serdes;
 279
 280         if (need_reset == 1) {
 281                 printf("Reset board to enable configuration\n");
 282                 cpld_data->system_rst = CONFIG_RESET;
 283         }
 284 }
 285
 286 int config_serdes_mux(void)
 287 {
 288         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 289         u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
 290
 291         protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
 292         switch (protocol) {
 293         case 0x10:
 294                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 295                 convert_serdes_mux(LANED_PCIEX2 |
 296                                 LANEC_PCIEX1, KEEP_STATUS);
 297                 break;
 298         case 0x20:
 299                 convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS);
 300                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 301                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 302                 break;
 303         case 0x30:
 304                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 305                 convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS);
 306                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 307                 break;
 308         case 0x70:
 309                 convert_serdes_mux(LANEB_SATA, KEEP_STATUS);
 310                 convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS);
 311                 convert_serdes_mux(LANED_SGMII2, KEEP_STATUS);
 312                 break;
 313         }
 314
 315         return 0;
 316 }
 317 #endif
 318
 319 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 320 int config_board_mux(void)
 321 {
 322         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 323         int conflict_flag;
 324
 325         conflict_flag = 0;
 326         if (hwconfig("i2c3")) {
 327                 conflict_flag++;
 328                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 329                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_I2C3;
 330         }
 331
 332         if (hwconfig("ifc")) {
 333                 conflict_flag++;
 334                 /* some signals can not enable simultaneous*/
 335                 if (conflict_flag > 1)
 336                         goto conflict;
 337                 cpld_data->soft_mux_on |= SOFT_MUX_ON_I2C3_IFC;
 338                 cpld_data->i2c3_ifc_mux = PIN_I2C3_IFC_MUX_IFC;
 339         }
 340
 341         conflict_flag = 0;
 342         if (hwconfig("usb2")) {
 343                 conflict_flag++;
 344                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 345                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_USB2;
 346         }
 347
 348         if (hwconfig("can3")) {
 349                 conflict_flag++;
 350                 /* some signals can not enable simultaneous*/
 351                 if (conflict_flag > 1)
 352                         goto conflict;
 353                 cpld_data->soft_mux_on |= SOFT_MUX_ON_CAN3_USB2;
 354                 cpld_data->can3_usb2_mux = PIN_CAN3_USB2_MUX_CAN3;
 355         }
 356
 357         conflict_flag = 0;
 358         if (hwconfig("lcd")) {
 359                 conflict_flag++;
 360                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 361                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_LCD;
 362         }
 363
 364         if (hwconfig("qe")) {
 365                 conflict_flag++;
 366                 /* some signals can not enable simultaneous*/
 367                 if (conflict_flag > 1)
 368                         goto conflict;
 369                 cpld_data->soft_mux_on |= SOFT_MUX_ON_QE_LCD;
 370                 cpld_data->qe_lcd_mux = PIN_QE_LCD_MUX_QE;
 371         }
 372
 373         return 0;
 374
 375 conflict:
 376         printf("WARNING: pin conflict! MUX setting may failed!\n");
 377         return 0;
 378 }
 379 #endif
 380
 381 int board_early_init_f(void)
 382 {
 383         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 384
 385 #ifdef CONFIG_TSEC_ENET
 386         /* clear BD & FR bits for BE BD's and frame data */
 387         clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 388         out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 389 #endif
 390
 391 #ifdef CONFIG_FSL_IFC
 392         init_early_memctl_regs();
 393 #endif
 394
 395         arch_soc_init();
 396
 397 #if defined(CONFIG_DEEP_SLEEP)
 398         if (is_warm_boot()) {
 399                 timer_init();
 400                 dram_init();
 401         }
 402 #endif
 403
 404         return 0;
 405 }
 406
 407 #ifdef CONFIG_SPL_BUILD
 408 void board_init_f(ulong dummy)
 409 {
 410         void (*second_uboot)(void);
 411
 412         /* Clear the BSS */
 413         memset(__bss_start, 0, __bss_end - __bss_start);
 414
 415         get_clocks();
 416
 417 #if defined(CONFIG_DEEP_SLEEP)
 418         if (is_warm_boot())
 419                 fsl_dp_disable_console();
 420 #endif
 421
 422         preloader_console_init();
 423
 424         timer_init();
 425         dram_init();
 426
 427         /* Allow OCRAM access permission as R/W */
 428 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 429         enable_layerscape_ns_access();
 430 #endif
 431
 432         /*
 433          * if it is woken up from deep sleep, then jump to second
 434          * stage uboot and continue executing without recopying
 435          * it from SD since it has already been reserved in memeory
 436          * in last boot.
 437          */
 438         if (is_warm_boot()) {
 439                 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
 440                 second_uboot();
 441         }
 442
 443         board_init_r(NULL, 0);
 444 }
 445 #endif
 446
 447 #ifdef CONFIG_DEEP_SLEEP
 448 /* program the regulator (MC34VR500) to support deep sleep */
 449 void ls1twr_program_regulator(void)
 450 {
 451         u8 i2c_device_id;
 452
 453 #define LS1TWR_I2C_BUS_MC34VR500        1
 454 #define MC34VR500_ADDR                  0x8
 455 #define MC34VR500_DEVICEID              0x4
 456 #define MC34VR500_DEVICEID_MASK         0x0f
 457 #ifdef CONFIG_DM_I2C
 458         struct udevice *dev;
 459         int ret;
 460
 461         ret = i2c_get_chip_for_busnum(LS1TWR_I2C_BUS_MC34VR500, MC34VR500_ADDR,
 462                                       1, &dev);
 463         if (ret) {
 464                 printf("%s: Cannot find udev for a bus %d\n", __func__,
 465                        LS1TWR_I2C_BUS_MC34VR500);
 466                 return;
 467         }
 468         i2c_device_id = dm_i2c_reg_read(dev, 0x0) &
 469                                         MC34VR500_DEVICEID_MASK;
 470         if (i2c_device_id != MC34VR500_DEVICEID) {
 471                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 472                 return;
 473         }
 474
 475         dm_i2c_reg_write(dev, 0x31, 0x4);
 476         dm_i2c_reg_write(dev, 0x4d, 0x4);
 477         dm_i2c_reg_write(dev, 0x6d, 0x38);
 478         dm_i2c_reg_write(dev, 0x6f, 0x37);
 479         dm_i2c_reg_write(dev, 0x71, 0x30);
 480 #else
 481         unsigned int i2c_bus;
 482         i2c_bus = i2c_get_bus_num();
 483         i2c_set_bus_num(LS1TWR_I2C_BUS_MC34VR500);
 484         i2c_device_id = i2c_reg_read(MC34VR500_ADDR, 0x0) &
 485                                         MC34VR500_DEVICEID_MASK;
 486         if (i2c_device_id != MC34VR500_DEVICEID) {
 487                 printf("The regulator (MC34VR500) does not exist. The device does not support deep sleep.\n");
 488                 return;
 489         }
 490
 491         i2c_reg_write(MC34VR500_ADDR, 0x31, 0x4);
 492         i2c_reg_write(MC34VR500_ADDR, 0x4d, 0x4);
 493         i2c_reg_write(MC34VR500_ADDR, 0x6d, 0x38);
 494         i2c_reg_write(MC34VR500_ADDR, 0x6f, 0x37);
 495         i2c_reg_write(MC34VR500_ADDR, 0x71, 0x30);
 496
 497         i2c_set_bus_num(i2c_bus);
 498 #endif
 499 }
 500 #endif
 501
 502 int board_init(void)
 503 {
 504 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
 505         erratum_a010315();
 506 #endif
 507
 508 #ifndef CONFIG_SYS_FSL_NO_SERDES
 509         fsl_serdes_init();
 510 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 511         config_serdes_mux();
 512 #endif
 513 #endif
 514
 515         ls102xa_smmu_stream_id_init();
 516
 517 #ifdef CONFIG_U_QE
 518         u_qe_init();
 519 #endif
 520
 521 #ifdef CONFIG_DEEP_SLEEP
 522         ls1twr_program_regulator();
 523 #endif
 524         return 0;
 525 }
 526
 527 #if defined(CONFIG_SPL_BUILD)
 528 void spl_board_init(void)
 529 {
 530         ls102xa_smmu_stream_id_init();
 531 }
 532 #endif
 533
 534 #ifdef CONFIG_BOARD_LATE_INIT
 535 int board_late_init(void)
 536 {
 537 #ifdef CONFIG_CHAIN_OF_TRUST
 538         fsl_setenv_chain_of_trust();
 539 #endif
 540
 541         return 0;
 542 }
 543 #endif
 544
 545 #if defined(CONFIG_MISC_INIT_R)
 546 int misc_init_r(void)
 547 {
 548 #ifdef CONFIG_FSL_DEVICE_DISABLE
 549         device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
 550 #endif
 551 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 552         config_board_mux();
 553 #endif
 554
 555 #ifdef CONFIG_FSL_CAAM
 556         return sec_init();
 557 #endif
 558 }
 559 #endif
 560
 561 #if defined(CONFIG_DEEP_SLEEP)
 562 void board_sleep_prepare(void)
 563 {
 564 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 565         enable_layerscape_ns_access();
 566 #endif
 567 }
 568 #endif
 569
 570 int ft_board_setup(void *blob, bd_t *bd)
 571 {
 572         ft_cpu_setup(blob, bd);
 573
 574 #ifdef CONFIG_PCI
 575         ft_pci_setup(blob, bd);
 576 #endif
 577
 578         return 0;
 579 }
 580
 581 u8 flash_read8(void *addr)
 582 {
 583         return __raw_readb(addr + 1);
 584 }
 585
 586 void flash_write16(u16 val, void *addr)
 587 {
 588         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 589
 590         __raw_writew(shftval, addr);
 591 }
 592
 593 u16 flash_read16(void *addr)
 594 {
 595         u16 val = __raw_readw(addr);
 596
 597         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 598 }
 599
 600 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) \
 601         && !defined(CONFIG_SPL_BUILD)
 602 static void convert_flash_bank(char bank)
 603 {
 604         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 605
 606         printf("Now switch to boot from flash bank %d.\n", bank);
 607         cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK;
 608         cpld_data->vbank = bank;
 609
 610         printf("Reset board to enable configuration.\n");
 611         cpld_data->system_rst = CONFIG_RESET;
 612 }
 613
 614 static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 615                           char * const argv[])
 616 {
 617         if (argc != 2)
 618                 return CMD_RET_USAGE;
 619         if (strcmp(argv[1], "0") == 0)
 620                 convert_flash_bank(BOOT_FROM_UPPER_BANK);
 621         else if (strcmp(argv[1], "1") == 0)
 622                 convert_flash_bank(BOOT_FROM_LOWER_BANK);
 623         else
 624                 return CMD_RET_USAGE;
 625
 626         return 0;
 627 }
 628
 629 U_BOOT_CMD(
 630         boot_bank, 2, 0, flash_bank_cmd,
 631         "Flash bank Selection Control",
 632         "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)"
 633 );
 634
 635 static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 636                           char * const argv[])
 637 {
 638         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 639
 640         if (argc > 2)
 641                 return CMD_RET_USAGE;
 642         if ((argc == 1) || (strcmp(argv[1], "conf") == 0))
 643                 cpld_data->system_rst = CONFIG_RESET;
 644         else if (strcmp(argv[1], "init") == 0)
 645                 cpld_data->global_rst = INIT_RESET;
 646         else
 647                 return CMD_RET_USAGE;
 648
 649         return 0;
 650 }
 651
 652 U_BOOT_CMD(
 653         cpld_reset, 2, 0, cpld_reset_cmd,
 654         "Reset via CPLD",
 655         "conf\n"
 656         "       -reset with current CPLD configuration\n"
 657         "init\n"
 658         "       -reset and initial CPLD configuration with default value"
 659
 660 );
 661
 662 static void print_serdes_mux(void)
 663 {
 664         char current_serdes;
 665         struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
 666
 667         current_serdes = cpld_data->serdes_mux;
 668
 669         printf("Serdes Lane B: ");
 670         if ((current_serdes & MASK_LANE_B) == 0)
 671                 printf("SATA,\n");
 672         else
 673                 printf("SGMII 1,\n");
 674
 675         printf("Serdes Lane C: ");
 676         if ((current_serdes & MASK_LANE_C) == 0)
 677                 printf("SGMII 1,\n");
 678         else
 679                 printf("PCIe,\n");
 680
 681         printf("Serdes Lane D: ");
 682         if ((current_serdes & MASK_LANE_D) == 0)
 683                 printf("PCIe,\n");
 684         else
 685                 printf("SGMII 2,\n");
 686
 687         printf("SGMII 1 is on lane ");
 688         if ((current_serdes & MASK_SGMII) == 0)
 689                 printf("C.\n");
 690         else
 691                 printf("B.\n");
 692 }
 693
 694 static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
 695                           char * const argv[])
 696 {
 697         if (argc != 2)
 698                 return CMD_RET_USAGE;
 699         if (strcmp(argv[1], "sata") == 0) {
 700                 printf("Set serdes lane B to SATA.\n");
 701                 convert_serdes_mux(LANEB_SATA, NEED_RESET);
 702         } else if (strcmp(argv[1], "sgmii1b") == 0) {
 703                 printf("Set serdes lane B to SGMII 1.\n");
 704                 convert_serdes_mux(LANEB_SGMII1, NEED_RESET);
 705         } else if (strcmp(argv[1], "sgmii1c") == 0) {
 706                 printf("Set serdes lane C to SGMII 1.\n");
 707                 convert_serdes_mux(LANEC_SGMII1, NEED_RESET);
 708         } else if (strcmp(argv[1], "sgmii2") == 0) {
 709                 printf("Set serdes lane D to SGMII 2.\n");
 710                 convert_serdes_mux(LANED_SGMII2, NEED_RESET);
 711         } else if (strcmp(argv[1], "pciex1") == 0) {
 712                 printf("Set serdes lane C to PCIe X1.\n");
 713                 convert_serdes_mux(LANEC_PCIEX1, NEED_RESET);
 714         } else if (strcmp(argv[1], "pciex2") == 0) {
 715                 printf("Set serdes lane C & lane D to PCIe X2.\n");
 716                 convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET);
 717         } else if (strcmp(argv[1], "show") == 0) {
 718                 print_serdes_mux();
 719         } else {
 720                 return CMD_RET_USAGE;
 721         }
 722
 723         return 0;
 724 }
 725
 726 U_BOOT_CMD(
 727         lane_bank, 2, 0, serdes_mux_cmd,
 728         "Multiplexed function setting for SerDes Lanes",
 729         "sata\n"
 730         "       -change lane B to sata\n"
 731         "lane_bank sgmii1b\n"
 732         "       -change lane B to SGMII1\n"
 733         "lane_bank sgmii1c\n"
 734         "       -change lane C to SGMII1\n"
 735         "lane_bank sgmii2\n"
 736         "       -change lane D to SGMII2\n"
 737         "lane_bank pciex1\n"
 738         "       -change lane C to PCIeX1\n"
 739         "lane_bank pciex2\n"
 740         "       -change lane C & lane D to PCIeX2\n"
 741         "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
 742 );
 743 #endif