drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <log.h>
  11 #include <asm/cache.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/omap.h>
  14 #include <malloc.h>
  15 #include <spi.h>
  16 #include <spi-mem.h>
  17 #include <dm.h>
  18 #include <asm/gpio.h>
  19 #include <asm/omap_gpio.h>
  20 #include <asm/omap_common.h>
  21 #include <asm/ti-common/ti-edma3.h>
  22 #include <linux/bitops.h>
  23 #include <linux/err.h>
  24 #include <linux/kernel.h>
  25 #include <regmap.h>
  26 #include <syscon.h>
  27
  28 DECLARE_GLOBAL_DATA_PTR;
  29
  30 /* ti qpsi register bit masks */
  31 #define QSPI_TIMEOUT                    2000000
  32 #define QSPI_FCLK                       192000000
  33 #define QSPI_DRA7XX_FCLK                76800000
  34 #define QSPI_WLEN_MAX_BITS              128
  35 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  36 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  37 /* clock control */
  38 #define QSPI_CLK_EN                     BIT(31)
  39 #define QSPI_CLK_DIV_MAX                0xffff
  40 /* command */
  41 #define QSPI_EN_CS(n)                   (n << 28)
  42 #define QSPI_WLEN(n)                    ((n-1) << 19)
  43 #define QSPI_3_PIN                      BIT(18)
  44 #define QSPI_RD_SNGL                    BIT(16)
  45 #define QSPI_WR_SNGL                    (2 << 16)
  46 #define QSPI_INVAL                      (4 << 16)
  47 #define QSPI_RD_QUAD                    (7 << 16)
  48 /* device control */
  49 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  50 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  51 #define QSPI_CKPOL(n)                   (1 << (n*8))
  52 /* status */
  53 #define QSPI_WC                         BIT(1)
  54 #define QSPI_BUSY                       BIT(0)
  55 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  56 #define QSPI_XFER_DONE                  QSPI_WC
  57 #define MM_SWITCH                       0x01
  58 #define MEM_CS(cs)                      ((cs + 1) << 8)
  59 #define MEM_CS_UNSELECT                 0xfffff8ff
  60
  61 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  62 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  63 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  64 #define QSPI_SETUP0_ADDR_SHIFT          (8)
  65 #define QSPI_SETUP0_DBITS_SHIFT         (10)
  66
  67 #define TI_QSPI_SETUP_REG(priv, cs)     (&(priv)->base->setup0 + (cs))
  68
  69 /* ti qspi register set */
  70 struct ti_qspi_regs {
  71         u32 pid;
  72         u32 pad0[3];
  73         u32 sysconfig;
  74         u32 pad1[3];
  75         u32 int_stat_raw;
  76         u32 int_stat_en;
  77         u32 int_en_set;
  78         u32 int_en_ctlr;
  79         u32 intc_eoi;
  80         u32 pad2[3];
  81         u32 clk_ctrl;
  82         u32 dc;
  83         u32 cmd;
  84         u32 status;
  85         u32 data;
  86         u32 setup0;
  87         u32 setup1;
  88         u32 setup2;
  89         u32 setup3;
  90         u32 memswitch;
  91         u32 data1;
  92         u32 data2;
  93         u32 data3;
  94 };
  95
  96 /* ti qspi priv */
  97 struct ti_qspi_priv {
  98         void *memory_map;
  99         size_t mmap_size;
 100         uint max_hz;
 101         u32 num_cs;
 102         struct ti_qspi_regs *base;
 103         void *ctrl_mod_mmap;
 104         ulong fclk;
 105         unsigned int mode;
 106         u32 cmd;
 107         u32 dc;
 108 };
 109
 110 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 111 {
 112         struct ti_qspi_priv *priv = dev_get_priv(bus);
 113         uint clk_div;
 114
 115         if (!hz)
 116                 clk_div = 0;
 117         else
 118                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 119
 120         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 121         if (clk_div > QSPI_CLK_DIV_MAX)
 122                 clk_div = QSPI_CLK_DIV_MAX;
 123
 124         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 125
 126         /* disable SCLK */
 127         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 128                &priv->base->clk_ctrl);
 129         /* enable SCLK and program the clk divider */
 130         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 131
 132         return 0;
 133 }
 134
 135 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 136 {
 137         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 138         /* dummy readl to ensure bus sync */
 139         readl(&priv->base->cmd);
 140 }
 141
 142 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 143 {
 144         u32 val;
 145
 146         val = readl(ctrl_mod_mmap);
 147         if (enable)
 148                 val |= MEM_CS(cs);
 149         else
 150                 val &= MEM_CS_UNSELECT;
 151         writel(val, ctrl_mod_mmap);
 152 }
 153
 154 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 155                         const void *dout, void *din, unsigned long flags)
 156 {
 157         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 158         struct ti_qspi_priv *priv;
 159         struct udevice *bus;
 160         uint words = bitlen >> 3; /* fixed 8-bit word length */
 161         const uchar *txp = dout;
 162         uchar *rxp = din;
 163         uint status;
 164         int timeout;
 165         unsigned int cs = slave->cs;
 166
 167         bus = dev->parent;
 168         priv = dev_get_priv(bus);
 169
 170         if (cs > priv->num_cs) {
 171                 debug("invalid qspi chip select\n");
 172                 return -EINVAL;
 173         }
 174
 175         if (bitlen == 0)
 176                 return -1;
 177
 178         if (bitlen % 8) {
 179                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 180                 return -1;
 181         }
 182
 183         /* Setup command reg */
 184         priv->cmd = 0;
 185         priv->cmd |= QSPI_WLEN(8);
 186         priv->cmd |= QSPI_EN_CS(cs);
 187         if (priv->mode & SPI_3WIRE)
 188                 priv->cmd |= QSPI_3_PIN;
 189         priv->cmd |= 0xfff;
 190
 191         while (words) {
 192                 u8 xfer_len = 0;
 193
 194                 if (txp) {
 195                         u32 cmd = priv->cmd;
 196
 197                         if (words >= QSPI_WLEN_MAX_BYTES) {
 198                                 u32 *txbuf = (u32 *)txp;
 199                                 u32 data;
 200
 201                                 data = cpu_to_be32(*txbuf++);
 202                                 writel(data, &priv->base->data3);
 203                                 data = cpu_to_be32(*txbuf++);
 204                                 writel(data, &priv->base->data2);
 205                                 data = cpu_to_be32(*txbuf++);
 206                                 writel(data, &priv->base->data1);
 207                                 data = cpu_to_be32(*txbuf++);
 208                                 writel(data, &priv->base->data);
 209                                 cmd &= ~QSPI_WLEN_MASK;
 210                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 211                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 212                         } else {
 213                                 writeb(*txp, &priv->base->data);
 214                                 xfer_len = 1;
 215                         }
 216                         debug("tx cmd %08x dc %08x\n",
 217                               cmd | QSPI_WR_SNGL, priv->dc);
 218                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 219                         status = readl(&priv->base->status);
 220                         timeout = QSPI_TIMEOUT;
 221                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 222                                 if (--timeout < 0) {
 223                                         printf("spi_xfer: TX timeout!\n");
 224                                         return -1;
 225                                 }
 226                                 status = readl(&priv->base->status);
 227                         }
 228                         txp += xfer_len;
 229                         debug("tx done, status %08x\n", status);
 230                 }
 231                 if (rxp) {
 232                         debug("rx cmd %08x dc %08x\n",
 233                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 234                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 235                         status = readl(&priv->base->status);
 236                         timeout = QSPI_TIMEOUT;
 237                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 238                                 if (--timeout < 0) {
 239                                         printf("spi_xfer: RX timeout!\n");
 240                                         return -1;
 241                                 }
 242                                 status = readl(&priv->base->status);
 243                         }
 244                         *rxp++ = readl(&priv->base->data);
 245                         xfer_len = 1;
 246                         debug("rx done, status %08x, read %02x\n",
 247                               status, *(rxp-1));
 248                 }
 249                 words -= xfer_len;
 250         }
 251
 252         /* Terminate frame */
 253         if (flags & SPI_XFER_END)
 254                 ti_qspi_cs_deactivate(priv);
 255
 256         return 0;
 257 }
 258
 259 /* TODO: control from sf layer to here through dm-spi */
 260 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 261 {
 262 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 263         unsigned int                    addr = (unsigned int) (data);
 264         unsigned int                    edma_slot_num = 1;
 265
 266         /* Invalidate the area, so no writeback into the RAM races with DMA */
 267         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 268
 269         /* enable edma3 clocks */
 270         enable_edma3_clocks();
 271
 272         /* Call edma3 api to do actual DMA transfer     */
 273         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 274
 275         /* disable edma3 clocks */
 276         disable_edma3_clocks();
 277 #else
 278         memcpy_fromio(data, offset, len);
 279 #endif
 280
 281         *((unsigned int *)offset) += len;
 282 }
 283
 284 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
 285                                     u8 opcode, u8 data_nbits, u8 addr_width,
 286                                     u8 dummy_bytes)
 287 {
 288         u32 memval = opcode;
 289
 290         switch (data_nbits) {
 291         case 4:
 292                 memval |= QSPI_SETUP0_READ_QUAD;
 293                 break;
 294         case 2:
 295                 memval |= QSPI_SETUP0_READ_DUAL;
 296                 break;
 297         default:
 298                 memval |= QSPI_SETUP0_READ_NORMAL;
 299                 break;
 300         }
 301
 302         memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
 303                    dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
 304
 305         writel(memval, TI_QSPI_SETUP_REG(priv, cs));
 306 }
 307
 308 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 309 {
 310         struct ti_qspi_priv *priv = dev_get_priv(bus);
 311
 312         priv->dc = 0;
 313         if (mode & SPI_CPHA)
 314                 priv->dc |= QSPI_CKPHA(0);
 315         if (mode & SPI_CPOL)
 316                 priv->dc |= QSPI_CKPOL(0);
 317         if (mode & SPI_CS_HIGH)
 318                 priv->dc |= QSPI_CSPOL(0);
 319
 320         return 0;
 321 }
 322
 323 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
 324                                const struct spi_mem_op *op)
 325 {
 326         struct dm_spi_slave_platdata *slave_plat;
 327         struct ti_qspi_priv *priv;
 328         struct udevice *bus;
 329         u32 from = 0;
 330         int ret = 0;
 331
 332         bus = slave->dev->parent;
 333         priv = dev_get_priv(bus);
 334         slave_plat = dev_get_parent_platdata(slave->dev);
 335
 336         /* Only optimize read path. */
 337         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 338             !op->addr.nbytes || op->addr.nbytes > 4)
 339                 return -ENOTSUPP;
 340
 341         /* Address exceeds MMIO window size, fall back to regular mode. */
 342         from = op->addr.val;
 343         if (from + op->data.nbytes > priv->mmap_size)
 344                 return -ENOTSUPP;
 345
 346         ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
 347                                 op->data.buswidth, op->addr.nbytes,
 348                                 op->dummy.nbytes);
 349
 350         ti_qspi_copy_mmap((void *)op->data.buf.in,
 351                           (void *)priv->memory_map + from, op->data.nbytes);
 352
 353         return ret;
 354 }
 355
 356 static int ti_qspi_claim_bus(struct udevice *dev)
 357 {
 358         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 359         struct ti_qspi_priv *priv;
 360         struct udevice *bus;
 361
 362         bus = dev->parent;
 363         priv = dev_get_priv(bus);
 364
 365         if (slave_plat->cs > priv->num_cs) {
 366                 debug("invalid qspi chip select\n");
 367                 return -EINVAL;
 368         }
 369
 370         writel(MM_SWITCH, &priv->base->memswitch);
 371         if (priv->ctrl_mod_mmap)
 372                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 373                                        slave_plat->cs, true);
 374
 375         writel(priv->dc, &priv->base->dc);
 376         writel(0, &priv->base->cmd);
 377         writel(0, &priv->base->data);
 378
 379         priv->dc <<= slave_plat->cs * 8;
 380         writel(priv->dc, &priv->base->dc);
 381
 382         return 0;
 383 }
 384
 385 static int ti_qspi_release_bus(struct udevice *dev)
 386 {
 387         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 388         struct ti_qspi_priv *priv;
 389         struct udevice *bus;
 390
 391         bus = dev->parent;
 392         priv = dev_get_priv(bus);
 393
 394         writel(~MM_SWITCH, &priv->base->memswitch);
 395         if (priv->ctrl_mod_mmap)
 396                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 397                                        slave_plat->cs, false);
 398
 399         writel(0, &priv->base->dc);
 400         writel(0, &priv->base->cmd);
 401         writel(0, &priv->base->data);
 402         writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
 403
 404         return 0;
 405 }
 406
 407 static int ti_qspi_probe(struct udevice *bus)
 408 {
 409         struct ti_qspi_priv *priv = dev_get_priv(bus);
 410
 411         priv->fclk = dev_get_driver_data(bus);
 412
 413         return 0;
 414 }
 415
 416 static void *map_syscon_chipselects(struct udevice *bus)
 417 {
 418 #if CONFIG_IS_ENABLED(SYSCON)
 419         struct udevice *syscon;
 420         struct regmap *regmap;
 421         const fdt32_t *cell;
 422         int len, err;
 423
 424         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 425                                            "syscon-chipselects", &syscon);
 426         if (err) {
 427                 debug("%s: unable to find syscon device (%d)\n", __func__,
 428                       err);
 429                 return NULL;
 430         }
 431
 432         regmap = syscon_get_regmap(syscon);
 433         if (IS_ERR(regmap)) {
 434                 debug("%s: unable to find regmap (%ld)\n", __func__,
 435                       PTR_ERR(regmap));
 436                 return NULL;
 437         }
 438
 439         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 440                            "syscon-chipselects", &len);
 441         if (len < 2*sizeof(fdt32_t)) {
 442                 debug("%s: offset not available\n", __func__);
 443                 return NULL;
 444         }
 445
 446         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 447 #else
 448         fdt_addr_t addr;
 449         addr = devfdt_get_addr_index(bus, 2);
 450         return (addr == FDT_ADDR_T_NONE) ? NULL :
 451                 map_physmem(addr, 0, MAP_NOCACHE);
 452 #endif
 453 }
 454
 455 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 456 {
 457         struct ti_qspi_priv *priv = dev_get_priv(bus);
 458         const void *blob = gd->fdt_blob;
 459         int node = dev_of_offset(bus);
 460         fdt_addr_t mmap_addr;
 461         fdt_addr_t mmap_size;
 462
 463         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 464         priv->base = map_physmem(dev_read_addr(bus),
 465                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 466         mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
 467         priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
 468         priv->mmap_size = mmap_size;
 469
 470         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 471         if (priv->max_hz < 0) {
 472                 debug("Error: Max frequency missing\n");
 473                 return -ENODEV;
 474         }
 475         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 476
 477         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 478               (int)priv->base, priv->max_hz);
 479
 480         return 0;
 481 }
 482
 483 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 484         .exec_op = ti_qspi_exec_mem_op,
 485 };
 486
 487 static const struct dm_spi_ops ti_qspi_ops = {
 488         .claim_bus      = ti_qspi_claim_bus,
 489         .release_bus    = ti_qspi_release_bus,
 490         .xfer           = ti_qspi_xfer,
 491         .set_speed      = ti_qspi_set_speed,
 492         .set_mode       = ti_qspi_set_mode,
 493         .mem_ops        = &ti_qspi_mem_ops,
 494 };
 495
 496 static const struct udevice_id ti_qspi_ids[] = {
 497         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 498         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 499         { }
 500 };
 501
 502 U_BOOT_DRIVER(ti_qspi) = {
 503         .name   = "ti_qspi",
 504         .id     = UCLASS_SPI,
 505         .of_match = ti_qspi_ids,
 506         .ops    = &ti_qspi_ops,
 507         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 508         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 509         .probe  = ti_qspi_probe,
 510 };