drivers/spi/ti_qspi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * TI QSPI driver
   4  *
   5  * Copyright (C) 2013, Texas Instruments, Incorporated
   6  */
   7
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/omap.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <spi-mem.h>
  15 #include <dm.h>
  16 #include <asm/gpio.h>
  17 #include <asm/omap_gpio.h>
  18 #include <asm/omap_common.h>
  19 #include <asm/ti-common/ti-edma3.h>
  20 #include <linux/kernel.h>
  21 #include <regmap.h>
  22 #include <syscon.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* ti qpsi register bit masks */
  27 #define QSPI_TIMEOUT                    2000000
  28 #define QSPI_FCLK                       192000000
  29 #define QSPI_DRA7XX_FCLK                76800000
  30 #define QSPI_WLEN_MAX_BITS              128
  31 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  32 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  33 /* clock control */
  34 #define QSPI_CLK_EN                     BIT(31)
  35 #define QSPI_CLK_DIV_MAX                0xffff
  36 /* command */
  37 #define QSPI_EN_CS(n)                   (n << 28)
  38 #define QSPI_WLEN(n)                    ((n-1) << 19)
  39 #define QSPI_3_PIN                      BIT(18)
  40 #define QSPI_RD_SNGL                    BIT(16)
  41 #define QSPI_WR_SNGL                    (2 << 16)
  42 #define QSPI_INVAL                      (4 << 16)
  43 #define QSPI_RD_QUAD                    (7 << 16)
  44 /* device control */
  45 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  46 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  47 #define QSPI_CKPOL(n)                   (1 << (n*8))
  48 /* status */
  49 #define QSPI_WC                         BIT(1)
  50 #define QSPI_BUSY                       BIT(0)
  51 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  52 #define QSPI_XFER_DONE                  QSPI_WC
  53 #define MM_SWITCH                       0x01
  54 #define MEM_CS(cs)                      ((cs + 1) << 8)
  55 #define MEM_CS_UNSELECT                 0xfffff8ff
  56
  57 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  58 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  59 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  60 #define QSPI_SETUP0_ADDR_SHIFT          (8)
  61 #define QSPI_SETUP0_DBITS_SHIFT         (10)
  62
  63 #define TI_QSPI_SETUP_REG(priv, cs)     (&(priv)->base->setup0 + (cs))
  64
  65 /* ti qspi register set */
  66 struct ti_qspi_regs {
  67         u32 pid;
  68         u32 pad0[3];
  69         u32 sysconfig;
  70         u32 pad1[3];
  71         u32 int_stat_raw;
  72         u32 int_stat_en;
  73         u32 int_en_set;
  74         u32 int_en_ctlr;
  75         u32 intc_eoi;
  76         u32 pad2[3];
  77         u32 clk_ctrl;
  78         u32 dc;
  79         u32 cmd;
  80         u32 status;
  81         u32 data;
  82         u32 setup0;
  83         u32 setup1;
  84         u32 setup2;
  85         u32 setup3;
  86         u32 memswitch;
  87         u32 data1;
  88         u32 data2;
  89         u32 data3;
  90 };
  91
  92 /* ti qspi priv */
  93 struct ti_qspi_priv {
  94         void *memory_map;
  95         size_t mmap_size;
  96         uint max_hz;
  97         u32 num_cs;
  98         struct ti_qspi_regs *base;
  99         void *ctrl_mod_mmap;
 100         ulong fclk;
 101         unsigned int mode;
 102         u32 cmd;
 103         u32 dc;
 104 };
 105
 106 static int ti_qspi_set_speed(struct udevice *bus, uint hz)
 107 {
 108         struct ti_qspi_priv *priv = dev_get_priv(bus);
 109         uint clk_div;
 110
 111         if (!hz)
 112                 clk_div = 0;
 113         else
 114                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 115
 116         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 117         if (clk_div > QSPI_CLK_DIV_MAX)
 118                 clk_div = QSPI_CLK_DIV_MAX;
 119
 120         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 121
 122         /* disable SCLK */
 123         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 124                &priv->base->clk_ctrl);
 125         /* enable SCLK and program the clk divider */
 126         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 127
 128         return 0;
 129 }
 130
 131 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 132 {
 133         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 134         /* dummy readl to ensure bus sync */
 135         readl(&priv->base->cmd);
 136 }
 137
 138 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 139 {
 140         u32 val;
 141
 142         val = readl(ctrl_mod_mmap);
 143         if (enable)
 144                 val |= MEM_CS(cs);
 145         else
 146                 val &= MEM_CS_UNSELECT;
 147         writel(val, ctrl_mod_mmap);
 148 }
 149
 150 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 151                         const void *dout, void *din, unsigned long flags)
 152 {
 153         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 154         struct ti_qspi_priv *priv;
 155         struct udevice *bus;
 156         uint words = bitlen >> 3; /* fixed 8-bit word length */
 157         const uchar *txp = dout;
 158         uchar *rxp = din;
 159         uint status;
 160         int timeout;
 161         unsigned int cs = slave->cs;
 162
 163         bus = dev->parent;
 164         priv = dev_get_priv(bus);
 165
 166         if (cs > priv->num_cs) {
 167                 debug("invalid qspi chip select\n");
 168                 return -EINVAL;
 169         }
 170
 171         if (bitlen == 0)
 172                 return -1;
 173
 174         if (bitlen % 8) {
 175                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 176                 return -1;
 177         }
 178
 179         /* Setup command reg */
 180         priv->cmd = 0;
 181         priv->cmd |= QSPI_WLEN(8);
 182         priv->cmd |= QSPI_EN_CS(cs);
 183         if (priv->mode & SPI_3WIRE)
 184                 priv->cmd |= QSPI_3_PIN;
 185         priv->cmd |= 0xfff;
 186
 187         while (words) {
 188                 u8 xfer_len = 0;
 189
 190                 if (txp) {
 191                         u32 cmd = priv->cmd;
 192
 193                         if (words >= QSPI_WLEN_MAX_BYTES) {
 194                                 u32 *txbuf = (u32 *)txp;
 195                                 u32 data;
 196
 197                                 data = cpu_to_be32(*txbuf++);
 198                                 writel(data, &priv->base->data3);
 199                                 data = cpu_to_be32(*txbuf++);
 200                                 writel(data, &priv->base->data2);
 201                                 data = cpu_to_be32(*txbuf++);
 202                                 writel(data, &priv->base->data1);
 203                                 data = cpu_to_be32(*txbuf++);
 204                                 writel(data, &priv->base->data);
 205                                 cmd &= ~QSPI_WLEN_MASK;
 206                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 207                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 208                         } else {
 209                                 writeb(*txp, &priv->base->data);
 210                                 xfer_len = 1;
 211                         }
 212                         debug("tx cmd %08x dc %08x\n",
 213                               cmd | QSPI_WR_SNGL, priv->dc);
 214                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 215                         status = readl(&priv->base->status);
 216                         timeout = QSPI_TIMEOUT;
 217                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 218                                 if (--timeout < 0) {
 219                                         printf("spi_xfer: TX timeout!\n");
 220                                         return -1;
 221                                 }
 222                                 status = readl(&priv->base->status);
 223                         }
 224                         txp += xfer_len;
 225                         debug("tx done, status %08x\n", status);
 226                 }
 227                 if (rxp) {
 228                         debug("rx cmd %08x dc %08x\n",
 229                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 230                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 231                         status = readl(&priv->base->status);
 232                         timeout = QSPI_TIMEOUT;
 233                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 234                                 if (--timeout < 0) {
 235                                         printf("spi_xfer: RX timeout!\n");
 236                                         return -1;
 237                                 }
 238                                 status = readl(&priv->base->status);
 239                         }
 240                         *rxp++ = readl(&priv->base->data);
 241                         xfer_len = 1;
 242                         debug("rx done, status %08x, read %02x\n",
 243                               status, *(rxp-1));
 244                 }
 245                 words -= xfer_len;
 246         }
 247
 248         /* Terminate frame */
 249         if (flags & SPI_XFER_END)
 250                 ti_qspi_cs_deactivate(priv);
 251
 252         return 0;
 253 }
 254
 255 /* TODO: control from sf layer to here through dm-spi */
 256 static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
 257 {
 258 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 259         unsigned int                    addr = (unsigned int) (data);
 260         unsigned int                    edma_slot_num = 1;
 261
 262         /* Invalidate the area, so no writeback into the RAM races with DMA */
 263         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 264
 265         /* enable edma3 clocks */
 266         enable_edma3_clocks();
 267
 268         /* Call edma3 api to do actual DMA transfer     */
 269         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 270
 271         /* disable edma3 clocks */
 272         disable_edma3_clocks();
 273 #else
 274         memcpy_fromio(data, offset, len);
 275 #endif
 276
 277         *((unsigned int *)offset) += len;
 278 }
 279
 280 static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, int cs,
 281                                     u8 opcode, u8 data_nbits, u8 addr_width,
 282                                     u8 dummy_bytes)
 283 {
 284         u32 memval = opcode;
 285
 286         switch (data_nbits) {
 287         case 4:
 288                 memval |= QSPI_SETUP0_READ_QUAD;
 289                 break;
 290         case 2:
 291                 memval |= QSPI_SETUP0_READ_DUAL;
 292                 break;
 293         default:
 294                 memval |= QSPI_SETUP0_READ_NORMAL;
 295                 break;
 296         }
 297
 298         memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
 299                    dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
 300
 301         writel(memval, TI_QSPI_SETUP_REG(priv, cs));
 302 }
 303
 304 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 305 {
 306         struct ti_qspi_priv *priv = dev_get_priv(bus);
 307
 308         priv->dc = 0;
 309         if (mode & SPI_CPHA)
 310                 priv->dc |= QSPI_CKPHA(0);
 311         if (mode & SPI_CPOL)
 312                 priv->dc |= QSPI_CKPOL(0);
 313         if (mode & SPI_CS_HIGH)
 314                 priv->dc |= QSPI_CSPOL(0);
 315
 316         return 0;
 317 }
 318
 319 static int ti_qspi_exec_mem_op(struct spi_slave *slave,
 320                                const struct spi_mem_op *op)
 321 {
 322         struct dm_spi_slave_platdata *slave_plat;
 323         struct ti_qspi_priv *priv;
 324         struct udevice *bus;
 325         u32 from = 0;
 326         int ret = 0;
 327
 328         bus = slave->dev->parent;
 329         priv = dev_get_priv(bus);
 330         slave_plat = dev_get_parent_platdata(slave->dev);
 331
 332         /* Only optimize read path. */
 333         if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
 334             !op->addr.nbytes || op->addr.nbytes > 4)
 335                 return -ENOTSUPP;
 336
 337         /* Address exceeds MMIO window size, fall back to regular mode. */
 338         from = op->addr.val;
 339         if (from + op->data.nbytes > priv->mmap_size)
 340                 return -ENOTSUPP;
 341
 342         ti_qspi_setup_mmap_read(priv, slave_plat->cs, op->cmd.opcode,
 343                                 op->data.buswidth, op->addr.nbytes,
 344                                 op->dummy.nbytes);
 345
 346         ti_qspi_copy_mmap((void *)op->data.buf.in,
 347                           (void *)priv->memory_map + from, op->data.nbytes);
 348
 349         return ret;
 350 }
 351
 352 static int ti_qspi_claim_bus(struct udevice *dev)
 353 {
 354         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 355         struct ti_qspi_priv *priv;
 356         struct udevice *bus;
 357
 358         bus = dev->parent;
 359         priv = dev_get_priv(bus);
 360
 361         if (slave_plat->cs > priv->num_cs) {
 362                 debug("invalid qspi chip select\n");
 363                 return -EINVAL;
 364         }
 365
 366         writel(MM_SWITCH, &priv->base->memswitch);
 367         if (priv->ctrl_mod_mmap)
 368                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 369                                        slave_plat->cs, true);
 370
 371         writel(priv->dc, &priv->base->dc);
 372         writel(0, &priv->base->cmd);
 373         writel(0, &priv->base->data);
 374
 375         priv->dc <<= slave_plat->cs * 8;
 376         writel(priv->dc, &priv->base->dc);
 377
 378         return 0;
 379 }
 380
 381 static int ti_qspi_release_bus(struct udevice *dev)
 382 {
 383         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 384         struct ti_qspi_priv *priv;
 385         struct udevice *bus;
 386
 387         bus = dev->parent;
 388         priv = dev_get_priv(bus);
 389
 390         writel(~MM_SWITCH, &priv->base->memswitch);
 391         if (priv->ctrl_mod_mmap)
 392                 ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
 393                                        slave_plat->cs, false);
 394
 395         writel(0, &priv->base->dc);
 396         writel(0, &priv->base->cmd);
 397         writel(0, &priv->base->data);
 398         writel(0, TI_QSPI_SETUP_REG(priv, slave_plat->cs));
 399
 400         return 0;
 401 }
 402
 403 static int ti_qspi_probe(struct udevice *bus)
 404 {
 405         struct ti_qspi_priv *priv = dev_get_priv(bus);
 406
 407         priv->fclk = dev_get_driver_data(bus);
 408
 409         return 0;
 410 }
 411
 412 static void *map_syscon_chipselects(struct udevice *bus)
 413 {
 414 #if CONFIG_IS_ENABLED(SYSCON)
 415         struct udevice *syscon;
 416         struct regmap *regmap;
 417         const fdt32_t *cell;
 418         int len, err;
 419
 420         err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
 421                                            "syscon-chipselects", &syscon);
 422         if (err) {
 423                 debug("%s: unable to find syscon device (%d)\n", __func__,
 424                       err);
 425                 return NULL;
 426         }
 427
 428         regmap = syscon_get_regmap(syscon);
 429         if (IS_ERR(regmap)) {
 430                 debug("%s: unable to find regmap (%ld)\n", __func__,
 431                       PTR_ERR(regmap));
 432                 return NULL;
 433         }
 434
 435         cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
 436                            "syscon-chipselects", &len);
 437         if (len < 2*sizeof(fdt32_t)) {
 438                 debug("%s: offset not available\n", __func__);
 439                 return NULL;
 440         }
 441
 442         return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
 443 #else
 444         fdt_addr_t addr;
 445         addr = devfdt_get_addr_index(bus, 2);
 446         return (addr == FDT_ADDR_T_NONE) ? NULL :
 447                 map_physmem(addr, 0, MAP_NOCACHE);
 448 #endif
 449 }
 450
 451 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 452 {
 453         struct ti_qspi_priv *priv = dev_get_priv(bus);
 454         const void *blob = gd->fdt_blob;
 455         int node = dev_of_offset(bus);
 456         fdt_addr_t mmap_addr;
 457         fdt_addr_t mmap_size;
 458
 459         priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
 460         priv->base = map_physmem(devfdt_get_addr(bus),
 461                                  sizeof(struct ti_qspi_regs), MAP_NOCACHE);
 462         mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
 463         priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
 464         priv->mmap_size = mmap_size;
 465
 466         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 467         if (priv->max_hz < 0) {
 468                 debug("Error: Max frequency missing\n");
 469                 return -ENODEV;
 470         }
 471         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 472
 473         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 474               (int)priv->base, priv->max_hz);
 475
 476         return 0;
 477 }
 478
 479 static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
 480         .exec_op = ti_qspi_exec_mem_op,
 481 };
 482
 483 static const struct dm_spi_ops ti_qspi_ops = {
 484         .claim_bus      = ti_qspi_claim_bus,
 485         .release_bus    = ti_qspi_release_bus,
 486         .xfer           = ti_qspi_xfer,
 487         .set_speed      = ti_qspi_set_speed,
 488         .set_mode       = ti_qspi_set_mode,
 489         .mem_ops        = &ti_qspi_mem_ops,
 490 };
 491
 492 static const struct udevice_id ti_qspi_ids[] = {
 493         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 494         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 495         { }
 496 };
 497
 498 U_BOOT_DRIVER(ti_qspi) = {
 499         .name   = "ti_qspi",
 500         .id     = UCLASS_SPI,
 501         .of_match = ti_qspi_ids,
 502         .ops    = &ti_qspi_ops,
 503         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 504         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 505         .probe  = ti_qspi_probe,
 506 };