2 * Copyright 2008, Freescale Semiconductor, Inc
5 * Based vaguely on the Linux code
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <dm/device-internal.h>
20 #include <linux/list.h>
22 #include "mmc_private.h"
24 __weak int board_mmc_getwp(struct mmc *mmc)
29 int mmc_getwp(struct mmc *mmc)
33 wp = board_mmc_getwp(mmc);
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
45 __weak int board_mmc_getcd(struct mmc *mmc)
50 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
54 #ifdef CONFIG_MMC_TRACE
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
62 printf("\t\tRET\t\t\t %d\n", ret);
64 switch (cmd->resp_type) {
66 printf("\t\tMMC_RSP_NONE\n");
69 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
73 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
77 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
79 printf("\t\t \t\t 0x%08X \n",
81 printf("\t\t \t\t 0x%08X \n",
83 printf("\t\t \t\t 0x%08X \n",
86 printf("\t\t\t\t\tDUMPING DATA\n");
87 for (i = 0; i < 4; i++) {
89 printf("\t\t\t\t\t%03d - ", i*4);
90 ptr = (u8 *)&cmd->response[i];
92 for (j = 0; j < 4; j++)
93 printf("%02X ", *ptr--);
98 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
102 printf("\t\tERROR MMC rsp not supported\n");
107 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
112 int mmc_send_status(struct mmc *mmc, int timeout)
115 int err, retries = 5;
116 #ifdef CONFIG_MMC_TRACE
120 cmd.cmdidx = MMC_CMD_SEND_STATUS;
121 cmd.resp_type = MMC_RSP_R1;
122 if (!mmc_host_is_spi(mmc))
123 cmd.cmdarg = mmc->rca << 16;
126 err = mmc_send_cmd(mmc, &cmd, NULL);
128 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
129 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
132 else if (cmd.response[0] & MMC_STATUS_MASK) {
133 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
134 printf("Status Error: 0x%08X\n",
139 } else if (--retries < 0)
148 #ifdef CONFIG_MMC_TRACE
149 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
150 printf("CURR STATE:%d\n", status);
153 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
154 printf("Timeout waiting card ready\n");
158 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
164 int mmc_set_blocklen(struct mmc *mmc, int len)
171 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
172 cmd.resp_type = MMC_RSP_R1;
175 return mmc_send_cmd(mmc, &cmd, NULL);
178 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
182 struct mmc_data data;
185 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
187 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
189 if (mmc->high_capacity)
192 cmd.cmdarg = start * mmc->read_bl_len;
194 cmd.resp_type = MMC_RSP_R1;
197 data.blocks = blkcnt;
198 data.blocksize = mmc->read_bl_len;
199 data.flags = MMC_DATA_READ;
201 if (mmc_send_cmd(mmc, &cmd, &data))
205 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
207 cmd.resp_type = MMC_RSP_R1b;
208 if (mmc_send_cmd(mmc, &cmd, NULL)) {
209 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
210 printf("mmc fail to send stop cmd\n");
220 static ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt,
223 static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start,
224 lbaint_t blkcnt, void *dst)
228 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
230 int dev_num = block_dev->devnum;
232 lbaint_t cur, blocks_todo = blkcnt;
237 struct mmc *mmc = find_mmc_device(dev_num);
241 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
245 if ((start + blkcnt) > block_dev->lba) {
246 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
247 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
248 start + blkcnt, block_dev->lba);
253 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
254 debug("%s: Failed to set blocklen\n", __func__);
259 cur = (blocks_todo > mmc->cfg->b_max) ?
260 mmc->cfg->b_max : blocks_todo;
261 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
262 debug("%s: Failed to read blocks\n", __func__);
267 dst += cur * mmc->read_bl_len;
268 } while (blocks_todo > 0);
273 static int mmc_go_idle(struct mmc *mmc)
280 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
282 cmd.resp_type = MMC_RSP_NONE;
284 err = mmc_send_cmd(mmc, &cmd, NULL);
294 static int sd_send_op_cond(struct mmc *mmc)
301 cmd.cmdidx = MMC_CMD_APP_CMD;
302 cmd.resp_type = MMC_RSP_R1;
305 err = mmc_send_cmd(mmc, &cmd, NULL);
310 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
311 cmd.resp_type = MMC_RSP_R3;
314 * Most cards do not answer if some reserved bits
315 * in the ocr are set. However, Some controller
316 * can set bit 7 (reserved for low voltages), but
317 * how to manage low voltages SD card is not yet
320 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
321 (mmc->cfg->voltages & 0xff8000);
323 if (mmc->version == SD_VERSION_2)
324 cmd.cmdarg |= OCR_HCS;
326 err = mmc_send_cmd(mmc, &cmd, NULL);
331 if (cmd.response[0] & OCR_BUSY)
340 if (mmc->version != SD_VERSION_2)
341 mmc->version = SD_VERSION_1_0;
343 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
344 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
345 cmd.resp_type = MMC_RSP_R3;
348 err = mmc_send_cmd(mmc, &cmd, NULL);
354 mmc->ocr = cmd.response[0];
356 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
362 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
367 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
368 cmd.resp_type = MMC_RSP_R3;
370 if (use_arg && !mmc_host_is_spi(mmc))
371 cmd.cmdarg = OCR_HCS |
372 (mmc->cfg->voltages &
373 (mmc->ocr & OCR_VOLTAGE_MASK)) |
374 (mmc->ocr & OCR_ACCESS_MODE);
376 err = mmc_send_cmd(mmc, &cmd, NULL);
379 mmc->ocr = cmd.response[0];
383 static int mmc_send_op_cond(struct mmc *mmc)
387 /* Some cards seem to need this */
390 /* Asking to the card its capabilities */
391 for (i = 0; i < 2; i++) {
392 err = mmc_send_op_cond_iter(mmc, i != 0);
396 /* exit if not busy (flag seems to be inverted) */
397 if (mmc->ocr & OCR_BUSY)
400 mmc->op_cond_pending = 1;
404 static int mmc_complete_op_cond(struct mmc *mmc)
411 mmc->op_cond_pending = 0;
412 if (!(mmc->ocr & OCR_BUSY)) {
413 start = get_timer(0);
415 err = mmc_send_op_cond_iter(mmc, 1);
418 if (mmc->ocr & OCR_BUSY)
420 if (get_timer(start) > timeout)
426 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
427 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
428 cmd.resp_type = MMC_RSP_R3;
431 err = mmc_send_cmd(mmc, &cmd, NULL);
436 mmc->ocr = cmd.response[0];
439 mmc->version = MMC_VERSION_UNKNOWN;
441 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
448 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
451 struct mmc_data data;
454 /* Get the Card Status Register */
455 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
456 cmd.resp_type = MMC_RSP_R1;
459 data.dest = (char *)ext_csd;
461 data.blocksize = MMC_MAX_BLOCK_LEN;
462 data.flags = MMC_DATA_READ;
464 err = mmc_send_cmd(mmc, &cmd, &data);
470 static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
476 cmd.cmdidx = MMC_CMD_SWITCH;
477 cmd.resp_type = MMC_RSP_R1b;
478 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
482 ret = mmc_send_cmd(mmc, &cmd, NULL);
484 /* Waiting for the ready status */
486 ret = mmc_send_status(mmc, timeout);
492 static int mmc_change_freq(struct mmc *mmc)
494 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
500 if (mmc_host_is_spi(mmc))
503 /* Only version 4 supports high-speed */
504 if (mmc->version < MMC_VERSION_4)
507 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
509 err = mmc_send_ext_csd(mmc, ext_csd);
514 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
516 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
519 return err == SWITCH_ERR ? 0 : err;
521 /* Now check to see that it worked */
522 err = mmc_send_ext_csd(mmc, ext_csd);
527 /* No high-speed support */
528 if (!ext_csd[EXT_CSD_HS_TIMING])
531 /* High Speed is set, there are two types: 52MHz and 26MHz */
532 if (cardtype & EXT_CSD_CARD_TYPE_52) {
533 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
534 mmc->card_caps |= MMC_MODE_DDR_52MHz;
535 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
537 mmc->card_caps |= MMC_MODE_HS;
543 static int mmc_set_capacity(struct mmc *mmc, int part_num)
547 mmc->capacity = mmc->capacity_user;
551 mmc->capacity = mmc->capacity_boot;
554 mmc->capacity = mmc->capacity_rpmb;
560 mmc->capacity = mmc->capacity_gp[part_num - 4];
566 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
571 static int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
575 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
576 (mmc->part_config & ~PART_ACCESS_MASK)
577 | (part_num & PART_ACCESS_MASK));
580 * Set the capacity if the switch succeeded or was intended
581 * to return to representing the raw device.
583 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
584 ret = mmc_set_capacity(mmc, part_num);
585 mmc_get_blk_desc(mmc)->hwpart = part_num;
592 static int mmc_select_hwpart(struct udevice *bdev, int hwpart)
594 struct udevice *mmc_dev = dev_get_parent(bdev);
595 struct mmc *mmc = mmc_get_mmc_dev(mmc_dev);
596 struct blk_desc *desc = dev_get_uclass_platdata(bdev);
599 if (desc->hwpart == hwpart)
602 if (mmc->part_config == MMCPART_NOAVAILABLE)
605 ret = mmc_switch_part(mmc, hwpart);
612 static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart)
614 struct mmc *mmc = find_mmc_device(desc->devnum);
620 if (mmc->block_dev.hwpart == hwpart)
623 if (mmc->part_config == MMCPART_NOAVAILABLE)
626 ret = mmc_switch_part(mmc, hwpart);
634 int mmc_hwpart_config(struct mmc *mmc,
635 const struct mmc_hwpart_conf *conf,
636 enum mmc_hwpart_conf_mode mode)
642 u32 max_enh_size_mult;
643 u32 tot_enh_size_mult = 0;
646 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
648 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
651 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
652 printf("eMMC >= 4.4 required for enhanced user data area\n");
656 if (!(mmc->part_support & PART_SUPPORT)) {
657 printf("Card does not support partitioning\n");
661 if (!mmc->hc_wp_grp_size) {
662 printf("Card does not define HC WP group size\n");
666 /* check partition alignment and total enhanced size */
667 if (conf->user.enh_size) {
668 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
669 conf->user.enh_start % mmc->hc_wp_grp_size) {
670 printf("User data enhanced area not HC WP group "
674 part_attrs |= EXT_CSD_ENH_USR;
675 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
676 if (mmc->high_capacity) {
677 enh_start_addr = conf->user.enh_start;
679 enh_start_addr = (conf->user.enh_start << 9);
685 tot_enh_size_mult += enh_size_mult;
687 for (pidx = 0; pidx < 4; pidx++) {
688 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
689 printf("GP%i partition not HC WP group size "
690 "aligned\n", pidx+1);
693 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
694 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
695 part_attrs |= EXT_CSD_ENH_GP(pidx);
696 tot_enh_size_mult += gp_size_mult[pidx];
700 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
701 printf("Card does not support enhanced attribute\n");
705 err = mmc_send_ext_csd(mmc, ext_csd);
710 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
711 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
712 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
713 if (tot_enh_size_mult > max_enh_size_mult) {
714 printf("Total enhanced size exceeds maximum (%u > %u)\n",
715 tot_enh_size_mult, max_enh_size_mult);
719 /* The default value of EXT_CSD_WR_REL_SET is device
720 * dependent, the values can only be changed if the
721 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
722 * changed only once and before partitioning is completed. */
723 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
724 if (conf->user.wr_rel_change) {
725 if (conf->user.wr_rel_set)
726 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
728 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
730 for (pidx = 0; pidx < 4; pidx++) {
731 if (conf->gp_part[pidx].wr_rel_change) {
732 if (conf->gp_part[pidx].wr_rel_set)
733 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
735 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
739 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
740 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
741 puts("Card does not support host controlled partition write "
742 "reliability settings\n");
746 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
747 EXT_CSD_PARTITION_SETTING_COMPLETED) {
748 printf("Card already partitioned\n");
752 if (mode == MMC_HWPART_CONF_CHECK)
755 /* Partitioning requires high-capacity size definitions */
756 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
757 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
758 EXT_CSD_ERASE_GROUP_DEF, 1);
763 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
765 /* update erase group size to be high-capacity */
766 mmc->erase_grp_size =
767 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
771 /* all OK, write the configuration */
772 for (i = 0; i < 4; i++) {
773 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
774 EXT_CSD_ENH_START_ADDR+i,
775 (enh_start_addr >> (i*8)) & 0xFF);
779 for (i = 0; i < 3; i++) {
780 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
781 EXT_CSD_ENH_SIZE_MULT+i,
782 (enh_size_mult >> (i*8)) & 0xFF);
786 for (pidx = 0; pidx < 4; pidx++) {
787 for (i = 0; i < 3; i++) {
788 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
789 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
790 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
795 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
796 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
800 if (mode == MMC_HWPART_CONF_SET)
803 /* The WR_REL_SET is a write-once register but shall be
804 * written before setting PART_SETTING_COMPLETED. As it is
805 * write-once we can only write it when completing the
807 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
808 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
809 EXT_CSD_WR_REL_SET, wr_rel_set);
814 /* Setting PART_SETTING_COMPLETED confirms the partition
815 * configuration but it only becomes effective after power
816 * cycle, so we do not adjust the partition related settings
817 * in the mmc struct. */
819 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
820 EXT_CSD_PARTITION_SETTING,
821 EXT_CSD_PARTITION_SETTING_COMPLETED);
828 int mmc_getcd(struct mmc *mmc)
832 cd = board_mmc_getcd(mmc);
835 if (mmc->cfg->ops->getcd)
836 cd = mmc->cfg->ops->getcd(mmc);
844 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
847 struct mmc_data data;
849 /* Switch the frequency */
850 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
851 cmd.resp_type = MMC_RSP_R1;
852 cmd.cmdarg = (mode << 31) | 0xffffff;
853 cmd.cmdarg &= ~(0xf << (group * 4));
854 cmd.cmdarg |= value << (group * 4);
856 data.dest = (char *)resp;
859 data.flags = MMC_DATA_READ;
861 return mmc_send_cmd(mmc, &cmd, &data);
865 static int sd_change_freq(struct mmc *mmc)
869 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
870 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
871 struct mmc_data data;
876 if (mmc_host_is_spi(mmc))
879 /* Read the SCR to find out if this card supports higher speeds */
880 cmd.cmdidx = MMC_CMD_APP_CMD;
881 cmd.resp_type = MMC_RSP_R1;
882 cmd.cmdarg = mmc->rca << 16;
884 err = mmc_send_cmd(mmc, &cmd, NULL);
889 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
890 cmd.resp_type = MMC_RSP_R1;
896 data.dest = (char *)scr;
899 data.flags = MMC_DATA_READ;
901 err = mmc_send_cmd(mmc, &cmd, &data);
910 mmc->scr[0] = __be32_to_cpu(scr[0]);
911 mmc->scr[1] = __be32_to_cpu(scr[1]);
913 switch ((mmc->scr[0] >> 24) & 0xf) {
915 mmc->version = SD_VERSION_1_0;
918 mmc->version = SD_VERSION_1_10;
921 mmc->version = SD_VERSION_2;
922 if ((mmc->scr[0] >> 15) & 0x1)
923 mmc->version = SD_VERSION_3;
926 mmc->version = SD_VERSION_1_0;
930 if (mmc->scr[0] & SD_DATA_4BIT)
931 mmc->card_caps |= MMC_MODE_4BIT;
933 /* Version 1.0 doesn't support switching */
934 if (mmc->version == SD_VERSION_1_0)
939 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
940 (u8 *)switch_status);
945 /* The high-speed function is busy. Try again */
946 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
950 /* If high-speed isn't supported, we return */
951 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
955 * If the host doesn't support SD_HIGHSPEED, do not switch card to
956 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
957 * This can avoid furthur problem when the card runs in different
958 * mode between the host.
960 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
961 (mmc->cfg->host_caps & MMC_MODE_HS)))
964 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
969 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
970 mmc->card_caps |= MMC_MODE_HS;
975 /* frequency bases */
976 /* divided by 10 to be nice to platforms without floating point */
977 static const int fbase[] = {
984 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
985 * to platforms without floating point.
987 static const u8 multipliers[] = {
1006 static void mmc_set_ios(struct mmc *mmc)
1008 if (mmc->cfg->ops->set_ios)
1009 mmc->cfg->ops->set_ios(mmc);
1012 void mmc_set_clock(struct mmc *mmc, uint clock)
1014 if (clock > mmc->cfg->f_max)
1015 clock = mmc->cfg->f_max;
1017 if (clock < mmc->cfg->f_min)
1018 clock = mmc->cfg->f_min;
1025 static void mmc_set_bus_width(struct mmc *mmc, uint width)
1027 mmc->bus_width = width;
1032 static int mmc_startup(struct mmc *mmc)
1036 u64 cmult, csize, capacity;
1038 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1039 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1041 bool has_parts = false;
1042 bool part_completed;
1043 struct blk_desc *bdesc;
1045 #ifdef CONFIG_MMC_SPI_CRC_ON
1046 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1047 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1048 cmd.resp_type = MMC_RSP_R1;
1050 err = mmc_send_cmd(mmc, &cmd, NULL);
1057 /* Put the Card in Identify Mode */
1058 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1059 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
1060 cmd.resp_type = MMC_RSP_R2;
1063 err = mmc_send_cmd(mmc, &cmd, NULL);
1068 memcpy(mmc->cid, cmd.response, 16);
1071 * For MMC cards, set the Relative Address.
1072 * For SD cards, get the Relatvie Address.
1073 * This also puts the cards into Standby State
1075 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1076 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1077 cmd.cmdarg = mmc->rca << 16;
1078 cmd.resp_type = MMC_RSP_R6;
1080 err = mmc_send_cmd(mmc, &cmd, NULL);
1086 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1089 /* Get the Card-Specific Data */
1090 cmd.cmdidx = MMC_CMD_SEND_CSD;
1091 cmd.resp_type = MMC_RSP_R2;
1092 cmd.cmdarg = mmc->rca << 16;
1094 err = mmc_send_cmd(mmc, &cmd, NULL);
1096 /* Waiting for the ready status */
1097 mmc_send_status(mmc, timeout);
1102 mmc->csd[0] = cmd.response[0];
1103 mmc->csd[1] = cmd.response[1];
1104 mmc->csd[2] = cmd.response[2];
1105 mmc->csd[3] = cmd.response[3];
1107 if (mmc->version == MMC_VERSION_UNKNOWN) {
1108 int version = (cmd.response[0] >> 26) & 0xf;
1112 mmc->version = MMC_VERSION_1_2;
1115 mmc->version = MMC_VERSION_1_4;
1118 mmc->version = MMC_VERSION_2_2;
1121 mmc->version = MMC_VERSION_3;
1124 mmc->version = MMC_VERSION_4;
1127 mmc->version = MMC_VERSION_1_2;
1132 /* divide frequency by 10, since the mults are 10x bigger */
1133 freq = fbase[(cmd.response[0] & 0x7)];
1134 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
1136 mmc->tran_speed = freq * mult;
1138 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
1139 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
1142 mmc->write_bl_len = mmc->read_bl_len;
1144 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
1146 if (mmc->high_capacity) {
1147 csize = (mmc->csd[1] & 0x3f) << 16
1148 | (mmc->csd[2] & 0xffff0000) >> 16;
1151 csize = (mmc->csd[1] & 0x3ff) << 2
1152 | (mmc->csd[2] & 0xc0000000) >> 30;
1153 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1156 mmc->capacity_user = (csize + 1) << (cmult + 2);
1157 mmc->capacity_user *= mmc->read_bl_len;
1158 mmc->capacity_boot = 0;
1159 mmc->capacity_rpmb = 0;
1160 for (i = 0; i < 4; i++)
1161 mmc->capacity_gp[i] = 0;
1163 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1164 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1166 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1167 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1169 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1170 cmd.cmdidx = MMC_CMD_SET_DSR;
1171 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1172 cmd.resp_type = MMC_RSP_NONE;
1173 if (mmc_send_cmd(mmc, &cmd, NULL))
1174 printf("MMC: SET_DSR failed\n");
1177 /* Select the card, and put it into Transfer Mode */
1178 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1179 cmd.cmdidx = MMC_CMD_SELECT_CARD;
1180 cmd.resp_type = MMC_RSP_R1;
1181 cmd.cmdarg = mmc->rca << 16;
1182 err = mmc_send_cmd(mmc, &cmd, NULL);
1189 * For SD, its erase group is always one sector
1191 mmc->erase_grp_size = 1;
1192 mmc->part_config = MMCPART_NOAVAILABLE;
1193 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
1194 /* check ext_csd version and capacity */
1195 err = mmc_send_ext_csd(mmc, ext_csd);
1198 if (ext_csd[EXT_CSD_REV] >= 2) {
1200 * According to the JEDEC Standard, the value of
1201 * ext_csd's capacity is valid if the value is more
1204 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1205 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1206 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1207 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1208 capacity *= MMC_MAX_BLOCK_LEN;
1209 if ((capacity >> 20) > 2 * 1024)
1210 mmc->capacity_user = capacity;
1213 switch (ext_csd[EXT_CSD_REV]) {
1215 mmc->version = MMC_VERSION_4_1;
1218 mmc->version = MMC_VERSION_4_2;
1221 mmc->version = MMC_VERSION_4_3;
1224 mmc->version = MMC_VERSION_4_41;
1227 mmc->version = MMC_VERSION_4_5;
1230 mmc->version = MMC_VERSION_5_0;
1234 /* The partition data may be non-zero but it is only
1235 * effective if PARTITION_SETTING_COMPLETED is set in
1236 * EXT_CSD, so ignore any data if this bit is not set,
1237 * except for enabling the high-capacity group size
1238 * definition (see below). */
1239 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1240 EXT_CSD_PARTITION_SETTING_COMPLETED);
1242 /* store the partition info of emmc */
1243 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1244 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1245 ext_csd[EXT_CSD_BOOT_MULT])
1246 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1247 if (part_completed &&
1248 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1249 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1251 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1253 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1255 for (i = 0; i < 4; i++) {
1256 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1257 uint mult = (ext_csd[idx + 2] << 16) +
1258 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1261 if (!part_completed)
1263 mmc->capacity_gp[i] = mult;
1264 mmc->capacity_gp[i] *=
1265 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1266 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1267 mmc->capacity_gp[i] <<= 19;
1270 if (part_completed) {
1271 mmc->enh_user_size =
1272 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1273 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1274 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1275 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1276 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1277 mmc->enh_user_size <<= 19;
1278 mmc->enh_user_start =
1279 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1280 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1281 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1282 ext_csd[EXT_CSD_ENH_START_ADDR];
1283 if (mmc->high_capacity)
1284 mmc->enh_user_start <<= 9;
1288 * Host needs to enable ERASE_GRP_DEF bit if device is
1289 * partitioned. This bit will be lost every time after a reset
1290 * or power off. This will affect erase size.
1294 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1295 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1298 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1299 EXT_CSD_ERASE_GROUP_DEF, 1);
1304 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1307 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1308 /* Read out group size from ext_csd */
1309 mmc->erase_grp_size =
1310 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1312 * if high capacity and partition setting completed
1313 * SEC_COUNT is valid even if it is smaller than 2 GiB
1314 * JEDEC Standard JESD84-B45, 6.2.4
1316 if (mmc->high_capacity && part_completed) {
1317 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1318 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1319 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1320 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1321 capacity *= MMC_MAX_BLOCK_LEN;
1322 mmc->capacity_user = capacity;
1325 /* Calculate the group size from the csd value. */
1326 int erase_gsz, erase_gmul;
1327 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1328 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1329 mmc->erase_grp_size = (erase_gsz + 1)
1333 mmc->hc_wp_grp_size = 1024
1334 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1335 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1337 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1340 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
1345 err = sd_change_freq(mmc);
1347 err = mmc_change_freq(mmc);
1352 /* Restrict card's capabilities by what the host can do */
1353 mmc->card_caps &= mmc->cfg->host_caps;
1356 if (mmc->card_caps & MMC_MODE_4BIT) {
1357 cmd.cmdidx = MMC_CMD_APP_CMD;
1358 cmd.resp_type = MMC_RSP_R1;
1359 cmd.cmdarg = mmc->rca << 16;
1361 err = mmc_send_cmd(mmc, &cmd, NULL);
1365 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1366 cmd.resp_type = MMC_RSP_R1;
1368 err = mmc_send_cmd(mmc, &cmd, NULL);
1372 mmc_set_bus_width(mmc, 4);
1375 if (mmc->card_caps & MMC_MODE_HS)
1376 mmc->tran_speed = 50000000;
1378 mmc->tran_speed = 25000000;
1379 } else if (mmc->version >= MMC_VERSION_4) {
1380 /* Only version 4 of MMC supports wider bus widths */
1383 /* An array of possible bus widths in order of preference */
1384 static unsigned ext_csd_bits[] = {
1385 EXT_CSD_DDR_BUS_WIDTH_8,
1386 EXT_CSD_DDR_BUS_WIDTH_4,
1387 EXT_CSD_BUS_WIDTH_8,
1388 EXT_CSD_BUS_WIDTH_4,
1389 EXT_CSD_BUS_WIDTH_1,
1392 /* An array to map CSD bus widths to host cap bits */
1393 static unsigned ext_to_hostcaps[] = {
1394 [EXT_CSD_DDR_BUS_WIDTH_4] =
1395 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1396 [EXT_CSD_DDR_BUS_WIDTH_8] =
1397 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1398 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1399 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1402 /* An array to map chosen bus width to an integer */
1403 static unsigned widths[] = {
1407 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1408 unsigned int extw = ext_csd_bits[idx];
1409 unsigned int caps = ext_to_hostcaps[extw];
1412 * If the bus width is still not changed,
1413 * don't try to set the default again.
1414 * Otherwise, recover from switch attempts
1415 * by switching to 1-bit bus width.
1417 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1418 mmc->bus_width == 1) {
1424 * Check to make sure the card and controller support
1425 * these capabilities
1427 if ((mmc->card_caps & caps) != caps)
1430 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1431 EXT_CSD_BUS_WIDTH, extw);
1436 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1437 mmc_set_bus_width(mmc, widths[idx]);
1439 err = mmc_send_ext_csd(mmc, test_csd);
1444 /* Only compare read only fields */
1445 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1446 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1447 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1448 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1449 ext_csd[EXT_CSD_REV]
1450 == test_csd[EXT_CSD_REV] &&
1451 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1452 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1453 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1454 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1463 if (mmc->card_caps & MMC_MODE_HS) {
1464 if (mmc->card_caps & MMC_MODE_HS_52MHz)
1465 mmc->tran_speed = 52000000;
1467 mmc->tran_speed = 26000000;
1471 mmc_set_clock(mmc, mmc->tran_speed);
1473 /* Fix the block length for DDR mode */
1474 if (mmc->ddr_mode) {
1475 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1476 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1479 /* fill in device description */
1480 bdesc = mmc_get_blk_desc(mmc);
1484 bdesc->blksz = mmc->read_bl_len;
1485 bdesc->log2blksz = LOG2(bdesc->blksz);
1486 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
1487 #if !defined(CONFIG_SPL_BUILD) || \
1488 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1489 !defined(CONFIG_USE_TINY_PRINTF))
1490 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
1491 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1492 (mmc->cid[3] >> 16) & 0xffff);
1493 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1494 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1495 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1496 (mmc->cid[2] >> 24) & 0xff);
1497 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1498 (mmc->cid[2] >> 16) & 0xf);
1500 bdesc->vendor[0] = 0;
1501 bdesc->product[0] = 0;
1502 bdesc->revision[0] = 0;
1504 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
1511 static int mmc_send_if_cond(struct mmc *mmc)
1516 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1517 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
1518 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
1519 cmd.resp_type = MMC_RSP_R7;
1521 err = mmc_send_cmd(mmc, &cmd, NULL);
1526 if ((cmd.response[0] & 0xff) != 0xaa)
1527 return UNUSABLE_ERR;
1529 mmc->version = SD_VERSION_2;
1535 int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
1537 struct blk_desc *bdesc;
1538 struct udevice *bdev;
1541 ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512,
1544 debug("Cannot create block device\n");
1547 bdesc = dev_get_uclass_platdata(bdev);
1551 /* the following chunk was from mmc_register() */
1553 /* Setup dsr related values */
1555 mmc->dsr = 0xffffffff;
1556 /* Setup the universal parts of the block interface just once */
1557 bdesc->removable = 1;
1559 /* setup initial part type */
1560 bdesc->part_type = cfg->part_type;
1566 int mmc_unbind(struct udevice *dev)
1568 struct udevice *bdev;
1570 device_find_first_child(dev, &bdev);
1572 device_remove(bdev);
1573 device_unbind(bdev);
1580 struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
1582 struct blk_desc *bdesc;
1585 /* quick validation */
1586 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1587 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1590 mmc = calloc(1, sizeof(*mmc));
1597 /* the following chunk was mmc_register() */
1599 /* Setup dsr related values */
1601 mmc->dsr = 0xffffffff;
1602 /* Setup the universal parts of the block interface just once */
1603 bdesc = mmc_get_blk_desc(mmc);
1604 bdesc->if_type = IF_TYPE_MMC;
1605 bdesc->removable = 1;
1606 bdesc->devnum = mmc_get_next_devnum();
1607 bdesc->block_read = mmc_bread;
1608 bdesc->block_write = mmc_bwrite;
1609 bdesc->block_erase = mmc_berase;
1611 /* setup initial part type */
1612 bdesc->part_type = mmc->cfg->part_type;
1618 void mmc_destroy(struct mmc *mmc)
1620 /* only freeing memory for now */
1626 static int mmc_get_dev(int dev, struct blk_desc **descp)
1628 struct mmc *mmc = find_mmc_device(dev);
1633 ret = mmc_init(mmc);
1637 *descp = &mmc->block_dev;
1643 /* board-specific MMC power initializations. */
1644 __weak void board_mmc_power_init(void)
1648 int mmc_start_init(struct mmc *mmc)
1652 /* we pretend there's no card when init is NULL */
1653 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
1655 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1656 printf("MMC: no card present\n");
1664 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1665 mmc_adapter_card_type_ident();
1667 board_mmc_power_init();
1669 /* made sure it's not NULL earlier */
1670 err = mmc->cfg->ops->init(mmc);
1676 mmc_set_bus_width(mmc, 1);
1677 mmc_set_clock(mmc, 1);
1679 /* Reset the Card */
1680 err = mmc_go_idle(mmc);
1685 /* The internal partition reset to user partition(0) at every CMD0*/
1686 mmc_get_blk_desc(mmc)->hwpart = 0;
1688 /* Test for SD version 2 */
1689 err = mmc_send_if_cond(mmc);
1691 /* Now try to get the SD card's operating condition */
1692 err = sd_send_op_cond(mmc);
1694 /* If the command timed out, we check for an MMC card */
1695 if (err == TIMEOUT) {
1696 err = mmc_send_op_cond(mmc);
1699 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1700 printf("Card did not respond to voltage select!\n");
1702 return UNUSABLE_ERR;
1707 mmc->init_in_progress = 1;
1712 static int mmc_complete_init(struct mmc *mmc)
1716 mmc->init_in_progress = 0;
1717 if (mmc->op_cond_pending)
1718 err = mmc_complete_op_cond(mmc);
1721 err = mmc_startup(mmc);
1729 int mmc_init(struct mmc *mmc)
1733 #ifdef CONFIG_DM_MMC
1734 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
1741 start = get_timer(0);
1743 if (!mmc->init_in_progress)
1744 err = mmc_start_init(mmc);
1747 err = mmc_complete_init(mmc);
1748 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
1752 int mmc_set_dsr(struct mmc *mmc, u16 val)
1758 /* CPU-specific MMC initializations */
1759 __weak int cpu_mmc_init(bd_t *bis)
1764 /* board-specific MMC initializations. */
1765 __weak int board_mmc_init(bd_t *bis)
1770 void mmc_set_preinit(struct mmc *mmc, int preinit)
1772 mmc->preinit = preinit;
1775 #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD)
1776 static int mmc_probe(bd_t *bis)
1780 #elif defined(CONFIG_DM_MMC)
1781 static int mmc_probe(bd_t *bis)
1785 struct udevice *dev;
1787 ret = uclass_get(UCLASS_MMC, &uc);
1792 * Try to add them in sequence order. Really with driver model we
1793 * should allow holes, but the current MMC list does not allow that.
1794 * So if we request 0, 1, 3 we will get 0, 1, 2.
1796 for (i = 0; ; i++) {
1797 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1801 uclass_foreach_dev(dev, uc) {
1802 ret = device_probe(dev);
1804 printf("%s - probe failed: %d\n", dev->name, ret);
1810 static int mmc_probe(bd_t *bis)
1812 if (board_mmc_init(bis) < 0)
1819 int mmc_initialize(bd_t *bis)
1821 static int initialized = 0;
1823 if (initialized) /* Avoid initializing mmc multiple times */
1830 ret = mmc_probe(bis);
1834 #ifndef CONFIG_SPL_BUILD
1835 print_mmc_devices(',');
1842 #ifdef CONFIG_SUPPORT_EMMC_BOOT
1844 * This function changes the size of boot partition and the size of rpmb
1845 * partition present on EMMC devices.
1848 * struct *mmc: pointer for the mmc device strcuture
1849 * bootsize: size of boot partition
1850 * rpmbsize: size of rpmb partition
1852 * Returns 0 on success.
1855 int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1856 unsigned long rpmbsize)
1861 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1862 cmd.cmdidx = MMC_CMD_RES_MAN;
1863 cmd.resp_type = MMC_RSP_R1b;
1864 cmd.cmdarg = MMC_CMD62_ARG1;
1866 err = mmc_send_cmd(mmc, &cmd, NULL);
1868 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1872 /* Boot partition changing mode */
1873 cmd.cmdidx = MMC_CMD_RES_MAN;
1874 cmd.resp_type = MMC_RSP_R1b;
1875 cmd.cmdarg = MMC_CMD62_ARG2;
1877 err = mmc_send_cmd(mmc, &cmd, NULL);
1879 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1882 /* boot partition size is multiple of 128KB */
1883 bootsize = (bootsize * 1024) / 128;
1885 /* Arg: boot partition size */
1886 cmd.cmdidx = MMC_CMD_RES_MAN;
1887 cmd.resp_type = MMC_RSP_R1b;
1888 cmd.cmdarg = bootsize;
1890 err = mmc_send_cmd(mmc, &cmd, NULL);
1892 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1895 /* RPMB partition size is multiple of 128KB */
1896 rpmbsize = (rpmbsize * 1024) / 128;
1897 /* Arg: RPMB partition size */
1898 cmd.cmdidx = MMC_CMD_RES_MAN;
1899 cmd.resp_type = MMC_RSP_R1b;
1900 cmd.cmdarg = rpmbsize;
1902 err = mmc_send_cmd(mmc, &cmd, NULL);
1904 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1911 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1912 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1915 * Returns 0 on success.
1917 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1921 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1922 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1923 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1924 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1932 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1933 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1936 * Returns 0 on success.
1938 int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1942 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1943 EXT_CSD_BOOT_ACK(ack) |
1944 EXT_CSD_BOOT_PART_NUM(part_num) |
1945 EXT_CSD_PARTITION_ACCESS(access));
1953 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1954 * for enable. Note that this is a write-once field for non-zero values.
1956 * Returns 0 on success.
1958 int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1960 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1966 static const struct blk_ops mmc_blk_ops = {
1968 .write = mmc_bwrite,
1969 .select_hwpart = mmc_select_hwpart,
1972 U_BOOT_DRIVER(mmc_blk) = {
1975 .ops = &mmc_blk_ops,
1978 U_BOOT_LEGACY_BLK(mmc) = {
1979 .if_typename = "mmc",
1980 .if_type = IF_TYPE_MMC,
1982 .get_dev = mmc_get_dev,
1983 .select_hwpart = mmc_select_hwpartp,