arch/arm/mach-versal/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2016 - 2018 Xilinx, Inc.
   4  * Michal Simek <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/armv8/mmu.h>
   9 #include <asm/io.h>
  10
  11 static struct mm_region versal_mem_map[] = {
  12         {
  13                 .virt = 0x0UL,
  14                 .phys = 0x0UL,
  15                 .size = 0x80000000UL,
  16                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  17                          PTE_BLOCK_INNER_SHARE
  18         }, {
  19                 .virt = 0x80000000UL,
  20                 .phys = 0x80000000UL,
  21                 .size = 0x70000000UL,
  22                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  23                          PTE_BLOCK_NON_SHARE |
  24                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  25         }, {
  26                 .virt = 0xf0000000UL,
  27                 .phys = 0xf0000000UL,
  28                 .size = 0x0fe00000UL,
  29                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  30                          PTE_BLOCK_NON_SHARE |
  31                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  32         }, {
  33                 .virt = 0xffe00000UL,
  34                 .phys = 0xffe00000UL,
  35                 .size = 0x00200000UL,
  36                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  37                          PTE_BLOCK_INNER_SHARE
  38         }, {
  39                 .virt = 0x400000000UL,
  40                 .phys = 0x400000000UL,
  41                 .size = 0x200000000UL,
  42                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  43                          PTE_BLOCK_NON_SHARE |
  44                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  45         }, {
  46                 .virt = 0x600000000UL,
  47                 .phys = 0x600000000UL,
  48                 .size = 0x800000000UL,
  49                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  50                          PTE_BLOCK_INNER_SHARE
  51         }, {
  52                 .virt = 0xe00000000UL,
  53                 .phys = 0xe00000000UL,
  54                 .size = 0xf200000000UL,
  55                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  56                          PTE_BLOCK_NON_SHARE |
  57                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
  58         }, {
  59                 /* List terminator */
  60                 0,
  61         }
  62 };
  63
  64 struct mm_region *mem_map = versal_mem_map;
  65
  66 u64 get_page_table_size(void)
  67 {
  68         return 0x14000;
  69 }
  70
  71 #if defined(CONFIG_OF_BOARD)
  72 void *board_fdt_blob_setup(void)
  73 {
  74         static void *fw_dtb = (void *)CONFIG_VERSAL_OF_BOARD_DTB_ADDR;
  75
  76         if (fdt_magic(fw_dtb) != FDT_MAGIC) {
  77                 printf("DTB is not passed via %llx\n", (u64)fw_dtb);
  78                 return NULL;
  79         }
  80
  81         return fw_dtb;
  82 }
  83 #endif