drivers/spi/ti_qspi.c

   1 /*
   2  * TI QSPI driver
   3  *
   4  * Copyright (C) 2013, Texas Instruments, Incorporated
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/omap.h>
  12 #include <malloc.h>
  13 #include <spi.h>
  14 #include <dm.h>
  15 #include <asm/gpio.h>
  16 #include <asm/omap_gpio.h>
  17 #include <asm/omap_common.h>
  18 #include <asm/ti-common/ti-edma3.h>
  19 #include <linux/kernel.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /* ti qpsi register bit masks */
  24 #define QSPI_TIMEOUT                    2000000
  25 #define QSPI_FCLK                       192000000
  26 #define QSPI_DRA7XX_FCLK                76800000
  27 #define QSPI_WLEN_MAX_BITS              128
  28 #define QSPI_WLEN_MAX_BYTES             (QSPI_WLEN_MAX_BITS >> 3)
  29 #define QSPI_WLEN_MASK                  QSPI_WLEN(QSPI_WLEN_MAX_BITS)
  30 /* clock control */
  31 #define QSPI_CLK_EN                     BIT(31)
  32 #define QSPI_CLK_DIV_MAX                0xffff
  33 /* command */
  34 #define QSPI_EN_CS(n)                   (n << 28)
  35 #define QSPI_WLEN(n)                    ((n-1) << 19)
  36 #define QSPI_3_PIN                      BIT(18)
  37 #define QSPI_RD_SNGL                    BIT(16)
  38 #define QSPI_WR_SNGL                    (2 << 16)
  39 #define QSPI_INVAL                      (4 << 16)
  40 #define QSPI_RD_QUAD                    (7 << 16)
  41 /* device control */
  42 #define QSPI_DD(m, n)                   (m << (3 + n*8))
  43 #define QSPI_CKPHA(n)                   (1 << (2 + n*8))
  44 #define QSPI_CSPOL(n)                   (1 << (1 + n*8))
  45 #define QSPI_CKPOL(n)                   (1 << (n*8))
  46 /* status */
  47 #define QSPI_WC                         BIT(1)
  48 #define QSPI_BUSY                       BIT(0)
  49 #define QSPI_WC_BUSY                    (QSPI_WC | QSPI_BUSY)
  50 #define QSPI_XFER_DONE                  QSPI_WC
  51 #define MM_SWITCH                       0x01
  52 #define MEM_CS(cs)                      ((cs + 1) << 8)
  53 #define MEM_CS_UNSELECT                 0xfffff8ff
  54 #define MMAP_START_ADDR_DRA             0x5c000000
  55 #define MMAP_START_ADDR_AM43x           0x30000000
  56 #define CORE_CTRL_IO                    0x4a002558
  57
  58 #define QSPI_CMD_READ                   (0x3 << 0)
  59 #define QSPI_CMD_READ_DUAL              (0x6b << 0)
  60 #define QSPI_CMD_READ_QUAD              (0x6c << 0)
  61 #define QSPI_CMD_READ_FAST              (0x0b << 0)
  62 #define QSPI_SETUP0_NUM_A_BYTES         (0x3 << 8)
  63 #define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
  64 #define QSPI_SETUP0_NUM_D_BYTES_8_BITS  (0x1 << 10)
  65 #define QSPI_SETUP0_READ_NORMAL         (0x0 << 12)
  66 #define QSPI_SETUP0_READ_DUAL           (0x1 << 12)
  67 #define QSPI_SETUP0_READ_QUAD           (0x3 << 12)
  68 #define QSPI_CMD_WRITE                  (0x12 << 16)
  69 #define QSPI_NUM_DUMMY_BITS             (0x0 << 24)
  70
  71 /* ti qspi register set */
  72 struct ti_qspi_regs {
  73         u32 pid;
  74         u32 pad0[3];
  75         u32 sysconfig;
  76         u32 pad1[3];
  77         u32 int_stat_raw;
  78         u32 int_stat_en;
  79         u32 int_en_set;
  80         u32 int_en_ctlr;
  81         u32 intc_eoi;
  82         u32 pad2[3];
  83         u32 clk_ctrl;
  84         u32 dc;
  85         u32 cmd;
  86         u32 status;
  87         u32 data;
  88         u32 setup0;
  89         u32 setup1;
  90         u32 setup2;
  91         u32 setup3;
  92         u32 memswitch;
  93         u32 data1;
  94         u32 data2;
  95         u32 data3;
  96 };
  97
  98 /* ti qspi priv */
  99 struct ti_qspi_priv {
 100 #ifndef CONFIG_DM_SPI
 101         struct spi_slave slave;
 102 #else
 103         void *memory_map;
 104         uint max_hz;
 105         u32 num_cs;
 106 #endif
 107         struct ti_qspi_regs *base;
 108         void *ctrl_mod_mmap;
 109         ulong fclk;
 110         unsigned int mode;
 111         u32 cmd;
 112         u32 dc;
 113 };
 114
 115 static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 116 {
 117         uint clk_div;
 118
 119         if (!hz)
 120                 clk_div = 0;
 121         else
 122                 clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 123
 124         /* truncate clk_div value to QSPI_CLK_DIV_MAX */
 125         if (clk_div > QSPI_CLK_DIV_MAX)
 126                 clk_div = QSPI_CLK_DIV_MAX;
 127
 128         debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
 129
 130         /* disable SCLK */
 131         writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 132                &priv->base->clk_ctrl);
 133         /* enable SCLK and program the clk divider */
 134         writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 135 }
 136
 137 static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
 138 {
 139         writel(priv->cmd | QSPI_INVAL, &priv->base->cmd);
 140         /* dummy readl to ensure bus sync */
 141         readl(&priv->base->cmd);
 142 }
 143
 144 static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
 145 {
 146         priv->dc = 0;
 147         if (mode & SPI_CPHA)
 148                 priv->dc |= QSPI_CKPHA(0);
 149         if (mode & SPI_CPOL)
 150                 priv->dc |= QSPI_CKPOL(0);
 151         if (mode & SPI_CS_HIGH)
 152                 priv->dc |= QSPI_CSPOL(0);
 153
 154         return 0;
 155 }
 156
 157 static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
 158 {
 159         writel(priv->dc, &priv->base->dc);
 160         writel(0, &priv->base->cmd);
 161         writel(0, &priv->base->data);
 162
 163         priv->dc <<= cs * 8;
 164         writel(priv->dc, &priv->base->dc);
 165
 166         return 0;
 167 }
 168
 169 static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
 170 {
 171         writel(0, &priv->base->dc);
 172         writel(0, &priv->base->cmd);
 173         writel(0, &priv->base->data);
 174 }
 175
 176 static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
 177 {
 178         u32 val;
 179
 180         val = readl(ctrl_mod_mmap);
 181         if (enable)
 182                 val |= MEM_CS(cs);
 183         else
 184                 val &= MEM_CS_UNSELECT;
 185         writel(val, ctrl_mod_mmap);
 186 }
 187
 188 static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
 189                         const void *dout, void *din, unsigned long flags,
 190                         u32 cs)
 191 {
 192         uint words = bitlen >> 3; /* fixed 8-bit word length */
 193         const uchar *txp = dout;
 194         uchar *rxp = din;
 195         uint status;
 196         int timeout;
 197
 198         /* Setup mmap flags */
 199         if (flags & SPI_XFER_MMAP) {
 200                 writel(MM_SWITCH, &priv->base->memswitch);
 201                 if (priv->ctrl_mod_mmap)
 202                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
 203                 return 0;
 204         } else if (flags & SPI_XFER_MMAP_END) {
 205                 writel(~MM_SWITCH, &priv->base->memswitch);
 206                 if (priv->ctrl_mod_mmap)
 207                         ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
 208                 return 0;
 209         }
 210
 211         if (bitlen == 0)
 212                 return -1;
 213
 214         if (bitlen % 8) {
 215                 debug("spi_xfer: Non byte aligned SPI transfer\n");
 216                 return -1;
 217         }
 218
 219         /* Setup command reg */
 220         priv->cmd = 0;
 221         priv->cmd |= QSPI_WLEN(8);
 222         priv->cmd |= QSPI_EN_CS(cs);
 223         if (priv->mode & SPI_3WIRE)
 224                 priv->cmd |= QSPI_3_PIN;
 225         priv->cmd |= 0xfff;
 226
 227         while (words) {
 228                 u8 xfer_len = 0;
 229
 230                 if (txp) {
 231                         u32 cmd = priv->cmd;
 232
 233                         if (words >= QSPI_WLEN_MAX_BYTES) {
 234                                 u32 *txbuf = (u32 *)txp;
 235                                 u32 data;
 236
 237                                 data = cpu_to_be32(*txbuf++);
 238                                 writel(data, &priv->base->data3);
 239                                 data = cpu_to_be32(*txbuf++);
 240                                 writel(data, &priv->base->data2);
 241                                 data = cpu_to_be32(*txbuf++);
 242                                 writel(data, &priv->base->data1);
 243                                 data = cpu_to_be32(*txbuf++);
 244                                 writel(data, &priv->base->data);
 245                                 cmd &= ~QSPI_WLEN_MASK;
 246                                 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS);
 247                                 xfer_len = QSPI_WLEN_MAX_BYTES;
 248                         } else {
 249                                 writeb(*txp, &priv->base->data);
 250                                 xfer_len = 1;
 251                         }
 252                         debug("tx cmd %08x dc %08x\n",
 253                               cmd | QSPI_WR_SNGL, priv->dc);
 254                         writel(cmd | QSPI_WR_SNGL, &priv->base->cmd);
 255                         status = readl(&priv->base->status);
 256                         timeout = QSPI_TIMEOUT;
 257                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 258                                 if (--timeout < 0) {
 259                                         printf("spi_xfer: TX timeout!\n");
 260                                         return -1;
 261                                 }
 262                                 status = readl(&priv->base->status);
 263                         }
 264                         txp += xfer_len;
 265                         debug("tx done, status %08x\n", status);
 266                 }
 267                 if (rxp) {
 268                         debug("rx cmd %08x dc %08x\n",
 269                               ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc);
 270                         writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd);
 271                         status = readl(&priv->base->status);
 272                         timeout = QSPI_TIMEOUT;
 273                         while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
 274                                 if (--timeout < 0) {
 275                                         printf("spi_xfer: RX timeout!\n");
 276                                         return -1;
 277                                 }
 278                                 status = readl(&priv->base->status);
 279                         }
 280                         *rxp++ = readl(&priv->base->data);
 281                         xfer_len = 1;
 282                         debug("rx done, status %08x, read %02x\n",
 283                               status, *(rxp-1));
 284                 }
 285                 words -= xfer_len;
 286         }
 287
 288         /* Terminate frame */
 289         if (flags & SPI_XFER_END)
 290                 ti_qspi_cs_deactivate(priv);
 291
 292         return 0;
 293 }
 294
 295 /* TODO: control from sf layer to here through dm-spi */
 296 #if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
 297 void spi_flash_copy_mmap(void *data, void *offset, size_t len)
 298 {
 299         unsigned int                    addr = (unsigned int) (data);
 300         unsigned int                    edma_slot_num = 1;
 301
 302         /* Invalidate the area, so no writeback into the RAM races with DMA */
 303         invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
 304
 305         /* enable edma3 clocks */
 306         enable_edma3_clocks();
 307
 308         /* Call edma3 api to do actual DMA transfer     */
 309         edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
 310
 311         /* disable edma3 clocks */
 312         disable_edma3_clocks();
 313
 314         *((unsigned int *)offset) += len;
 315 }
 316 #endif
 317
 318 #ifndef CONFIG_DM_SPI
 319
 320 static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
 321 {
 322         return container_of(slave, struct ti_qspi_priv, slave);
 323 }
 324
 325 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 326 {
 327         return 1;
 328 }
 329
 330 void spi_cs_activate(struct spi_slave *slave)
 331 {
 332         /* CS handled in xfer */
 333         return;
 334 }
 335
 336 void spi_cs_deactivate(struct spi_slave *slave)
 337 {
 338         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 339         ti_qspi_cs_deactivate(priv);
 340 }
 341
 342 void spi_init(void)
 343 {
 344         /* nothing to do */
 345 }
 346
 347 static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
 348 {
 349         u32 memval = 0;
 350
 351 #ifdef CONFIG_QSPI_QUAD_SUPPORT
 352         struct spi_slave *slave = &priv->slave;
 353         memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
 354                         QSPI_SETUP0_NUM_D_BYTES_8_BITS |
 355                         QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
 356                         QSPI_NUM_DUMMY_BITS);
 357         slave->mode |= SPI_RX_QUAD;
 358 #else
 359         memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
 360                         QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
 361                         QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
 362                         QSPI_NUM_DUMMY_BITS;
 363 #endif
 364
 365         writel(memval, &priv->base->setup0);
 366 }
 367
 368 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 369                                   unsigned int max_hz, unsigned int mode)
 370 {
 371         struct ti_qspi_priv *priv;
 372
 373 #ifdef CONFIG_AM43XX
 374         gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
 375         gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
 376 #endif
 377
 378         priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
 379         if (!priv) {
 380                 printf("SPI_error: Fail to allocate ti_qspi_priv\n");
 381                 return NULL;
 382         }
 383
 384         priv->base = (struct ti_qspi_regs *)QSPI_BASE;
 385         priv->mode = mode;
 386 #if defined(CONFIG_DRA7XX)
 387         priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
 388         priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
 389         priv->fclk = QSPI_DRA7XX_FCLK;
 390 #else
 391         priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
 392         priv->fclk = QSPI_FCLK;
 393 #endif
 394
 395         ti_spi_set_speed(priv, max_hz);
 396
 397 #ifdef CONFIG_TI_SPI_MMAP
 398         ti_spi_setup_spi_register(priv);
 399 #endif
 400
 401         return &priv->slave;
 402 }
 403
 404 void spi_free_slave(struct spi_slave *slave)
 405 {
 406         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 407         free(priv);
 408 }
 409
 410 int spi_claim_bus(struct spi_slave *slave)
 411 {
 412         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 413
 414         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 415         __ti_qspi_set_mode(priv, priv->mode);
 416         return __ti_qspi_claim_bus(priv, priv->slave.cs);
 417 }
 418 void spi_release_bus(struct spi_slave *slave)
 419 {
 420         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 421
 422         debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
 423         __ti_qspi_release_bus(priv);
 424 }
 425
 426 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 427              void *din, unsigned long flags)
 428 {
 429         struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
 430
 431         debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
 432               priv->slave.bus, priv->slave.cs, bitlen, flags);
 433         return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
 434 }
 435
 436 #else /* CONFIG_DM_SPI */
 437
 438 static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
 439                                       struct spi_slave *slave,
 440                                       bool enable)
 441 {
 442         u32 memval;
 443         u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
 444
 445         if (!enable) {
 446                 writel(0, &priv->base->setup0);
 447                 return;
 448         }
 449
 450         memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
 451
 452         switch (mode) {
 453         case SPI_RX_QUAD:
 454                 memval |= QSPI_CMD_READ_QUAD;
 455                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 456                 memval |= QSPI_SETUP0_READ_QUAD;
 457                 slave->mode |= SPI_RX_QUAD;
 458                 break;
 459         case SPI_RX_DUAL:
 460                 memval |= QSPI_CMD_READ_DUAL;
 461                 memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
 462                 memval |= QSPI_SETUP0_READ_DUAL;
 463                 break;
 464         default:
 465                 memval |= QSPI_CMD_READ;
 466                 memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
 467                 memval |= QSPI_SETUP0_READ_NORMAL;
 468                 break;
 469         }
 470
 471         writel(memval, &priv->base->setup0);
 472 }
 473
 474
 475 static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
 476 {
 477         struct ti_qspi_priv *priv = dev_get_priv(bus);
 478
 479         ti_spi_set_speed(priv, max_hz);
 480
 481         return 0;
 482 }
 483
 484 static int ti_qspi_set_mode(struct udevice *bus, uint mode)
 485 {
 486         struct ti_qspi_priv *priv = dev_get_priv(bus);
 487         return __ti_qspi_set_mode(priv, mode);
 488 }
 489
 490 static int ti_qspi_claim_bus(struct udevice *dev)
 491 {
 492         struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
 493         struct spi_slave *slave = dev_get_parent_priv(dev);
 494         struct ti_qspi_priv *priv;
 495         struct udevice *bus;
 496
 497         bus = dev->parent;
 498         priv = dev_get_priv(bus);
 499
 500         if (slave_plat->cs > priv->num_cs) {
 501                 debug("invalid qspi chip select\n");
 502                 return -EINVAL;
 503         }
 504
 505         __ti_qspi_setup_memorymap(priv, slave, true);
 506
 507         return __ti_qspi_claim_bus(priv, slave_plat->cs);
 508 }
 509
 510 static int ti_qspi_release_bus(struct udevice *dev)
 511 {
 512         struct spi_slave *slave = dev_get_parent_priv(dev);
 513         struct ti_qspi_priv *priv;
 514         struct udevice *bus;
 515
 516         bus = dev->parent;
 517         priv = dev_get_priv(bus);
 518
 519         __ti_qspi_setup_memorymap(priv, slave, false);
 520         __ti_qspi_release_bus(priv);
 521
 522         return 0;
 523 }
 524
 525 static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
 526                         const void *dout, void *din, unsigned long flags)
 527 {
 528         struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
 529         struct ti_qspi_priv *priv;
 530         struct udevice *bus;
 531
 532         bus = dev->parent;
 533         priv = dev_get_priv(bus);
 534
 535         if (slave->cs > priv->num_cs) {
 536                 debug("invalid qspi chip select\n");
 537                 return -EINVAL;
 538         }
 539
 540         return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
 541 }
 542
 543 static int ti_qspi_probe(struct udevice *bus)
 544 {
 545         struct ti_qspi_priv *priv = dev_get_priv(bus);
 546
 547         priv->fclk = dev_get_driver_data(bus);
 548
 549         return 0;
 550 }
 551
 552 static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
 553 {
 554         struct ti_qspi_priv *priv = dev_get_priv(bus);
 555         const void *blob = gd->fdt_blob;
 556         int node = dev_of_offset(bus);
 557         fdt_addr_t addr;
 558         void *mmap;
 559
 560         priv->base = map_physmem(dev_get_addr(bus), sizeof(struct ti_qspi_regs),
 561                                  MAP_NOCACHE);
 562         priv->memory_map = map_physmem(dev_get_addr_index(bus, 1), 0,
 563                                        MAP_NOCACHE);
 564         addr = dev_get_addr_index(bus, 2);
 565         mmap = map_physmem(dev_get_addr_index(bus, 2), 0, MAP_NOCACHE);
 566         priv->ctrl_mod_mmap = (addr == FDT_ADDR_T_NONE) ? NULL : mmap;
 567
 568         priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
 569         if (priv->max_hz < 0) {
 570                 debug("Error: Max frequency missing\n");
 571                 return -ENODEV;
 572         }
 573         priv->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
 574
 575         debug("%s: regs=<0x%x>, max-frequency=%d\n", __func__,
 576               (int)priv->base, priv->max_hz);
 577
 578         return 0;
 579 }
 580
 581 static int ti_qspi_child_pre_probe(struct udevice *dev)
 582 {
 583         struct spi_slave *slave = dev_get_parent_priv(dev);
 584         struct udevice *bus = dev_get_parent(dev);
 585         struct ti_qspi_priv *priv = dev_get_priv(bus);
 586
 587         slave->memory_map = priv->memory_map;
 588         return 0;
 589 }
 590
 591 static const struct dm_spi_ops ti_qspi_ops = {
 592         .claim_bus      = ti_qspi_claim_bus,
 593         .release_bus    = ti_qspi_release_bus,
 594         .xfer           = ti_qspi_xfer,
 595         .set_speed      = ti_qspi_set_speed,
 596         .set_mode       = ti_qspi_set_mode,
 597 };
 598
 599 static const struct udevice_id ti_qspi_ids[] = {
 600         { .compatible = "ti,dra7xxx-qspi",      .data = QSPI_DRA7XX_FCLK},
 601         { .compatible = "ti,am4372-qspi",       .data = QSPI_FCLK},
 602         { }
 603 };
 604
 605 U_BOOT_DRIVER(ti_qspi) = {
 606         .name   = "ti_qspi",
 607         .id     = UCLASS_SPI,
 608         .of_match = ti_qspi_ids,
 609         .ops    = &ti_qspi_ops,
 610         .ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
 611         .priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
 612         .probe  = ti_qspi_probe,
 613         .child_pre_probe = ti_qspi_child_pre_probe,
 614 };
 615 #endif /* CONFIG_DM_SPI */