drivers/video/mxsfb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX23/i.MX28 LCDIF driver
   4  *
   5  * Copyright (C) 2011-2013 Marek Vasut <[email protected]>
   6  */
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <env.h>
  11 #include <dm/device_compat.h>
  12 #include <linux/errno.h>
  13 #include <malloc.h>
  14 #include <video.h>
  15 #include <video_fb.h>
  16
  17 #include <asm/arch/clock.h>
  18 #include <asm/arch/imx-regs.h>
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/mach-imx/dma.h>
  21 #include <asm/io.h>
  22
  23 #include "videomodes.h"
  24
  25 #define PS2KHZ(ps)      (1000000000UL / (ps))
  26 #define HZ2PS(hz)       (1000000000UL / ((hz) / 1000))
  27
  28 #define BITS_PP         18
  29 #define BYTES_PP        4
  30
  31 struct mxs_dma_desc desc;
  32
  33 /**
  34  * mxsfb_system_setup() - Fine-tune LCDIF configuration
  35  *
  36  * This function is used to adjust the LCDIF configuration. This is usually
  37  * needed when driving the controller in System-Mode to operate an 8080 or
  38  * 6800 connected SmartLCD.
  39  */
  40 __weak void mxsfb_system_setup(void)
  41 {
  42 }
  43
  44 /*
  45  * ARIES M28EVK:
  46  * setenv videomode
  47  * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
  48  *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
  49  *
  50  * Freescale mx23evk/mx28evk with a Seiko 4.3'' WVGA panel:
  51  * setenv videomode
  52  * video=ctfb:x:800,y:480,depth:24,mode:0,pclk:29851,
  53  *       le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0
  54  */
  55
  56 static void mxs_lcd_init(struct udevice *dev, u32 fb_addr,
  57                          struct display_timing *timings, int bpp)
  58 {
  59         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  60         const enum display_flags flags = timings->flags;
  61         uint32_t word_len = 0, bus_width = 0;
  62         uint8_t valid_data = 0;
  63         uint32_t vdctrl0;
  64
  65 #if CONFIG_IS_ENABLED(CLK)
  66         struct clk per_clk;
  67         int ret;
  68
  69         ret = clk_get_by_name(dev, "per", &per_clk);
  70         if (ret) {
  71                 dev_err(dev, "Failed to get mxs clk: %d\n", ret);
  72                 return;
  73         }
  74
  75         ret = clk_set_rate(&per_clk, timings->pixelclock.typ);
  76         if (ret < 0) {
  77                 dev_err(dev, "Failed to set mxs clk: %d\n", ret);
  78                 return;
  79         }
  80 #else
  81         /* Kick in the LCDIF clock */
  82         mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000);
  83 #endif
  84
  85         /* Restart the LCDIF block */
  86         mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
  87
  88         switch (bpp) {
  89         case 24:
  90                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  91                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
  92                 valid_data = 0x7;
  93                 break;
  94         case 18:
  95                 word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
  96                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
  97                 valid_data = 0x7;
  98                 break;
  99         case 16:
 100                 word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
 101                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
 102                 valid_data = 0xf;
 103                 break;
 104         case 8:
 105                 word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
 106                 bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
 107                 valid_data = 0xf;
 108                 break;
 109         }
 110
 111         writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
 112                 LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
 113                 &regs->hw_lcdif_ctrl);
 114
 115         writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
 116                 &regs->hw_lcdif_ctrl1);
 117
 118         mxsfb_system_setup();
 119
 120         writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
 121                 timings->hactive.typ, &regs->hw_lcdif_transfer_count);
 122
 123         vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
 124                   LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
 125                   LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
 126                   timings->vsync_len.typ;
 127
 128         if(flags & DISPLAY_FLAGS_HSYNC_HIGH)
 129                 vdctrl0 |= LCDIF_VDCTRL0_HSYNC_POL;
 130         writel(vdctrl0, &regs->hw_lcdif_vdctrl0);
 131         writel(timings->vback_porch.typ + timings->vfront_porch.typ +
 132                 timings->vsync_len.typ + timings->vactive.typ,
 133                 &regs->hw_lcdif_vdctrl1);
 134         writel((timings->hsync_len.typ << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
 135                 (timings->hback_porch.typ + timings->hfront_porch.typ +
 136                 timings->hsync_len.typ + timings->hactive.typ),
 137                 &regs->hw_lcdif_vdctrl2);
 138         writel(((timings->hback_porch.typ + timings->hsync_len.typ) <<
 139                 LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
 140                 (timings->vback_porch.typ + timings->vsync_len.typ),
 141                 &regs->hw_lcdif_vdctrl3);
 142         writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | timings->hactive.typ,
 143                 &regs->hw_lcdif_vdctrl4);
 144
 145         writel(fb_addr, &regs->hw_lcdif_cur_buf);
 146         writel(fb_addr, &regs->hw_lcdif_next_buf);
 147
 148         /* Flush FIFO first */
 149         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
 150
 151 #ifndef CONFIG_VIDEO_MXS_MODE_SYSTEM
 152         /* Sync signals ON */
 153         setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
 154 #endif
 155
 156         /* FIFO cleared */
 157         writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
 158
 159         /* RUN! */
 160         writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
 161 }
 162
 163 static int mxs_probe_common(struct udevice *dev, struct display_timing *timings,
 164                             int bpp, u32 fb)
 165 {
 166         /* Start framebuffer */
 167         mxs_lcd_init(dev, fb, timings, bpp);
 168
 169 #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM
 170         /*
 171          * If the LCD runs in system mode, the LCD refresh has to be triggered
 172          * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid
 173          * having to set this bit manually after every single change in the
 174          * framebuffer memory, we set up specially crafted circular DMA, which
 175          * sets the RUN bit, then waits until it gets cleared and repeats this
 176          * infinitelly. This way, we get smooth continuous updates of the LCD.
 177          */
 178         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 179
 180         memset(&desc, 0, sizeof(struct mxs_dma_desc));
 181         desc.address = (dma_addr_t)&desc;
 182         desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
 183                         MXS_DMA_DESC_WAIT4END |
 184                         (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
 185         desc.cmd.pio_words[0] = readl(&regs->hw_lcdif_ctrl) | LCDIF_CTRL_RUN;
 186         desc.cmd.next = (uint32_t)&desc.cmd;
 187
 188         /* Execute the DMA chain. */
 189         mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc);
 190 #endif
 191
 192         return 0;
 193 }
 194
 195 static int mxs_remove_common(u32 fb)
 196 {
 197         struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
 198         int timeout = 1000000;
 199
 200         if (!fb)
 201                 return -EINVAL;
 202
 203         writel(fb, &regs->hw_lcdif_cur_buf_reg);
 204         writel(fb, &regs->hw_lcdif_next_buf_reg);
 205         writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr);
 206         while (--timeout) {
 207                 if (readl(&regs->hw_lcdif_ctrl1_reg) &
 208                     LCDIF_CTRL1_VSYNC_EDGE_IRQ)
 209                         break;
 210                 udelay(1);
 211         }
 212         mxs_reset_block((struct mxs_register_32 *)&regs->hw_lcdif_ctrl_reg);
 213
 214         return 0;
 215 }
 216
 217 #ifndef CONFIG_DM_VIDEO
 218
 219 static GraphicDevice panel;
 220
 221 void lcdif_power_down(void)
 222 {
 223         mxs_remove_common(panel.frameAdrs);
 224 }
 225
 226 void *video_hw_init(void)
 227 {
 228         int bpp = -1;
 229         int ret = 0;
 230         char *penv;
 231         void *fb = NULL;
 232         struct ctfb_res_modes mode;
 233         struct display_timing timings;
 234
 235         puts("Video: ");
 236
 237         /* Suck display configuration from "videomode" variable */
 238         penv = env_get("videomode");
 239         if (!penv) {
 240                 puts("MXSFB: 'videomode' variable not set!\n");
 241                 return NULL;
 242         }
 243
 244         bpp = video_get_params(&mode, penv);
 245
 246         /* fill in Graphic device struct */
 247         sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
 248
 249         panel.winSizeX = mode.xres;
 250         panel.winSizeY = mode.yres;
 251         panel.plnSizeX = mode.xres;
 252         panel.plnSizeY = mode.yres;
 253
 254         switch (bpp) {
 255         case 24:
 256         case 18:
 257                 panel.gdfBytesPP = 4;
 258                 panel.gdfIndex = GDF_32BIT_X888RGB;
 259                 break;
 260         case 16:
 261                 panel.gdfBytesPP = 2;
 262                 panel.gdfIndex = GDF_16BIT_565RGB;
 263                 break;
 264         case 8:
 265                 panel.gdfBytesPP = 1;
 266                 panel.gdfIndex = GDF__8BIT_INDEX;
 267                 break;
 268         default:
 269                 printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
 270                 return NULL;
 271         }
 272
 273         panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
 274
 275         /* Allocate framebuffer */
 276         fb = memalign(ARCH_DMA_MINALIGN,
 277                       roundup(panel.memSize, ARCH_DMA_MINALIGN));
 278         if (!fb) {
 279                 printf("MXSFB: Error allocating framebuffer!\n");
 280                 return NULL;
 281         }
 282
 283         /* Wipe framebuffer */
 284         memset(fb, 0, panel.memSize);
 285
 286         panel.frameAdrs = (u32)fb;
 287
 288         printf("%s\n", panel.modeIdent);
 289
 290         video_ctfb_mode_to_display_timing(&mode, &timings);
 291
 292         ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
 293         if (ret)
 294                 goto dealloc_fb;
 295
 296         return (void *)&panel;
 297
 298 dealloc_fb:
 299         free(fb);
 300
 301         return NULL;
 302 }
 303 #else /* ifndef CONFIG_DM_VIDEO */
 304
 305 static int mxs_of_get_timings(struct udevice *dev,
 306                               struct display_timing *timings,
 307                               u32 *bpp)
 308 {
 309         int ret = 0;
 310         u32 display_phandle;
 311         ofnode display_node;
 312
 313         ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle);
 314         if (ret) {
 315                 dev_err(dev, "required display property isn't provided\n");
 316                 return -EINVAL;
 317         }
 318
 319         display_node = ofnode_get_by_phandle(display_phandle);
 320         if (!ofnode_valid(display_node)) {
 321                 dev_err(dev, "failed to find display subnode\n");
 322                 return -EINVAL;
 323         }
 324
 325         ret = ofnode_read_u32(display_node, "bits-per-pixel", bpp);
 326         if (ret) {
 327                 dev_err(dev,
 328                         "required bits-per-pixel property isn't provided\n");
 329                 return -EINVAL;
 330         }
 331
 332         ret = ofnode_decode_display_timing(display_node, 0, timings);
 333         if (ret) {
 334                 dev_err(dev, "failed to get any display timings\n");
 335                 return -EINVAL;
 336         }
 337
 338         return ret;
 339 }
 340
 341 static int mxs_video_probe(struct udevice *dev)
 342 {
 343         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 344         struct video_priv *uc_priv = dev_get_uclass_priv(dev);
 345
 346         struct display_timing timings;
 347         u32 bpp = 0;
 348         u32 fb_start, fb_end;
 349         int ret;
 350
 351         debug("%s() plat: base 0x%lx, size 0x%x\n",
 352                __func__, plat->base, plat->size);
 353
 354         ret = mxs_of_get_timings(dev, &timings, &bpp);
 355         if (ret)
 356                 return ret;
 357
 358         ret = mxs_probe_common(dev, &timings, bpp, plat->base);
 359         if (ret)
 360                 return ret;
 361
 362         switch (bpp) {
 363         case 32:
 364         case 24:
 365         case 18:
 366                 uc_priv->bpix = VIDEO_BPP32;
 367                 break;
 368         case 16:
 369                 uc_priv->bpix = VIDEO_BPP16;
 370                 break;
 371         case 8:
 372                 uc_priv->bpix = VIDEO_BPP8;
 373                 break;
 374         default:
 375                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 376                 return -EINVAL;
 377         }
 378
 379         uc_priv->xsize = timings.hactive.typ;
 380         uc_priv->ysize = timings.vactive.typ;
 381
 382         /* Enable dcache for the frame buffer */
 383         fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
 384         fb_end = plat->base + plat->size;
 385         fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
 386         mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
 387                                         DCACHE_WRITEBACK);
 388         video_set_flush_dcache(dev, true);
 389         gd->fb_base = plat->base;
 390
 391         return ret;
 392 }
 393
 394 static int mxs_video_bind(struct udevice *dev)
 395 {
 396         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 397         struct display_timing timings;
 398         u32 bpp = 0;
 399         u32 bytes_pp = 0;
 400         int ret;
 401
 402         ret = mxs_of_get_timings(dev, &timings, &bpp);
 403         if (ret)
 404                 return ret;
 405
 406         switch (bpp) {
 407         case 32:
 408         case 24:
 409         case 18:
 410                 bytes_pp = 4;
 411                 break;
 412         case 16:
 413                 bytes_pp = 2;
 414                 break;
 415         case 8:
 416                 bytes_pp = 1;
 417                 break;
 418         default:
 419                 dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp);
 420                 return -EINVAL;
 421         }
 422
 423         plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp;
 424
 425         return 0;
 426 }
 427
 428 static int mxs_video_remove(struct udevice *dev)
 429 {
 430         struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
 431
 432         mxs_remove_common(plat->base);
 433
 434         return 0;
 435 }
 436
 437 static const struct udevice_id mxs_video_ids[] = {
 438         { .compatible = "fsl,imx23-lcdif" },
 439         { .compatible = "fsl,imx28-lcdif" },
 440         { .compatible = "fsl,imx7ulp-lcdif" },
 441         { .compatible = "fsl,imxrt-lcdif" },
 442         { /* sentinel */ }
 443 };
 444
 445 U_BOOT_DRIVER(mxs_video) = {
 446         .name   = "mxs_video",
 447         .id     = UCLASS_VIDEO,
 448         .of_match = mxs_video_ids,
 449         .bind   = mxs_video_bind,
 450         .probe  = mxs_video_probe,
 451         .remove = mxs_video_remove,
 452         .flags  = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
 453 };
 454 #endif /* ifndef CONFIG_DM_VIDEO */